53 	tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);  in tegra_dc_readl_active()
55 	tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);  in tegra_dc_readl_active()
92 	tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset));  in tegra_plane_writel()
122 	tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);  in tegra_dc_commit()
123 	tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);  in tegra_dc_commit()
949 	tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);  in __tegra_cursor_atomic_update()
953 	tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);  in __tegra_cursor_atomic_update()
959 	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);  in __tegra_cursor_atomic_update()
973 	tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);  in __tegra_cursor_atomic_update()
985 		tegra_dc_writel(dc, value, DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR);  in __tegra_cursor_atomic_update()
989 		tegra_dc_writel(dc, value, DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR);  in __tegra_cursor_atomic_update()
997 	tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);  in __tegra_cursor_atomic_update()
1024 	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);  in tegra_cursor_atomic_disable()
1082 		tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);  in tegra_cursor_atomic_async_update()
1086 		tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);  in tegra_cursor_atomic_async_update()
1677 	tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);  in tegra_dc_show_crc()
1686 	tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);  in tegra_dc_show_crc()
1773 	tegra_dc_writel(dc, value, DC_CMD_INT_MASK);  in tegra_dc_enable_vblank()
1785 	tegra_dc_writel(dc, value, DC_CMD_INT_MASK);  in tegra_dc_disable_vblank()
1810 		tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);  in tegra_dc_set_timings()
1813 		tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);  in tegra_dc_set_timings()
1818 	tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);  in tegra_dc_set_timings()
1822 	tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);  in tegra_dc_set_timings()
1826 	tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);  in tegra_dc_set_timings()
1829 	tegra_dc_writel(dc, value, DC_DISP_ACTIVE);  in tegra_dc_set_timings()
1953 	tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);  in tegra_dc_stop()
2116 		tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);  in tegra_crtc_atomic_disable()
2171 		tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);  in tegra_crtc_atomic_enable()
2174 		tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);  in tegra_crtc_atomic_enable()
2180 		tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);  in tegra_crtc_atomic_enable()
2187 		tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);  in tegra_crtc_atomic_enable()
2191 		tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);  in tegra_crtc_atomic_enable()
2194 		tegra_dc_writel(dc, value, DC_CMD_INT_MASK);  in tegra_crtc_atomic_enable()
2196 		tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);  in tegra_crtc_atomic_enable()
2200 		tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);  in tegra_crtc_atomic_enable()
2204 		tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);  in tegra_crtc_atomic_enable()
2209 		tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);  in tegra_crtc_atomic_enable()
2213 		tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);  in tegra_crtc_atomic_enable()
2217 		tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);  in tegra_crtc_atomic_enable()
2221 		tegra_dc_writel(dc, value, DC_CMD_INT_MASK);  in tegra_crtc_atomic_enable()
2225 		tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR);  in tegra_crtc_atomic_enable()
2227 		tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);  in tegra_crtc_atomic_enable()
2232 		tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);  in tegra_crtc_atomic_enable()
2242 		tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);  in tegra_crtc_atomic_enable()
2248 	tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);  in tegra_crtc_atomic_enable()
2254 		tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);  in tegra_crtc_atomic_enable()
2260 		tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW);  in tegra_crtc_atomic_enable()
2266 		tegra_dc_writel(dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS);  in tegra_crtc_atomic_enable()
2305 	tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);  in tegra_crtc_atomic_flush()
2309 	tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);  in tegra_crtc_atomic_flush()
2526 	tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);  in tegra_dc_irq()