Lines Matching full:dc
31 #include "dc.h"
49 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset) in tegra_dc_readl_active() argument
53 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
54 value = tegra_dc_readl(dc, offset); in tegra_dc_readl_active()
55 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
78 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset); in tegra_plane_offset()
86 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset)); in tegra_plane_readl()
92 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset)); in tegra_plane_writel()
95 bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev) in tegra_dc_has_output() argument
97 struct device_node *np = dc->dev->of_node; in tegra_dc_has_output()
120 void tegra_dc_commit(struct tegra_dc *dc) in tegra_dc_commit() argument
122 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); in tegra_dc_commit()
123 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); in tegra_dc_commit()
316 struct tegra_dc *dc = plane->dc; in tegra_plane_use_horizontal_filtering() local
321 if (plane->index == 0 && dc->soc->has_win_a_without_filters) in tegra_plane_use_horizontal_filtering()
331 struct tegra_dc *dc = plane->dc; in tegra_plane_use_vertical_filtering() local
336 if (plane->index == 0 && dc->soc->has_win_a_without_filters) in tegra_plane_use_vertical_filtering()
339 if (plane->index == 2 && dc->soc->has_win_c_without_vert_filter) in tegra_plane_use_vertical_filtering()
349 struct tegra_dc *dc = plane->dc; in tegra_dc_setup_window() local
426 if (dc->soc->supports_block_linear) { in tegra_dc_setup_window()
532 if (dc->soc->has_legacy_blending) in tegra_dc_setup_window()
628 struct tegra_dc *dc = to_tegra_dc(new_plane_state->crtc); in tegra_plane_atomic_check() local
652 if (dc->soc->has_legacy_blending) { in tegra_plane_atomic_check()
663 !dc->soc->supports_block_linear) { in tegra_plane_atomic_check()
803 struct tegra_dc *dc) in tegra_primary_plane_create() argument
820 plane->dc = dc; in tegra_primary_plane_create()
822 num_formats = dc->soc->num_primary_formats; in tegra_primary_plane_create()
823 formats = dc->soc->primary_formats; in tegra_primary_plane_create()
824 modifiers = dc->soc->modifiers; in tegra_primary_plane_create()
850 dev_err(dc->dev, "failed to create rotation property: %d\n", in tegra_primary_plane_create()
906 struct tegra_dc *dc = to_tegra_dc(new_state->crtc); in __tegra_cursor_atomic_update() local
909 u64 dma_mask = *dc->dev->dma_mask; in __tegra_cursor_atomic_update()
922 if (!dc->soc->has_nvdisplay) in __tegra_cursor_atomic_update()
949 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR); in __tegra_cursor_atomic_update()
953 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI); in __tegra_cursor_atomic_update()
957 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in __tegra_cursor_atomic_update()
959 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in __tegra_cursor_atomic_update()
961 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL); in __tegra_cursor_atomic_update()
965 if (dc->soc->has_nvdisplay) in __tegra_cursor_atomic_update()
973 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL); in __tegra_cursor_atomic_update()
976 if (dc->soc->has_nvdisplay) { in __tegra_cursor_atomic_update()
985 tegra_dc_writel(dc, value, DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR); in __tegra_cursor_atomic_update()
989 tegra_dc_writel(dc, value, DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR); in __tegra_cursor_atomic_update()
997 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION); in __tegra_cursor_atomic_update()
1013 struct tegra_dc *dc; in tegra_cursor_atomic_disable() local
1020 dc = to_tegra_dc(old_state->crtc); in tegra_cursor_atomic_disable()
1022 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_cursor_atomic_disable()
1024 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_cursor_atomic_disable()
1068 struct tegra_dc *dc = to_tegra_dc(new_state->crtc); in tegra_cursor_atomic_async_update() local
1082 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); in tegra_cursor_atomic_async_update()
1083 (void)tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); in tegra_cursor_atomic_async_update()
1086 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); in tegra_cursor_atomic_async_update()
1087 (void)tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); in tegra_cursor_atomic_async_update()
1107 struct tegra_dc *dc) in tegra_dc_cursor_plane_create() argument
1127 plane->dc = dc; in tegra_dc_cursor_plane_create()
1129 if (!dc->soc->has_nvdisplay) { in tegra_dc_cursor_plane_create()
1252 struct tegra_dc *dc, in tegra_dc_overlay_plane_create() argument
1269 plane->dc = dc; in tegra_dc_overlay_plane_create()
1271 num_formats = dc->soc->num_overlay_formats; in tegra_dc_overlay_plane_create()
1272 formats = dc->soc->overlay_formats; in tegra_dc_overlay_plane_create()
1304 dev_err(dc->dev, "failed to create rotation property: %d\n", in tegra_dc_overlay_plane_create()
1311 struct tegra_dc *dc) in tegra_dc_add_shared_planes() argument
1316 for (i = 0; i < dc->soc->num_wgrps; i++) { in tegra_dc_add_shared_planes()
1317 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i]; in tegra_dc_add_shared_planes()
1319 if (wgrp->dc == dc->pipe) { in tegra_dc_add_shared_planes()
1323 plane = tegra_shared_plane_create(drm, dc, in tegra_dc_add_shared_planes()
1345 struct tegra_dc *dc) in tegra_dc_add_planes() argument
1352 primary = tegra_primary_plane_create(drm, dc); in tegra_dc_add_planes()
1356 if (dc->soc->supports_cursor) in tegra_dc_add_planes()
1362 planes[i] = tegra_dc_overlay_plane_create(drm, dc, 1 + i, in tegra_dc_add_planes()
1639 struct tegra_dc *dc = node->info_ent->data; in tegra_dc_show_regs() local
1643 drm_modeset_lock(&dc->base.mutex, NULL); in tegra_dc_show_regs()
1645 if (!dc->base.state->active) { in tegra_dc_show_regs()
1654 offset, tegra_dc_readl(dc, offset)); in tegra_dc_show_regs()
1658 drm_modeset_unlock(&dc->base.mutex); in tegra_dc_show_regs()
1665 struct tegra_dc *dc = node->info_ent->data; in tegra_dc_show_crc() local
1669 drm_modeset_lock(&dc->base.mutex, NULL); in tegra_dc_show_crc()
1671 if (!dc->base.state->active) { in tegra_dc_show_crc()
1677 tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL); in tegra_dc_show_crc()
1678 tegra_dc_commit(dc); in tegra_dc_show_crc()
1680 drm_crtc_wait_one_vblank(&dc->base); in tegra_dc_show_crc()
1681 drm_crtc_wait_one_vblank(&dc->base); in tegra_dc_show_crc()
1683 value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM); in tegra_dc_show_crc()
1686 tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL); in tegra_dc_show_crc()
1689 drm_modeset_unlock(&dc->base.mutex); in tegra_dc_show_crc()
1696 struct tegra_dc *dc = node->info_ent->data; in tegra_dc_show_stats() local
1698 seq_printf(s, "frames: %lu\n", dc->stats.frames); in tegra_dc_show_stats()
1699 seq_printf(s, "vblank: %lu\n", dc->stats.vblank); in tegra_dc_show_stats()
1700 seq_printf(s, "underflow: %lu\n", dc->stats.underflow); in tegra_dc_show_stats()
1701 seq_printf(s, "overflow: %lu\n", dc->stats.overflow); in tegra_dc_show_stats()
1703 seq_printf(s, "frames total: %lu\n", dc->stats.frames_total); in tegra_dc_show_stats()
1704 seq_printf(s, "vblank total: %lu\n", dc->stats.vblank_total); in tegra_dc_show_stats()
1705 seq_printf(s, "underflow total: %lu\n", dc->stats.underflow_total); in tegra_dc_show_stats()
1706 seq_printf(s, "overflow total: %lu\n", dc->stats.overflow_total); in tegra_dc_show_stats()
1722 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_dc_late_register() local
1730 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), in tegra_dc_late_register()
1732 if (!dc->debugfs_files) in tegra_dc_late_register()
1736 dc->debugfs_files[i].data = dc; in tegra_dc_late_register()
1738 drm_debugfs_create_files(dc->debugfs_files, count, root, minor); in tegra_dc_late_register()
1747 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_dc_early_unregister() local
1749 drm_debugfs_remove_files(dc->debugfs_files, count, minor); in tegra_dc_early_unregister()
1750 kfree(dc->debugfs_files); in tegra_dc_early_unregister()
1751 dc->debugfs_files = NULL; in tegra_dc_early_unregister()
1756 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_dc_get_vblank_counter() local
1759 if (dc->syncpt && !dc->soc->has_nvdisplay) in tegra_dc_get_vblank_counter()
1760 return host1x_syncpt_read(dc->syncpt); in tegra_dc_get_vblank_counter()
1763 return (u32)drm_crtc_vblank_count(&dc->base); in tegra_dc_get_vblank_counter()
1768 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_dc_enable_vblank() local
1771 value = tegra_dc_readl(dc, DC_CMD_INT_MASK); in tegra_dc_enable_vblank()
1773 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_dc_enable_vblank()
1780 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_dc_disable_vblank() local
1783 value = tegra_dc_readl(dc, DC_CMD_INT_MASK); in tegra_dc_disable_vblank()
1785 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_dc_disable_vblank()
1802 static int tegra_dc_set_timings(struct tegra_dc *dc, in tegra_dc_set_timings() argument
1809 if (!dc->soc->has_nvdisplay) { in tegra_dc_set_timings()
1810 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS); in tegra_dc_set_timings()
1813 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC); in tegra_dc_set_timings()
1818 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH); in tegra_dc_set_timings()
1822 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH); in tegra_dc_set_timings()
1826 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH); in tegra_dc_set_timings()
1829 tegra_dc_writel(dc, value, DC_DISP_ACTIVE); in tegra_dc_set_timings()
1837 * @dc: display controller
1846 int tegra_dc_state_setup_clock(struct tegra_dc *dc, in tegra_dc_state_setup_clock() argument
1853 if (!clk_has_parent(dc->clk, clk)) in tegra_dc_state_setup_clock()
1863 static void tegra_dc_update_voltage_state(struct tegra_dc *dc, in tegra_dc_update_voltage_state() argument
1870 if (!dc->has_opp_table) in tegra_dc_update_voltage_state()
1874 rate = DIV_ROUND_UP(clk_get_rate(dc->clk) * 2, state->div + 2); in tegra_dc_update_voltage_state()
1877 opp = dev_pm_opp_find_freq_ceil(dc->dev, &rate); in tegra_dc_update_voltage_state()
1885 opp = dev_pm_opp_find_freq_floor(dc->dev, &rate); in tegra_dc_update_voltage_state()
1888 dev_err(dc->dev, "failed to find OPP for %luHz: %pe\n", in tegra_dc_update_voltage_state()
1903 err = dev_pm_genpd_set_performance_state(dc->dev, pstate); in tegra_dc_update_voltage_state()
1905 dev_err(dc->dev, "failed to set power domain state to %lu: %d\n", in tegra_dc_update_voltage_state()
1909 static void tegra_dc_set_clock_rate(struct tegra_dc *dc, in tegra_dc_set_clock_rate() argument
1914 err = clk_set_parent(dc->clk, state->clk); in tegra_dc_set_clock_rate()
1916 dev_err(dc->dev, "failed to set parent clock: %d\n", err); in tegra_dc_set_clock_rate()
1929 dev_err(dc->dev, in tegra_dc_set_clock_rate()
1933 err = clk_set_rate(dc->clk, state->pclk); in tegra_dc_set_clock_rate()
1935 dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n", in tegra_dc_set_clock_rate()
1936 dc->clk, state->pclk, err); in tegra_dc_set_clock_rate()
1939 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), in tegra_dc_set_clock_rate()
1943 tegra_dc_update_voltage_state(dc, state); in tegra_dc_set_clock_rate()
1946 static void tegra_dc_stop(struct tegra_dc *dc) in tegra_dc_stop() argument
1951 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); in tegra_dc_stop()
1953 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); in tegra_dc_stop()
1955 tegra_dc_commit(dc); in tegra_dc_stop()
1958 static bool tegra_dc_idle(struct tegra_dc *dc) in tegra_dc_idle() argument
1962 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND); in tegra_dc_idle()
1967 static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout) in tegra_dc_wait_idle() argument
1972 if (tegra_dc_idle(dc)) in tegra_dc_wait_idle()
1978 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n"); in tegra_dc_wait_idle()
1992 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_crtc_update_memory_bandwidth() local
1996 if (dc->soc->has_nvdisplay) in tegra_crtc_update_memory_bandwidth()
2031 if (tegra->dc != dc) in tegra_crtc_update_memory_bandwidth()
2057 * freq should go high before the DC changes are committed in tegra_crtc_update_memory_bandwidth()
2082 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_crtc_atomic_disable() local
2086 if (!tegra_dc_idle(dc)) { in tegra_crtc_atomic_disable()
2087 tegra_dc_stop(dc); in tegra_crtc_atomic_disable()
2093 tegra_dc_wait_idle(dc, 100); in tegra_crtc_atomic_disable()
2112 if (dc->rgb) { in tegra_crtc_atomic_disable()
2113 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); in tegra_crtc_atomic_disable()
2116 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); in tegra_crtc_atomic_disable()
2119 tegra_dc_stats_reset(&dc->stats); in tegra_crtc_atomic_disable()
2131 err = host1x_client_suspend(&dc->client); in tegra_crtc_atomic_disable()
2133 dev_err(dc->dev, "failed to suspend: %d\n", err); in tegra_crtc_atomic_disable()
2135 if (dc->has_opp_table) { in tegra_crtc_atomic_disable()
2136 err = dev_pm_genpd_set_performance_state(dc->dev, 0); in tegra_crtc_atomic_disable()
2138 dev_err(dc->dev, in tegra_crtc_atomic_disable()
2148 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_crtc_atomic_enable() local
2153 tegra_dc_set_clock_rate(dc, crtc_state); in tegra_crtc_atomic_enable()
2155 err = host1x_client_resume(&dc->client); in tegra_crtc_atomic_enable()
2157 dev_err(dc->dev, "failed to resume: %d\n", err); in tegra_crtc_atomic_enable()
2162 if (dc->syncpt) { in tegra_crtc_atomic_enable()
2163 u32 syncpt = host1x_syncpt_id(dc->syncpt), enable; in tegra_crtc_atomic_enable()
2165 if (dc->soc->has_nvdisplay) in tegra_crtc_atomic_enable()
2171 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); in tegra_crtc_atomic_enable()
2174 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC); in tegra_crtc_atomic_enable()
2177 if (dc->soc->has_nvdisplay) { in tegra_crtc_atomic_enable()
2180 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); in tegra_crtc_atomic_enable()
2187 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); in tegra_crtc_atomic_enable()
2191 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); in tegra_crtc_atomic_enable()
2194 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_crtc_atomic_enable()
2196 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); in tegra_crtc_atomic_enable()
2200 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); in tegra_crtc_atomic_enable()
2204 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); in tegra_crtc_atomic_enable()
2209 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY); in tegra_crtc_atomic_enable()
2213 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); in tegra_crtc_atomic_enable()
2217 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); in tegra_crtc_atomic_enable()
2221 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_crtc_atomic_enable()
2224 if (dc->soc->supports_background_color) in tegra_crtc_atomic_enable()
2225 tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR); in tegra_crtc_atomic_enable()
2227 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR); in tegra_crtc_atomic_enable()
2230 if (!dc->soc->has_nvdisplay) { in tegra_crtc_atomic_enable()
2232 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL); in tegra_crtc_atomic_enable()
2236 tegra_dc_set_timings(dc, mode); in tegra_crtc_atomic_enable()
2239 if (dc->soc->supports_interlacing) { in tegra_crtc_atomic_enable()
2240 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL); in tegra_crtc_atomic_enable()
2242 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL); in tegra_crtc_atomic_enable()
2245 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); in tegra_crtc_atomic_enable()
2248 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); in tegra_crtc_atomic_enable()
2250 if (!dc->soc->has_nvdisplay) { in tegra_crtc_atomic_enable()
2251 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); in tegra_crtc_atomic_enable()
2254 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); in tegra_crtc_atomic_enable()
2258 if (dc->soc->has_nvdisplay) { in tegra_crtc_atomic_enable()
2260 tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW); in tegra_crtc_atomic_enable()
2263 if (dc->rgb) { in tegra_crtc_atomic_enable()
2266 tegra_dc_writel(dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS); in tegra_crtc_atomic_enable()
2269 tegra_dc_commit(dc); in tegra_crtc_atomic_enable()
2301 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_crtc_atomic_flush() local
2305 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); in tegra_crtc_atomic_flush()
2306 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); in tegra_crtc_atomic_flush()
2309 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); in tegra_crtc_atomic_flush()
2310 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); in tegra_crtc_atomic_flush()
2383 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_crtc_calculate_memory_bandwidth() local
2395 if (dc->soc->has_nvdisplay) in tegra_crtc_calculate_memory_bandwidth()
2430 * overlapping planes, where "simultaneously" means areas where DC in tegra_crtc_calculate_memory_bandwidth()
2522 struct tegra_dc *dc = data; in tegra_dc_irq() local
2525 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS); in tegra_dc_irq()
2526 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS); in tegra_dc_irq()
2530 dev_dbg(dc->dev, "%s(): frame end\n", __func__); in tegra_dc_irq()
2532 dc->stats.frames_total++; in tegra_dc_irq()
2533 dc->stats.frames++; in tegra_dc_irq()
2538 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__); in tegra_dc_irq()
2540 drm_crtc_handle_vblank(&dc->base); in tegra_dc_irq()
2541 dc->stats.vblank_total++; in tegra_dc_irq()
2542 dc->stats.vblank++; in tegra_dc_irq()
2547 dev_dbg(dc->dev, "%s(): underflow\n", __func__); in tegra_dc_irq()
2549 dc->stats.underflow_total++; in tegra_dc_irq()
2550 dc->stats.underflow++; in tegra_dc_irq()
2555 dev_dbg(dc->dev, "%s(): overflow\n", __func__); in tegra_dc_irq()
2557 dc->stats.overflow_total++; in tegra_dc_irq()
2558 dc->stats.overflow++; in tegra_dc_irq()
2562 dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__); in tegra_dc_irq()
2563 dc->stats.underflow_total++; in tegra_dc_irq()
2564 dc->stats.underflow++; in tegra_dc_irq()
2570 static bool tegra_dc_has_window_groups(struct tegra_dc *dc) in tegra_dc_has_window_groups() argument
2574 if (!dc->soc->wgrps) in tegra_dc_has_window_groups()
2577 for (i = 0; i < dc->soc->num_wgrps; i++) { in tegra_dc_has_window_groups()
2578 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i]; in tegra_dc_has_window_groups()
2580 if (wgrp->dc == dc->pipe && wgrp->num_windows > 0) in tegra_dc_has_window_groups()
2601 struct tegra_dc *dc = host1x_client_to_dc(client); in tegra_dc_init() local
2608 * DC has been reset by now, so VBLANK syncpoint can be released in tegra_dc_init()
2611 host1x_syncpt_release_vblank_reservation(client, 26 + dc->pipe); in tegra_dc_init()
2618 if (!tegra_dc_has_window_groups(dc)) in tegra_dc_init()
2627 if (dc->soc->has_nvdisplay) in tegra_dc_init()
2630 dc->syncpt = host1x_syncpt_request(client, flags); in tegra_dc_init()
2631 if (!dc->syncpt) in tegra_dc_init()
2632 dev_warn(dc->dev, "failed to allocate syncpoint\n"); in tegra_dc_init()
2640 if (dc->soc->wgrps) in tegra_dc_init()
2641 primary = tegra_dc_add_shared_planes(drm, dc); in tegra_dc_init()
2643 primary = tegra_dc_add_planes(drm, dc); in tegra_dc_init()
2650 if (dc->soc->supports_cursor) { in tegra_dc_init()
2651 cursor = tegra_dc_cursor_plane_create(drm, dc); in tegra_dc_init()
2658 cursor = tegra_dc_overlay_plane_create(drm, dc, 2, true); in tegra_dc_init()
2665 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor, in tegra_dc_init()
2670 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs); in tegra_dc_init()
2676 if (dc->soc->pitch_align > tegra->pitch_align) in tegra_dc_init()
2677 tegra->pitch_align = dc->soc->pitch_align; in tegra_dc_init()
2680 if (dc->soc->has_nvdisplay) in tegra_dc_init()
2685 err = tegra_dc_rgb_init(drm, dc); in tegra_dc_init()
2687 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err); in tegra_dc_init()
2691 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0, in tegra_dc_init()
2692 dev_name(dc->dev), dc); in tegra_dc_init()
2694 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq, in tegra_dc_init()
2715 host1x_syncpt_put(dc->syncpt); in tegra_dc_init()
2722 struct tegra_dc *dc = host1x_client_to_dc(client); in tegra_dc_exit() local
2725 if (!tegra_dc_has_window_groups(dc)) in tegra_dc_exit()
2731 devm_free_irq(dc->dev, dc->irq, dc); in tegra_dc_exit()
2733 err = tegra_dc_rgb_exit(dc); in tegra_dc_exit()
2735 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err); in tegra_dc_exit()
2740 host1x_syncpt_put(dc->syncpt); in tegra_dc_exit()
2757 struct tegra_dc *dc = host1x_client_to_dc(client); in tegra_dc_runtime_suspend() local
2761 err = reset_control_assert(dc->rst); in tegra_dc_runtime_suspend()
2767 if (dc->soc->has_powergate) in tegra_dc_runtime_suspend()
2768 tegra_powergate_power_off(dc->powergate); in tegra_dc_runtime_suspend()
2770 clk_disable_unprepare(dc->clk); in tegra_dc_runtime_suspend()
2778 struct tegra_dc *dc = host1x_client_to_dc(client); in tegra_dc_runtime_resume() local
2788 if (dc->soc->has_powergate) { in tegra_dc_runtime_resume()
2789 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk, in tegra_dc_runtime_resume()
2790 dc->rst); in tegra_dc_runtime_resume()
2796 err = clk_prepare_enable(dc->clk); in tegra_dc_runtime_resume()
2802 err = reset_control_deassert(dc->rst); in tegra_dc_runtime_resume()
2812 clk_disable_unprepare(dc->clk); in tegra_dc_runtime_resume()
2945 .dc = 0,
2950 .dc = 1,
2955 .dc = 1,
2960 .dc = 2,
2965 .dc = 2,
2970 .dc = 2,
2996 .dc = 0,
3001 .dc = 1,
3006 .dc = 1,
3011 .dc = 2,
3016 .dc = 2,
3021 .dc = 2,
3046 .compatible = "nvidia,tegra194-dc",
3049 .compatible = "nvidia,tegra186-dc",
3052 .compatible = "nvidia,tegra210-dc",
3055 .compatible = "nvidia,tegra124-dc",
3058 .compatible = "nvidia,tegra114-dc",
3061 .compatible = "nvidia,tegra30-dc",
3064 .compatible = "nvidia,tegra20-dc",
3072 static int tegra_dc_parse_dt(struct tegra_dc *dc) in tegra_dc_parse_dt() argument
3078 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value); in tegra_dc_parse_dt()
3080 dev_err(dc->dev, "missing \"nvidia,head\" property\n"); in tegra_dc_parse_dt()
3095 if (np == dc->dev->of_node) { in tegra_dc_parse_dt()
3104 dc->pipe = value; in tegra_dc_parse_dt()
3111 struct tegra_dc *dc = dev_get_drvdata(dev); in tegra_dc_match_by_pipe() local
3114 return dc->pipe == pipe; in tegra_dc_match_by_pipe()
3117 static int tegra_dc_couple(struct tegra_dc *dc) in tegra_dc_couple() argument
3124 if (dc->soc->coupled_pm && dc->pipe == 1) { in tegra_dc_couple()
3128 companion = driver_find_device(dc->dev->driver, NULL, (const void *)0, in tegra_dc_couple()
3134 dc->client.parent = &parent->client; in tegra_dc_couple()
3136 dev_dbg(dc->dev, "coupled to %s\n", dev_name(companion)); in tegra_dc_couple()
3142 static int tegra_dc_init_opp_table(struct tegra_dc *dc) in tegra_dc_init_opp_table() argument
3147 err = devm_tegra_core_dev_init_opp_table(dc->dev, &opp_params); in tegra_dc_init_opp_table()
3152 dc->has_opp_table = false; in tegra_dc_init_opp_table()
3154 dc->has_opp_table = true; in tegra_dc_init_opp_table()
3162 struct tegra_dc *dc; in tegra_dc_probe() local
3171 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL); in tegra_dc_probe()
3172 if (!dc) in tegra_dc_probe()
3175 dc->soc = of_device_get_match_data(&pdev->dev); in tegra_dc_probe()
3177 INIT_LIST_HEAD(&dc->list); in tegra_dc_probe()
3178 dc->dev = &pdev->dev; in tegra_dc_probe()
3180 err = tegra_dc_parse_dt(dc); in tegra_dc_probe()
3184 err = tegra_dc_couple(dc); in tegra_dc_probe()
3188 dc->clk = devm_clk_get(&pdev->dev, NULL); in tegra_dc_probe()
3189 if (IS_ERR(dc->clk)) { in tegra_dc_probe()
3191 return PTR_ERR(dc->clk); in tegra_dc_probe()
3194 dc->rst = devm_reset_control_get(&pdev->dev, "dc"); in tegra_dc_probe()
3195 if (IS_ERR(dc->rst)) { in tegra_dc_probe()
3197 return PTR_ERR(dc->rst); in tegra_dc_probe()
3201 err = clk_prepare_enable(dc->clk); in tegra_dc_probe()
3207 err = reset_control_assert(dc->rst); in tegra_dc_probe()
3213 clk_disable_unprepare(dc->clk); in tegra_dc_probe()
3215 if (dc->soc->has_powergate) { in tegra_dc_probe()
3216 if (dc->pipe == 0) in tegra_dc_probe()
3217 dc->powergate = TEGRA_POWERGATE_DIS; in tegra_dc_probe()
3219 dc->powergate = TEGRA_POWERGATE_DISB; in tegra_dc_probe()
3221 tegra_powergate_power_off(dc->powergate); in tegra_dc_probe()
3224 err = tegra_dc_init_opp_table(dc); in tegra_dc_probe()
3228 dc->regs = devm_platform_ioremap_resource(pdev, 0); in tegra_dc_probe()
3229 if (IS_ERR(dc->regs)) in tegra_dc_probe()
3230 return PTR_ERR(dc->regs); in tegra_dc_probe()
3232 dc->irq = platform_get_irq(pdev, 0); in tegra_dc_probe()
3233 if (dc->irq < 0) in tegra_dc_probe()
3236 err = tegra_dc_rgb_probe(dc); in tegra_dc_probe()
3241 platform_set_drvdata(pdev, dc); in tegra_dc_probe()
3244 INIT_LIST_HEAD(&dc->client.list); in tegra_dc_probe()
3245 dc->client.ops = &dc_client_ops; in tegra_dc_probe()
3246 dc->client.dev = &pdev->dev; in tegra_dc_probe()
3248 err = host1x_client_register(&dc->client); in tegra_dc_probe()
3259 tegra_dc_rgb_remove(dc); in tegra_dc_probe()
3266 struct tegra_dc *dc = platform_get_drvdata(pdev); in tegra_dc_remove() local
3269 err = host1x_client_unregister(&dc->client); in tegra_dc_remove()
3276 err = tegra_dc_rgb_remove(dc); in tegra_dc_remove()
3289 .name = "tegra-dc",