Lines Matching +full:tcon +full:- +full:top
1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
11 #include <linux/media-bus-format.h>
48 drm_connector_list_iter_begin(encoder->dev, &iter); in sun4i_tcon_get_connector()
50 if (connector->encoder == encoder) { in sun4i_tcon_get_connector()
66 return -EINVAL; in sun4i_tcon_get_pixel_depth()
68 info = &connector->display_info; in sun4i_tcon_get_pixel_depth()
69 if (info->num_bus_formats != 1) in sun4i_tcon_get_pixel_depth()
70 return -EINVAL; in sun4i_tcon_get_pixel_depth()
72 switch (info->bus_formats[0]) { in sun4i_tcon_get_pixel_depth()
81 return -EINVAL; in sun4i_tcon_get_pixel_depth()
84 static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel, in sun4i_tcon_channel_set_status() argument
91 WARN_ON(!tcon->quirks->has_channel_0); in sun4i_tcon_channel_set_status()
92 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, in sun4i_tcon_channel_set_status()
95 clk = tcon->dclk; in sun4i_tcon_channel_set_status()
98 WARN_ON(!tcon->quirks->has_channel_1); in sun4i_tcon_channel_set_status()
99 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, in sun4i_tcon_channel_set_status()
102 clk = tcon->sclk1; in sun4i_tcon_channel_set_status()
118 static void sun4i_tcon_setup_lvds_phy(struct sun4i_tcon *tcon, in sun4i_tcon_setup_lvds_phy() argument
121 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun4i_tcon_setup_lvds_phy()
130 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA1_REG, in sun4i_tcon_setup_lvds_phy()
134 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA1_REG, in sun4i_tcon_setup_lvds_phy()
137 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun4i_tcon_setup_lvds_phy()
142 static void sun6i_tcon_setup_lvds_phy(struct sun4i_tcon *tcon, in sun6i_tcon_setup_lvds_phy() argument
147 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun6i_tcon_setup_lvds_phy()
154 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun6i_tcon_setup_lvds_phy()
159 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun6i_tcon_setup_lvds_phy()
168 regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun6i_tcon_setup_lvds_phy()
173 static void sun4i_tcon_lvds_set_status(struct sun4i_tcon *tcon, in sun4i_tcon_lvds_set_status() argument
178 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, in sun4i_tcon_lvds_set_status()
181 if (tcon->quirks->setup_lvds_phy) in sun4i_tcon_lvds_set_status()
182 tcon->quirks->setup_lvds_phy(tcon, encoder); in sun4i_tcon_lvds_set_status()
184 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, in sun4i_tcon_lvds_set_status()
189 void sun4i_tcon_set_status(struct sun4i_tcon *tcon, in sun4i_tcon_set_status() argument
196 switch (encoder->encoder_type) { in sun4i_tcon_set_status()
214 sun4i_tcon_lvds_set_status(tcon, encoder, false); in sun4i_tcon_set_status()
216 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, in sun4i_tcon_set_status()
221 sun4i_tcon_lvds_set_status(tcon, encoder, true); in sun4i_tcon_set_status()
223 sun4i_tcon_channel_set_status(tcon, channel, enabled); in sun4i_tcon_set_status()
226 void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable) in sun4i_tcon_enable_vblank() argument
239 regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG, mask, val); in sun4i_tcon_enable_vblank()
244 * This function is a helper for TCON output muxing. The TCON output
245 * muxing control register in earlier SoCs (without the TCON TOP block)
251 struct sun4i_drv *drv = drm->dev_private; in sun4i_get_tcon0()
252 struct sun4i_tcon *tcon; in sun4i_get_tcon0() local
254 list_for_each_entry(tcon, &drv->tcon_list, list) in sun4i_get_tcon0()
255 if (tcon->id == 0) in sun4i_get_tcon0()
256 return tcon; in sun4i_get_tcon0()
258 dev_warn(drm->dev, in sun4i_get_tcon0()
264 static void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel, in sun4i_tcon_set_mux() argument
267 int ret = -ENOTSUPP; in sun4i_tcon_set_mux()
269 if (tcon->quirks->set_mux) in sun4i_tcon_set_mux()
270 ret = tcon->quirks->set_mux(tcon, encoder); in sun4i_tcon_set_mux()
273 encoder->name, encoder->crtc->name, ret); in sun4i_tcon_set_mux()
279 int delay = mode->vtotal - mode->vdisplay; in sun4i_tcon_get_clk_delay()
281 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in sun4i_tcon_get_clk_delay()
285 delay -= 2; in sun4i_tcon_get_clk_delay()
289 DRM_DEBUG_DRIVER("TCON %d clock delay %u\n", channel, delay); in sun4i_tcon_get_clk_delay()
294 static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon, in sun4i_tcon0_mode_set_common() argument
298 clk_set_rate(tcon->dclk, mode->crtc_clock * 1000); in sun4i_tcon0_mode_set_common()
301 regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG, in sun4i_tcon0_mode_set_common()
302 SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) | in sun4i_tcon0_mode_set_common()
303 SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay)); in sun4i_tcon0_mode_set_common()
306 static void sun4i_tcon0_mode_set_dithering(struct sun4i_tcon *tcon, in sun4i_tcon0_mode_set_dithering() argument
322 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PR_REG, 0x11111111); in sun4i_tcon0_mode_set_dithering()
323 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PG_REG, 0x11111111); in sun4i_tcon0_mode_set_dithering()
324 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PB_REG, 0x11111111); in sun4i_tcon0_mode_set_dithering()
325 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LR_REG, 0x11111111); in sun4i_tcon0_mode_set_dithering()
326 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LG_REG, 0x11111111); in sun4i_tcon0_mode_set_dithering()
327 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LB_REG, 0x11111111); in sun4i_tcon0_mode_set_dithering()
328 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL0_REG, 0x01010000); in sun4i_tcon0_mode_set_dithering()
329 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL1_REG, 0x15151111); in sun4i_tcon0_mode_set_dithering()
330 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL2_REG, 0x57575555); in sun4i_tcon0_mode_set_dithering()
331 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL3_REG, 0x7f7f7777); in sun4i_tcon0_mode_set_dithering()
334 if (connector->display_info.bpc == 6) in sun4i_tcon0_mode_set_dithering()
337 if (connector->display_info.num_bus_formats == 1) in sun4i_tcon0_mode_set_dithering()
338 bus_format = connector->display_info.bus_formats[0]; in sun4i_tcon0_mode_set_dithering()
355 regmap_write(tcon->regs, SUN4I_TCON_FRM_CTL_REG, val); in sun4i_tcon0_mode_set_dithering()
358 static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon, in sun4i_tcon0_mode_set_cpu() argument
364 struct mipi_dsi_device *device = dsi->device; in sun4i_tcon0_mode_set_cpu()
365 u8 bpp = mipi_dsi_pixel_format_to_bpp(device->format); in sun4i_tcon0_mode_set_cpu()
366 u8 lanes = device->lanes; in sun4i_tcon0_mode_set_cpu()
370 tcon->dclk_min_div = SUN6I_DSI_TCON_DIV; in sun4i_tcon0_mode_set_cpu()
371 tcon->dclk_max_div = SUN6I_DSI_TCON_DIV; in sun4i_tcon0_mode_set_cpu()
373 sun4i_tcon0_mode_set_common(tcon, mode); in sun4i_tcon0_mode_set_cpu()
376 sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder)); in sun4i_tcon0_mode_set_cpu()
378 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, in sun4i_tcon0_mode_set_cpu()
382 regmap_write(tcon->regs, SUN4I_TCON_ECC_FIFO_REG, in sun4i_tcon0_mode_set_cpu()
385 regmap_write(tcon->regs, SUN4I_TCON0_CPU_IF_REG, in sun4i_tcon0_mode_set_cpu()
397 regmap_read(tcon->regs, SUN4I_TCON0_DCLK_REG, &tcon_div); in sun4i_tcon0_mode_set_cpu()
399 block_space = mode->htotal * bpp / (tcon_div * lanes); in sun4i_tcon0_mode_set_cpu()
400 block_space -= mode->hdisplay + 40; in sun4i_tcon0_mode_set_cpu()
402 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI0_REG, in sun4i_tcon0_mode_set_cpu()
404 SUN4I_TCON0_CPU_TRI0_BLOCK_SIZE(mode->hdisplay)); in sun4i_tcon0_mode_set_cpu()
406 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI1_REG, in sun4i_tcon0_mode_set_cpu()
407 SUN4I_TCON0_CPU_TRI1_BLOCK_NUM(mode->vdisplay)); in sun4i_tcon0_mode_set_cpu()
409 start_delay = (mode->crtc_vtotal - mode->crtc_vdisplay - 10 - 1); in sun4i_tcon0_mode_set_cpu()
410 start_delay = start_delay * mode->crtc_htotal * 149; in sun4i_tcon0_mode_set_cpu()
411 start_delay = start_delay / (mode->crtc_clock / 1000) / 8; in sun4i_tcon0_mode_set_cpu()
412 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI2_REG, in sun4i_tcon0_mode_set_cpu()
420 regmap_write(tcon->regs, SUN4I_TCON_SAFE_PERIOD_REG, in sun4i_tcon0_mode_set_cpu()
425 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, in sun4i_tcon0_mode_set_cpu()
429 static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon, in sun4i_tcon0_mode_set_lvds() argument
437 WARN_ON(!tcon->quirks->has_channel_0); in sun4i_tcon0_mode_set_lvds()
439 tcon->dclk_min_div = 7; in sun4i_tcon0_mode_set_lvds()
440 tcon->dclk_max_div = 7; in sun4i_tcon0_mode_set_lvds()
441 sun4i_tcon0_mode_set_common(tcon, mode); in sun4i_tcon0_mode_set_lvds()
444 sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder)); in sun4i_tcon0_mode_set_lvds()
448 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, in sun4i_tcon0_mode_set_lvds()
456 bp = mode->crtc_htotal - mode->crtc_hsync_start; in sun4i_tcon0_mode_set_lvds()
458 mode->crtc_htotal, bp); in sun4i_tcon0_mode_set_lvds()
461 regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG, in sun4i_tcon0_mode_set_lvds()
462 SUN4I_TCON0_BASIC1_H_TOTAL(mode->htotal) | in sun4i_tcon0_mode_set_lvds()
469 bp = mode->crtc_vtotal - mode->crtc_vsync_start; in sun4i_tcon0_mode_set_lvds()
471 mode->crtc_vtotal, bp); in sun4i_tcon0_mode_set_lvds()
474 regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG, in sun4i_tcon0_mode_set_lvds()
475 SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) | in sun4i_tcon0_mode_set_lvds()
484 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, reg); in sun4i_tcon0_mode_set_lvds()
487 if (!(mode->flags & DRM_MODE_FLAG_PHSYNC)) in sun4i_tcon0_mode_set_lvds()
490 if (!(mode->flags & DRM_MODE_FLAG_PVSYNC)) in sun4i_tcon0_mode_set_lvds()
493 regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val); in sun4i_tcon0_mode_set_lvds()
496 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, in sun4i_tcon0_mode_set_lvds()
501 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0xe0000000); in sun4i_tcon0_mode_set_lvds()
504 static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon, in sun4i_tcon0_mode_set_rgb() argument
509 const struct drm_display_info *info = &connector->display_info; in sun4i_tcon0_mode_set_rgb()
514 WARN_ON(!tcon->quirks->has_channel_0); in sun4i_tcon0_mode_set_rgb()
516 tcon->dclk_min_div = tcon->quirks->dclk_min_div; in sun4i_tcon0_mode_set_rgb()
517 tcon->dclk_max_div = 127; in sun4i_tcon0_mode_set_rgb()
518 sun4i_tcon0_mode_set_common(tcon, mode); in sun4i_tcon0_mode_set_rgb()
521 sun4i_tcon0_mode_set_dithering(tcon, connector); in sun4i_tcon0_mode_set_rgb()
525 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, in sun4i_tcon0_mode_set_rgb()
533 bp = mode->crtc_htotal - mode->crtc_hsync_start; in sun4i_tcon0_mode_set_rgb()
535 mode->crtc_htotal, bp); in sun4i_tcon0_mode_set_rgb()
538 regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG, in sun4i_tcon0_mode_set_rgb()
539 SUN4I_TCON0_BASIC1_H_TOTAL(mode->crtc_htotal) | in sun4i_tcon0_mode_set_rgb()
546 bp = mode->crtc_vtotal - mode->crtc_vsync_start; in sun4i_tcon0_mode_set_rgb()
548 mode->crtc_vtotal, bp); in sun4i_tcon0_mode_set_rgb()
551 regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG, in sun4i_tcon0_mode_set_rgb()
552 SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) | in sun4i_tcon0_mode_set_rgb()
556 hsync = mode->crtc_hsync_end - mode->crtc_hsync_start; in sun4i_tcon0_mode_set_rgb()
557 vsync = mode->crtc_vsync_end - mode->crtc_vsync_start; in sun4i_tcon0_mode_set_rgb()
559 regmap_write(tcon->regs, SUN4I_TCON0_BASIC3_REG, in sun4i_tcon0_mode_set_rgb()
564 if (mode->flags & DRM_MODE_FLAG_PHSYNC) in sun4i_tcon0_mode_set_rgb()
567 if (mode->flags & DRM_MODE_FLAG_PVSYNC) in sun4i_tcon0_mode_set_rgb()
570 if (info->bus_flags & DRM_BUS_FLAG_DE_LOW) in sun4i_tcon0_mode_set_rgb()
573 if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) in sun4i_tcon0_mode_set_rgb()
576 regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG, in sun4i_tcon0_mode_set_rgb()
584 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, in sun4i_tcon0_mode_set_rgb()
589 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0); in sun4i_tcon0_mode_set_rgb()
592 static void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon, in sun4i_tcon1_mode_set() argument
599 WARN_ON(!tcon->quirks->has_channel_1); in sun4i_tcon1_mode_set()
602 clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000); in sun4i_tcon1_mode_set()
606 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, in sun4i_tcon1_mode_set()
611 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in sun4i_tcon1_mode_set()
615 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, in sun4i_tcon1_mode_set()
620 regmap_write(tcon->regs, SUN4I_TCON1_BASIC0_REG, in sun4i_tcon1_mode_set()
621 SUN4I_TCON1_BASIC0_X(mode->crtc_hdisplay) | in sun4i_tcon1_mode_set()
622 SUN4I_TCON1_BASIC0_Y(mode->crtc_vdisplay)); in sun4i_tcon1_mode_set()
625 regmap_write(tcon->regs, SUN4I_TCON1_BASIC1_REG, in sun4i_tcon1_mode_set()
626 SUN4I_TCON1_BASIC1_X(mode->crtc_hdisplay) | in sun4i_tcon1_mode_set()
627 SUN4I_TCON1_BASIC1_Y(mode->crtc_vdisplay)); in sun4i_tcon1_mode_set()
630 regmap_write(tcon->regs, SUN4I_TCON1_BASIC2_REG, in sun4i_tcon1_mode_set()
631 SUN4I_TCON1_BASIC2_X(mode->crtc_hdisplay) | in sun4i_tcon1_mode_set()
632 SUN4I_TCON1_BASIC2_Y(mode->crtc_vdisplay)); in sun4i_tcon1_mode_set()
635 bp = mode->crtc_htotal - mode->crtc_hsync_start; in sun4i_tcon1_mode_set()
637 mode->htotal, bp); in sun4i_tcon1_mode_set()
638 regmap_write(tcon->regs, SUN4I_TCON1_BASIC3_REG, in sun4i_tcon1_mode_set()
639 SUN4I_TCON1_BASIC3_H_TOTAL(mode->crtc_htotal) | in sun4i_tcon1_mode_set()
642 bp = mode->crtc_vtotal - mode->crtc_vsync_start; in sun4i_tcon1_mode_set()
644 mode->crtc_vtotal, bp); in sun4i_tcon1_mode_set()
659 vtotal = mode->vtotal; in sun4i_tcon1_mode_set()
660 if (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) in sun4i_tcon1_mode_set()
664 regmap_write(tcon->regs, SUN4I_TCON1_BASIC4_REG, in sun4i_tcon1_mode_set()
669 hsync = mode->crtc_hsync_end - mode->crtc_hsync_start; in sun4i_tcon1_mode_set()
670 vsync = mode->crtc_vsync_end - mode->crtc_vsync_start; in sun4i_tcon1_mode_set()
672 regmap_write(tcon->regs, SUN4I_TCON1_BASIC5_REG, in sun4i_tcon1_mode_set()
677 if (tcon->quirks->polarity_in_ch0) { in sun4i_tcon1_mode_set()
680 if (mode->flags & DRM_MODE_FLAG_PHSYNC) in sun4i_tcon1_mode_set()
683 if (mode->flags & DRM_MODE_FLAG_PVSYNC) in sun4i_tcon1_mode_set()
686 regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val); in sun4i_tcon1_mode_set()
691 if (mode->flags & DRM_MODE_FLAG_PHSYNC) in sun4i_tcon1_mode_set()
694 if (mode->flags & DRM_MODE_FLAG_PVSYNC) in sun4i_tcon1_mode_set()
697 regmap_write(tcon->regs, SUN4I_TCON1_IO_POL_REG, val); in sun4i_tcon1_mode_set()
701 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, in sun4i_tcon1_mode_set()
706 void sun4i_tcon_mode_set(struct sun4i_tcon *tcon, in sun4i_tcon_mode_set() argument
710 switch (encoder->encoder_type) { in sun4i_tcon_mode_set()
713 sun4i_tcon0_mode_set_cpu(tcon, encoder, mode); in sun4i_tcon_mode_set()
716 sun4i_tcon0_mode_set_lvds(tcon, encoder, mode); in sun4i_tcon_mode_set()
719 sun4i_tcon0_mode_set_rgb(tcon, encoder, mode); in sun4i_tcon_mode_set()
720 sun4i_tcon_set_mux(tcon, 0, encoder); in sun4i_tcon_mode_set()
724 sun4i_tcon1_mode_set(tcon, mode); in sun4i_tcon_mode_set()
725 sun4i_tcon_set_mux(tcon, 1, encoder); in sun4i_tcon_mode_set()
738 spin_lock_irqsave(&dev->event_lock, flags); in sun4i_tcon_finish_page_flip()
739 if (scrtc->event) { in sun4i_tcon_finish_page_flip()
740 drm_crtc_send_vblank_event(&scrtc->crtc, scrtc->event); in sun4i_tcon_finish_page_flip()
741 drm_crtc_vblank_put(&scrtc->crtc); in sun4i_tcon_finish_page_flip()
742 scrtc->event = NULL; in sun4i_tcon_finish_page_flip()
744 spin_unlock_irqrestore(&dev->event_lock, flags); in sun4i_tcon_finish_page_flip()
749 struct sun4i_tcon *tcon = private; in sun4i_tcon_handler() local
750 struct drm_device *drm = tcon->drm; in sun4i_tcon_handler()
751 struct sun4i_crtc *scrtc = tcon->crtc; in sun4i_tcon_handler()
752 struct sunxi_engine *engine = scrtc->engine; in sun4i_tcon_handler()
755 regmap_read(tcon->regs, SUN4I_TCON_GINT0_REG, &status); in sun4i_tcon_handler()
762 drm_crtc_handle_vblank(&scrtc->crtc); in sun4i_tcon_handler()
766 regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG, in sun4i_tcon_handler()
772 if (engine->ops->vblank_quirk) in sun4i_tcon_handler()
773 engine->ops->vblank_quirk(engine); in sun4i_tcon_handler()
779 struct sun4i_tcon *tcon) in sun4i_tcon_init_clocks() argument
781 tcon->clk = devm_clk_get(dev, "ahb"); in sun4i_tcon_init_clocks()
782 if (IS_ERR(tcon->clk)) { in sun4i_tcon_init_clocks()
783 dev_err(dev, "Couldn't get the TCON bus clock\n"); in sun4i_tcon_init_clocks()
784 return PTR_ERR(tcon->clk); in sun4i_tcon_init_clocks()
786 clk_prepare_enable(tcon->clk); in sun4i_tcon_init_clocks()
788 if (tcon->quirks->has_channel_0) { in sun4i_tcon_init_clocks()
789 tcon->sclk0 = devm_clk_get(dev, "tcon-ch0"); in sun4i_tcon_init_clocks()
790 if (IS_ERR(tcon->sclk0)) { in sun4i_tcon_init_clocks()
791 dev_err(dev, "Couldn't get the TCON channel 0 clock\n"); in sun4i_tcon_init_clocks()
792 return PTR_ERR(tcon->sclk0); in sun4i_tcon_init_clocks()
795 clk_prepare_enable(tcon->sclk0); in sun4i_tcon_init_clocks()
797 if (tcon->quirks->has_channel_1) { in sun4i_tcon_init_clocks()
798 tcon->sclk1 = devm_clk_get(dev, "tcon-ch1"); in sun4i_tcon_init_clocks()
799 if (IS_ERR(tcon->sclk1)) { in sun4i_tcon_init_clocks()
800 dev_err(dev, "Couldn't get the TCON channel 1 clock\n"); in sun4i_tcon_init_clocks()
801 return PTR_ERR(tcon->sclk1); in sun4i_tcon_init_clocks()
808 static void sun4i_tcon_free_clocks(struct sun4i_tcon *tcon) in sun4i_tcon_free_clocks() argument
810 clk_disable_unprepare(tcon->sclk0); in sun4i_tcon_free_clocks()
811 clk_disable_unprepare(tcon->clk); in sun4i_tcon_free_clocks()
815 struct sun4i_tcon *tcon) in sun4i_tcon_init_irq() argument
825 dev_name(dev), tcon); in sun4i_tcon_init_irq()
842 struct sun4i_tcon *tcon) in sun4i_tcon_init_regmap() argument
851 tcon->regs = devm_regmap_init_mmio(dev, regs, in sun4i_tcon_init_regmap()
853 if (IS_ERR(tcon->regs)) { in sun4i_tcon_init_regmap()
854 dev_err(dev, "Couldn't create the TCON regmap\n"); in sun4i_tcon_init_regmap()
855 return PTR_ERR(tcon->regs); in sun4i_tcon_init_regmap()
858 /* Make sure the TCON is disabled and all IRQs are off */ in sun4i_tcon_init_regmap()
859 regmap_write(tcon->regs, SUN4I_TCON_GCTL_REG, 0); in sun4i_tcon_init_regmap()
860 regmap_write(tcon->regs, SUN4I_TCON_GINT0_REG, 0); in sun4i_tcon_init_regmap()
861 regmap_write(tcon->regs, SUN4I_TCON_GINT1_REG, 0); in sun4i_tcon_init_regmap()
864 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, ~0); in sun4i_tcon_init_regmap()
865 regmap_write(tcon->regs, SUN4I_TCON1_IO_TRI_REG, ~0); in sun4i_tcon_init_regmap()
872 * the TCON is always tied to just one backend. Hence we can traverse
873 * the of_graph upwards to find the backend our tcon is connected to,
878 * registered and binded before the TCON, we can just go through the
891 struct sunxi_engine *engine = ERR_PTR(-EINVAL); in sun4i_tcon_find_engine_traverse()
896 return ERR_PTR(-EINVAL); in sun4i_tcon_find_engine_traverse()
899 * This only works if there is only one path from the TCON in sun4i_tcon_find_engine_traverse()
920 list_for_each_entry(engine, &drv->engine_list, list) in sun4i_tcon_find_engine_traverse()
921 if (remote == engine->node) in sun4i_tcon_find_engine_traverse()
927 * more than one input and one output (TCON TOP) exits, correct in sun4i_tcon_find_engine_traverse()
935 reg -= 1; in sun4i_tcon_find_engine_traverse()
952 * connection between components, up to and including the TCON, of
963 int ret = -EINVAL; in sun4i_tcon_of_get_id_from_port()
985 * Once we know the TCON's id, we can look through the list of
994 list_for_each_entry(engine, &drv->engine_list, list) in sun4i_tcon_get_engine_by_id()
995 if (engine->id == id) in sun4i_tcon_get_engine_by_id()
998 return ERR_PTR(-EINVAL); in sun4i_tcon_get_engine_by_id()
1006 remote = of_graph_get_remote_node(node, 0, -1); in sun4i_tcon_connected_to_tcon_top()
1022 * Because TCON is added to the list at the end of the probe in sun4i_tcon_get_index()
1023 * (after this function is called), index of the current TCON in sun4i_tcon_get_index()
1024 * will be same as current TCON list size. in sun4i_tcon_get_index()
1026 list_for_each(pos, &drv->tcon_list) in sun4i_tcon_get_index()
1034 * we assumed the TCON was always tied to just one backend. However
1035 * this proved not to be the case. On the A31, the TCON can select
1037 * the backend can choose which TCON to output to.
1040 * connection between components, up to and including the TCON, of
1046 * However the connections between the backend and TCON were assumed
1049 * up the remote endpoint ID of a TCON input endpoint. TCON1 would be
1052 * This function first checks if the TCON node has 2 input endpoints.
1057 * have endpoint connections between the backend and TCON across
1073 return ERR_PTR(-EINVAL); in sun4i_tcon_find_engine()
1077 * connections between the backend and TCON? in sun4i_tcon_find_engine()
1086 * contains TCON TOP, chances are that there are either more in sun4i_tcon_find_engine()
1087 * TCONs than engines (R40) or TCONs with non-consecutive ids. in sun4i_tcon_find_engine()
1088 * (H6). In that case it's easier just use TCON index in list in sun4i_tcon_find_engine()
1091 * TCON TOP, remaining 2 TCONs can't be connected to anything in sun4i_tcon_find_engine()
1115 struct sun4i_drv *drv = drm->dev_private; in sun4i_tcon_bind()
1118 struct sun4i_tcon *tcon; in sun4i_tcon_bind() local
1123 engine = sun4i_tcon_find_engine(drv, dev->of_node); in sun4i_tcon_bind()
1126 return -EPROBE_DEFER; in sun4i_tcon_bind()
1129 tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL); in sun4i_tcon_bind()
1130 if (!tcon) in sun4i_tcon_bind()
1131 return -ENOMEM; in sun4i_tcon_bind()
1132 dev_set_drvdata(dev, tcon); in sun4i_tcon_bind()
1133 tcon->drm = drm; in sun4i_tcon_bind()
1134 tcon->dev = dev; in sun4i_tcon_bind()
1135 tcon->id = engine->id; in sun4i_tcon_bind()
1136 tcon->quirks = of_device_get_match_data(dev); in sun4i_tcon_bind()
1138 tcon->lcd_rst = devm_reset_control_get(dev, "lcd"); in sun4i_tcon_bind()
1139 if (IS_ERR(tcon->lcd_rst)) { in sun4i_tcon_bind()
1141 return PTR_ERR(tcon->lcd_rst); in sun4i_tcon_bind()
1144 if (tcon->quirks->needs_edp_reset) { in sun4i_tcon_bind()
1158 /* Make sure our TCON is reset */ in sun4i_tcon_bind()
1159 ret = reset_control_reset(tcon->lcd_rst); in sun4i_tcon_bind()
1165 if (tcon->quirks->supports_lvds) { in sun4i_tcon_bind()
1173 tcon->lvds_rst = devm_reset_control_get_optional(dev, "lvds"); in sun4i_tcon_bind()
1174 if (IS_ERR(tcon->lvds_rst)) { in sun4i_tcon_bind()
1176 return PTR_ERR(tcon->lvds_rst); in sun4i_tcon_bind()
1177 } else if (tcon->lvds_rst) { in sun4i_tcon_bind()
1179 reset_control_reset(tcon->lvds_rst); in sun4i_tcon_bind()
1191 if (tcon->quirks->has_lvds_alt) { in sun4i_tcon_bind()
1192 tcon->lvds_pll = devm_clk_get(dev, "lvds-alt"); in sun4i_tcon_bind()
1193 if (IS_ERR(tcon->lvds_pll)) { in sun4i_tcon_bind()
1194 if (PTR_ERR(tcon->lvds_pll) == -ENOENT) { in sun4i_tcon_bind()
1198 return PTR_ERR(tcon->lvds_pll); in sun4i_tcon_bind()
1206 (tcon->quirks->has_lvds_alt && !has_lvds_alt)) { in sun4i_tcon_bind()
1217 ret = sun4i_tcon_init_clocks(dev, tcon); in sun4i_tcon_bind()
1219 dev_err(dev, "Couldn't init our TCON clocks\n"); in sun4i_tcon_bind()
1223 ret = sun4i_tcon_init_regmap(dev, tcon); in sun4i_tcon_bind()
1225 dev_err(dev, "Couldn't init our TCON regmap\n"); in sun4i_tcon_bind()
1229 if (tcon->quirks->has_channel_0) { in sun4i_tcon_bind()
1230 ret = sun4i_dclk_create(dev, tcon); in sun4i_tcon_bind()
1232 dev_err(dev, "Couldn't create our TCON dot clock\n"); in sun4i_tcon_bind()
1237 ret = sun4i_tcon_init_irq(dev, tcon); in sun4i_tcon_bind()
1239 dev_err(dev, "Couldn't init our TCON interrupts\n"); in sun4i_tcon_bind()
1243 tcon->crtc = sun4i_crtc_init(drm, engine, tcon); in sun4i_tcon_bind()
1244 if (IS_ERR(tcon->crtc)) { in sun4i_tcon_bind()
1246 ret = PTR_ERR(tcon->crtc); in sun4i_tcon_bind()
1250 if (tcon->quirks->has_channel_0) { in sun4i_tcon_bind()
1252 * If we have an LVDS panel connected to the TCON, we should in sun4i_tcon_bind()
1256 remote = of_graph_get_remote_node(dev->of_node, 1, 0); in sun4i_tcon_bind()
1257 if (of_device_is_compatible(remote, "panel-lvds")) in sun4i_tcon_bind()
1259 ret = sun4i_lvds_init(drm, tcon); in sun4i_tcon_bind()
1261 ret = -EINVAL; in sun4i_tcon_bind()
1263 ret = sun4i_rgb_init(drm, tcon); in sun4i_tcon_bind()
1270 if (tcon->quirks->needs_de_be_mux) { in sun4i_tcon_bind()
1276 * the CRTC is tied to the TCON, while the layers are in sun4i_tcon_bind()
1281 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, in sun4i_tcon_bind()
1283 tcon->id); in sun4i_tcon_bind()
1284 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, in sun4i_tcon_bind()
1286 tcon->id); in sun4i_tcon_bind()
1289 list_add_tail(&tcon->list, &drv->tcon_list); in sun4i_tcon_bind()
1294 if (tcon->quirks->has_channel_0) in sun4i_tcon_bind()
1295 sun4i_dclk_free(tcon); in sun4i_tcon_bind()
1297 sun4i_tcon_free_clocks(tcon); in sun4i_tcon_bind()
1299 reset_control_assert(tcon->lcd_rst); in sun4i_tcon_bind()
1306 struct sun4i_tcon *tcon = dev_get_drvdata(dev); in sun4i_tcon_unbind() local
1308 list_del(&tcon->list); in sun4i_tcon_unbind()
1309 if (tcon->quirks->has_channel_0) in sun4i_tcon_unbind()
1310 sun4i_dclk_free(tcon); in sun4i_tcon_unbind()
1311 sun4i_tcon_free_clocks(tcon); in sun4i_tcon_unbind()
1321 struct device_node *node = pdev->dev.of_node; in sun4i_tcon_probe()
1327 quirks = of_device_get_match_data(&pdev->dev); in sun4i_tcon_probe()
1330 if (quirks->has_channel_0) { in sun4i_tcon_probe()
1332 if (ret == -EPROBE_DEFER) in sun4i_tcon_probe()
1336 return component_add(&pdev->dev, &sun4i_tcon_ops); in sun4i_tcon_probe()
1341 component_del(&pdev->dev, &sun4i_tcon_ops); in sun4i_tcon_remove()
1346 /* platform specific TCON muxing callbacks */
1347 static int sun4i_a10_tcon_set_mux(struct sun4i_tcon *tcon, in sun4i_a10_tcon_set_mux() argument
1350 struct sun4i_tcon *tcon0 = sun4i_get_tcon0(encoder->dev); in sun4i_a10_tcon_set_mux()
1354 return -EINVAL; in sun4i_a10_tcon_set_mux()
1356 switch (encoder->encoder_type) { in sun4i_a10_tcon_set_mux()
1362 return -EINVAL; in sun4i_a10_tcon_set_mux()
1365 regmap_update_bits(tcon0->regs, SUN4I_TCON_MUX_CTRL_REG, in sun4i_a10_tcon_set_mux()
1366 0x3 << shift, tcon->id << shift); in sun4i_a10_tcon_set_mux()
1371 static int sun5i_a13_tcon_set_mux(struct sun4i_tcon *tcon, in sun5i_a13_tcon_set_mux() argument
1376 if (encoder->encoder_type == DRM_MODE_ENCODER_TVDAC) in sun5i_a13_tcon_set_mux()
1384 return regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, val); in sun5i_a13_tcon_set_mux()
1387 static int sun6i_tcon_set_mux(struct sun4i_tcon *tcon, in sun6i_tcon_set_mux() argument
1390 struct sun4i_tcon *tcon0 = sun4i_get_tcon0(encoder->dev); in sun6i_tcon_set_mux()
1394 return -EINVAL; in sun6i_tcon_set_mux()
1396 switch (encoder->encoder_type) { in sun6i_tcon_set_mux()
1403 return -EINVAL; in sun6i_tcon_set_mux()
1406 regmap_update_bits(tcon0->regs, SUN4I_TCON_MUX_CTRL_REG, in sun6i_tcon_set_mux()
1407 0x3 << shift, tcon->id << shift); in sun6i_tcon_set_mux()
1412 static int sun8i_r40_tcon_tv_set_mux(struct sun4i_tcon *tcon, in sun8i_r40_tcon_tv_set_mux() argument
1419 /* find TCON TOP platform device and TCON id */ in sun8i_r40_tcon_tv_set_mux()
1421 port = of_graph_get_port_by_id(tcon->dev->of_node, 0); in sun8i_r40_tcon_tv_set_mux()
1423 return -EINVAL; in sun8i_r40_tcon_tv_set_mux()
1428 remote = of_graph_get_remote_node(tcon->dev->of_node, 0, -1); in sun8i_r40_tcon_tv_set_mux()
1430 return -EINVAL; in sun8i_r40_tcon_tv_set_mux()
1435 return -EINVAL; in sun8i_r40_tcon_tv_set_mux()
1438 encoder->encoder_type == DRM_MODE_ENCODER_TMDS) { in sun8i_r40_tcon_tv_set_mux()
1439 ret = sun8i_tcon_top_set_hdmi_src(&pdev->dev, id); in sun8i_r40_tcon_tv_set_mux()
1441 put_device(&pdev->dev); in sun8i_r40_tcon_tv_set_mux()
1447 ret = sun8i_tcon_top_de_config(&pdev->dev, tcon->id, id); in sun8i_r40_tcon_tv_set_mux()
1449 put_device(&pdev->dev); in sun8i_r40_tcon_tv_set_mux()
1552 /* sun4i_drv uses this list to check if a device node is a TCON */
1554 { .compatible = "allwinner,sun4i-a10-tcon", .data = &sun4i_a10_quirks },
1555 { .compatible = "allwinner,sun5i-a13-tcon", .data = &sun5i_a13_quirks },
1556 { .compatible = "allwinner,sun6i-a31-tcon", .data = &sun6i_a31_quirks },
1557 { .compatible = "allwinner,sun6i-a31s-tcon", .data = &sun6i_a31s_quirks },
1558 { .compatible = "allwinner,sun7i-a20-tcon", .data = &sun7i_a20_quirks },
1559 { .compatible = "allwinner,sun7i-a20-tcon0", .data = &sun7i_a20_tcon0_quirks },
1560 { .compatible = "allwinner,sun7i-a20-tcon1", .data = &sun7i_a20_quirks },
1561 { .compatible = "allwinner,sun8i-a23-tcon", .data = &sun8i_a33_quirks },
1562 { .compatible = "allwinner,sun8i-a33-tcon", .data = &sun8i_a33_quirks },
1563 { .compatible = "allwinner,sun8i-a83t-tcon-lcd", .data = &sun8i_a83t_lcd_quirks },
1564 { .compatible = "allwinner,sun8i-a83t-tcon-tv", .data = &sun8i_a83t_tv_quirks },
1565 { .compatible = "allwinner,sun8i-r40-tcon-tv", .data = &sun8i_r40_tv_quirks },
1566 { .compatible = "allwinner,sun8i-v3s-tcon", .data = &sun8i_v3s_quirks },
1567 { .compatible = "allwinner,sun9i-a80-tcon-lcd", .data = &sun9i_a80_tcon_lcd_quirks },
1568 { .compatible = "allwinner,sun9i-a80-tcon-tv", .data = &sun9i_a80_tcon_tv_quirks },
1569 { .compatible = "allwinner,sun20i-d1-tcon-lcd", .data = &sun20i_d1_lcd_quirks },
1570 { .compatible = "allwinner,sun20i-d1-tcon-tv", .data = &sun8i_r40_tv_quirks },
1580 .name = "sun4i-tcon",
1586 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");