Lines Matching +full:0 +full:x504
11 #define HDMI_SRZ_CFG 0x504
12 #define HDMI_SRZ_PLL_CFG 0x510
13 #define HDMI_SRZ_ICNTL 0x518
14 #define HDMI_SRZ_CALCODE_EXT 0x520
16 #define HDMI_SRZ_CFG_EN BIT(0)
32 #define PLL_CFG_EN BIT(0)
37 #define ODF_DIV_1 (0)
56 {0, 20000000, 1, ODF_DIV_8},
65 {0, 250000000, {0x0, 0x0, 0x0, 0x0} },
66 {250000000, 300000000, {0x1110, 0x0, 0x0, 0x0} },
79 u32 val, tmdsck, idf, odf, pllctrl = 0; in sti_hdmi_tx3g4c28phy_start()
85 for (i = 0; i < NB_PLL_MODE; i++) { in sti_hdmi_tx3g4c28phy_start()
117 DRM_DEBUG_DRIVER("pllctrl = 0x%x\n", pllctrl); in sti_hdmi_tx3g4c28phy_start()
126 if ((hdmi_read(hdmi, HDMI_STA) & HDMI_STA_DLL_LCK) == 0) { in sti_hdmi_tx3g4c28phy_start()
146 for (i = 0; i < NB_HDMI_PHY_CONFIG; i++) { in sti_hdmi_tx3g4c28phy_start()
149 val |= (hdmiphy_config[i].config[0] in sti_hdmi_tx3g4c28phy_start()
159 DRM_DEBUG_DRIVER("serializer cfg 0x%x 0x%x 0x%x\n", in sti_hdmi_tx3g4c28phy_start()
160 hdmiphy_config[i].config[0], in sti_hdmi_tx3g4c28phy_start()
172 hdmi_write(hdmi, 0x0, HDMI_SRZ_ICNTL); in sti_hdmi_tx3g4c28phy_start()
173 hdmi_write(hdmi, 0x0, HDMI_SRZ_CALCODE_EXT); in sti_hdmi_tx3g4c28phy_start()
188 int val = 0; in sti_hdmi_tx3g4c28phy_stop()
198 hdmi_write(hdmi, 0, HDMI_SRZ_PLL_CFG); in sti_hdmi_tx3g4c28phy_stop()