Lines Matching +full:0 +full:x610
15 #define VOP_FEATURE_OUTPUT_10BIT BIT(0)
17 #define WIN_FEATURE_AFBDC BIT(0)
180 #define ROCKCHIP_OUT_MODE_P888 0
181 #define ROCKCHIP_OUT_MODE_BT1120 0
216 #define RK3568_GRF_VO_CON1 0x0364
218 #define RK3568_REG_CFG_DONE 0x000
219 #define RK3568_VERSION_INFO 0x004
220 #define RK3568_SYS_AUTO_GATING_CTRL 0x008
221 #define RK3568_SYS_AXI_LUT_CTRL 0x024
222 #define RK3568_DSP_IF_EN 0x028
223 #define RK3568_DSP_IF_CTRL 0x02c
224 #define RK3568_DSP_IF_POL 0x030
225 #define RK3568_WB_CTRL 0x40
226 #define RK3568_WB_XSCAL_FACTOR 0x44
227 #define RK3568_WB_YRGB_MST 0x48
228 #define RK3568_WB_CBR_MST 0x4C
229 #define RK3568_OTP_WIN_EN 0x050
230 #define RK3568_LUT_PORT_SEL 0x058
231 #define RK3568_SYS_STATUS0 0x060
232 #define RK3568_VP_LINE_FLAG(vp) (0x70 + (vp) * 0x4)
233 #define RK3568_SYS0_INT_EN 0x80
234 #define RK3568_SYS0_INT_CLR 0x84
235 #define RK3568_SYS0_INT_STATUS 0x88
236 #define RK3568_SYS1_INT_EN 0x90
237 #define RK3568_SYS1_INT_CLR 0x94
238 #define RK3568_SYS1_INT_STATUS 0x98
239 #define RK3568_VP_INT_EN(vp) (0xA0 + (vp) * 0x10)
240 #define RK3568_VP_INT_CLR(vp) (0xA4 + (vp) * 0x10)
241 #define RK3568_VP_INT_STATUS(vp) (0xA8 + (vp) * 0x10)
242 #define RK3568_VP_INT_RAW_STATUS(vp) (0xAC + (vp) * 0x10)
245 #define RK3568_VP_DSP_CTRL 0x00
246 #define RK3568_VP_MIPI_CTRL 0x04
247 #define RK3568_VP_COLOR_BAR_CTRL 0x08
248 #define RK3568_VP_3D_LUT_CTRL 0x10
249 #define RK3568_VP_3D_LUT_MST 0x20
250 #define RK3568_VP_DSP_BG 0x2C
251 #define RK3568_VP_PRE_SCAN_HTIMING 0x30
252 #define RK3568_VP_POST_DSP_HACT_INFO 0x34
253 #define RK3568_VP_POST_DSP_VACT_INFO 0x38
254 #define RK3568_VP_POST_SCL_FACTOR_YRGB 0x3C
255 #define RK3568_VP_POST_SCL_CTRL 0x40
256 #define RK3568_VP_POST_DSP_VACT_INFO_F1 0x44
257 #define RK3568_VP_DSP_HTOTAL_HS_END 0x48
258 #define RK3568_VP_DSP_HACT_ST_END 0x4C
259 #define RK3568_VP_DSP_VTOTAL_VS_END 0x50
260 #define RK3568_VP_DSP_VACT_ST_END 0x54
261 #define RK3568_VP_DSP_VS_ST_END_F1 0x58
262 #define RK3568_VP_DSP_VACT_ST_END_F1 0x5C
263 #define RK3568_VP_BCSH_CTRL 0x60
264 #define RK3568_VP_BCSH_BCS 0x64
265 #define RK3568_VP_BCSH_H 0x68
266 #define RK3568_VP_BCSH_COLOR_BAR 0x6C
269 #define RK3568_OVL_CTRL 0x600
270 #define RK3568_OVL_LAYER_SEL 0x604
271 #define RK3568_OVL_PORT_SEL 0x608
272 #define RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL 0x610
273 #define RK3568_CLUSTER0_MIX_DST_COLOR_CTRL 0x614
274 #define RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x618
275 #define RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL 0x61C
276 #define RK3568_MIX0_SRC_COLOR_CTRL 0x650
277 #define RK3568_MIX0_DST_COLOR_CTRL 0x654
278 #define RK3568_MIX0_SRC_ALPHA_CTRL 0x658
279 #define RK3568_MIX0_DST_ALPHA_CTRL 0x65C
280 #define RK3568_HDR0_SRC_COLOR_CTRL 0x6C0
281 #define RK3568_HDR0_DST_COLOR_CTRL 0x6C4
282 #define RK3568_HDR0_SRC_ALPHA_CTRL 0x6C8
283 #define RK3568_HDR0_DST_ALPHA_CTRL 0x6CC
284 #define RK3568_VP_BG_MIX_CTRL(vp) (0x6E0 + (vp) * 4)
285 #define RK3568_CLUSTER_DLY_NUM 0x6F0
286 #define RK3568_SMART_DLY_NUM 0x6F8
289 #define RK3568_CLUSTER_WIN_CTRL0 0x00
290 #define RK3568_CLUSTER_WIN_CTRL1 0x04
291 #define RK3568_CLUSTER_WIN_YRGB_MST 0x10
292 #define RK3568_CLUSTER_WIN_CBR_MST 0x14
293 #define RK3568_CLUSTER_WIN_VIR 0x18
294 #define RK3568_CLUSTER_WIN_ACT_INFO 0x20
295 #define RK3568_CLUSTER_WIN_DSP_INFO 0x24
296 #define RK3568_CLUSTER_WIN_DSP_ST 0x28
297 #define RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB 0x30
298 #define RK3568_CLUSTER_WIN_AFBCD_TRANSFORM_OFFSET 0x3C
299 #define RK3568_CLUSTER_WIN_AFBCD_OUTPUT_CTRL 0x50
300 #define RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE 0x54
301 #define RK3568_CLUSTER_WIN_AFBCD_HDR_PTR 0x58
302 #define RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH 0x5C
303 #define RK3568_CLUSTER_WIN_AFBCD_PIC_SIZE 0x60
304 #define RK3568_CLUSTER_WIN_AFBCD_PIC_OFFSET 0x64
305 #define RK3568_CLUSTER_WIN_AFBCD_DSP_OFFSET 0x68
306 #define RK3568_CLUSTER_WIN_AFBCD_CTRL 0x6C
308 #define RK3568_CLUSTER_CTRL 0x100
311 #define RK3568_SMART_CTRL0 0x00
312 #define RK3568_SMART_CTRL1 0x04
313 #define RK3568_SMART_REGION0_CTRL 0x10
314 #define RK3568_SMART_REGION0_YRGB_MST 0x14
315 #define RK3568_SMART_REGION0_CBR_MST 0x18
316 #define RK3568_SMART_REGION0_VIR 0x1C
317 #define RK3568_SMART_REGION0_ACT_INFO 0x20
318 #define RK3568_SMART_REGION0_DSP_INFO 0x24
319 #define RK3568_SMART_REGION0_DSP_ST 0x28
320 #define RK3568_SMART_REGION0_SCL_CTRL 0x30
321 #define RK3568_SMART_REGION0_SCL_FACTOR_YRGB 0x34
322 #define RK3568_SMART_REGION0_SCL_FACTOR_CBR 0x38
323 #define RK3568_SMART_REGION0_SCL_OFFSET 0x3C
324 #define RK3568_SMART_REGION1_CTRL 0x40
325 #define RK3568_SMART_REGION1_YRGB_MST 0x44
326 #define RK3568_SMART_REGION1_CBR_MST 0x48
327 #define RK3568_SMART_REGION1_VIR 0x4C
328 #define RK3568_SMART_REGION1_ACT_INFO 0x50
329 #define RK3568_SMART_REGION1_DSP_INFO 0x54
330 #define RK3568_SMART_REGION1_DSP_ST 0x58
331 #define RK3568_SMART_REGION1_SCL_CTRL 0x60
332 #define RK3568_SMART_REGION1_SCL_FACTOR_YRGB 0x64
333 #define RK3568_SMART_REGION1_SCL_FACTOR_CBR 0x68
334 #define RK3568_SMART_REGION1_SCL_OFFSET 0x6C
335 #define RK3568_SMART_REGION2_CTRL 0x70
336 #define RK3568_SMART_REGION2_YRGB_MST 0x74
337 #define RK3568_SMART_REGION2_CBR_MST 0x78
338 #define RK3568_SMART_REGION2_VIR 0x7C
339 #define RK3568_SMART_REGION2_ACT_INFO 0x80
340 #define RK3568_SMART_REGION2_DSP_INFO 0x84
341 #define RK3568_SMART_REGION2_DSP_ST 0x88
342 #define RK3568_SMART_REGION2_SCL_CTRL 0x90
343 #define RK3568_SMART_REGION2_SCL_FACTOR_YRGB 0x94
344 #define RK3568_SMART_REGION2_SCL_FACTOR_CBR 0x98
345 #define RK3568_SMART_REGION2_SCL_OFFSET 0x9C
346 #define RK3568_SMART_REGION3_CTRL 0xA0
347 #define RK3568_SMART_REGION3_YRGB_MST 0xA4
348 #define RK3568_SMART_REGION3_CBR_MST 0xA8
349 #define RK3568_SMART_REGION3_VIR 0xAC
350 #define RK3568_SMART_REGION3_ACT_INFO 0xB0
351 #define RK3568_SMART_REGION3_DSP_INFO 0xB4
352 #define RK3568_SMART_REGION3_DSP_ST 0xB8
353 #define RK3568_SMART_REGION3_SCL_CTRL 0xC0
354 #define RK3568_SMART_REGION3_SCL_FACTOR_YRGB 0xC4
355 #define RK3568_SMART_REGION3_SCL_FACTOR_CBR 0xC8
356 #define RK3568_SMART_REGION3_SCL_OFFSET 0xCC
357 #define RK3568_SMART_COLOR_KEY_CTRL 0xD0
360 #define RK3568_HDR_LUT_CTRL 0x2000
361 #define RK3568_HDR_LUT_MST 0x2004
362 #define RK3568_SDR2HDR_CTRL 0x2010
363 #define RK3568_HDR2SDR_CTRL 0x2020
364 #define RK3568_HDR2SDR_SRC_RANGE 0x2024
365 #define RK3568_HDR2SDR_NORMFACEETF 0x2028
366 #define RK3568_HDR2SDR_DST_RANGE 0x202C
367 #define RK3568_HDR2SDR_NORMFACCGAMMA 0x2030
368 #define RK3568_HDR_EETF_OETF_Y0 0x203C
369 #define RK3568_HDR_SAT_Y0 0x20C0
370 #define RK3568_HDR_EOTF_OETF_Y0 0x20F0
371 #define RK3568_HDR_OETF_DX_POW1 0x2200
372 #define RK3568_HDR_OETF_XN1 0x2300
387 #define RK3568_VP_DSP_CTRL__OUT_MODE GENMASK(3, 0)
390 #define RK3568_VP_POST_SCL_CTRL__HSCALEDOWN BIT(0)
405 #define RK3568_SYS_DSP_INFACE_EN_RGB BIT(0)
410 #define RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL GENMASK(3, 0)
421 #define VOP2_CLUSTER_YUV444_10 0x12
438 #define RK3568_OVL_PORT_SET__PORT0_MUX GENMASK(3, 0)
444 #define RK3568_CLUSTER_DLY_NUM__CLUSTER0_0 GENMASK(7, 0)
449 #define RK3568_SMART_DLY_NUM__ESMART0 GENMASK(7, 0)
457 #define VP_INT_FS BIT(0)
462 ROCKCHIP_VOP2_CLUSTER0 = 0,