Lines Matching +full:0 +full:xff000000

45 		tmp |= 0xe70000;  in vce_v2_0_set_sw_cg()
49 tmp |= 0xff000000; in vce_v2_0_set_sw_cg()
53 tmp &= ~0x3fc; in vce_v2_0_set_sw_cg()
56 WREG32(VCE_CGTT_CLK_OVERRIDE, 0); in vce_v2_0_set_sw_cg()
59 tmp |= 0xe7; in vce_v2_0_set_sw_cg()
60 tmp &= ~0xe70000; in vce_v2_0_set_sw_cg()
64 tmp |= 0x1fe000; in vce_v2_0_set_sw_cg()
65 tmp &= ~0xff000000; in vce_v2_0_set_sw_cg()
69 tmp |= 0x3fc; in vce_v2_0_set_sw_cg()
79 tmp &= ~0x00060006; in vce_v2_0_set_dyn_cg()
81 tmp |= 0xe10000; in vce_v2_0_set_dyn_cg()
83 tmp |= 0xe1; in vce_v2_0_set_dyn_cg()
84 tmp &= ~0xe10000; in vce_v2_0_set_dyn_cg()
89 tmp &= ~0x1fe000; in vce_v2_0_set_dyn_cg()
90 tmp &= ~0xff000000; in vce_v2_0_set_dyn_cg()
95 tmp &= ~0x3fc; in vce_v2_0_set_dyn_cg()
100 WREG32(VCE_CGTT_CLK_OVERRIDE, 0); in vce_v2_0_set_dyn_cg()
137 tmp |= (CGC_CLK_GATE_DLY_TIMER(0) | CGC_CLK_GATER_OFF_DLY_TIMER(4)); in vce_v2_0_init_cg()
143 tmp |= (CLOCK_ON_DELAY(0) | CLOCK_OFF_DELAY(4)); in vce_v2_0_init_cg()
147 tmp |= 0x10; in vce_v2_0_init_cg()
148 tmp &= ~0x100000; in vce_v2_0_init_cg()
163 WREG32_P(VCE_CLOCK_GATING_A, 0, ~(1 << 16)); in vce_v2_0_resume()
164 WREG32_P(VCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); in vce_v2_0_resume()
165 WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); in vce_v2_0_resume()
166 WREG32(VCE_CLOCK_GATING_B, 0xf7); in vce_v2_0_resume()
168 WREG32(VCE_LMI_CTRL, 0x00398000); in vce_v2_0_resume()
169 WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1); in vce_v2_0_resume()
170 WREG32(VCE_LMI_SWAP_CNTL, 0); in vce_v2_0_resume()
171 WREG32(VCE_LMI_SWAP_CNTL1, 0); in vce_v2_0_resume()
172 WREG32(VCE_LMI_VM_CTRL, 0); in vce_v2_0_resume()
176 addr &= 0xff; in vce_v2_0_resume()
178 WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff); in vce_v2_0_resume()
183 WREG32(VCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff); in vce_v2_0_resume()
188 WREG32(VCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff); in vce_v2_0_resume()
191 WREG32_P(VCE_LMI_CTRL2, 0x0, ~0x100); in vce_v2_0_resume()
198 return 0; in vce_v2_0_resume()