347 	u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk;  in sumo_program_bsp()
411 		m_a = asi * ps->levels[i].sclk / 100;  in sumo_program_at()
670 		pi->boost_pl = new_ps->levels[new_ps->num_levels - 1];  in sumo_patch_boost_state()
762 		sumo_program_power_level(rdev, &new_ps->levels[i], i);  in sumo_program_power_levels_0_to_n()
844 	if (new_ps->levels[new_ps->num_levels - 1].sclk >=  in sumo_set_uvd_clock_before_set_eng_clock()
845 	    current_ps->levels[current_ps->num_levels - 1].sclk)  in sumo_set_uvd_clock_before_set_eng_clock()
862 	if (new_ps->levels[new_ps->num_levels - 1].sclk <  in sumo_set_uvd_clock_after_set_eng_clock()
863 	    current_ps->levels[current_ps->num_levels - 1].sclk)  in sumo_set_uvd_clock_after_set_eng_clock()
1053 		current_vddc = current_ps->levels[current_index].vddc_index;  in sumo_patch_thermal_state()
1054 		current_sclk = current_ps->levels[current_index].sclk;  in sumo_patch_thermal_state()
1060 	ps->levels[0].vddc_index = current_vddc;  in sumo_patch_thermal_state()
1062 	if (ps->levels[0].sclk > current_sclk)  in sumo_patch_thermal_state()
1063 		ps->levels[0].sclk = current_sclk;  in sumo_patch_thermal_state()
1065 	ps->levels[0].ss_divider_index =  in sumo_patch_thermal_state()
1066 		sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, sclk_in_sr);  in sumo_patch_thermal_state()
1068 	ps->levels[0].ds_divider_index =  in sumo_patch_thermal_state()
1069 		sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, SUMO_MINIMUM_ENGINE_CLOCK);  in sumo_patch_thermal_state()
1071 	if (ps->levels[0].ds_divider_index > ps->levels[0].ss_divider_index + 1)  in sumo_patch_thermal_state()
1072 		ps->levels[0].ds_divider_index = ps->levels[0].ss_divider_index + 1;  in sumo_patch_thermal_state()
1074 	if (ps->levels[0].ss_divider_index == ps->levels[0].ds_divider_index) {  in sumo_patch_thermal_state()
1075 		if (ps->levels[0].ss_divider_index > 1)  in sumo_patch_thermal_state()
1076 			ps->levels[0].ss_divider_index = ps->levels[0].ss_divider_index - 1;  in sumo_patch_thermal_state()
1079 	if (ps->levels[0].ss_divider_index == 0)  in sumo_patch_thermal_state()
1080 		ps->levels[0].ds_divider_index = 0;  in sumo_patch_thermal_state()
1082 	if (ps->levels[0].ds_divider_index == 0)  in sumo_patch_thermal_state()
1083 		ps->levels[0].ss_divider_index = 0;  in sumo_patch_thermal_state()
1112 		if (ps->levels[i].vddc_index < min_voltage)  in sumo_apply_state_adjust_rules()
1113 			ps->levels[i].vddc_index = min_voltage;  in sumo_apply_state_adjust_rules()
1115 		if (ps->levels[i].sclk < min_sclk)  in sumo_apply_state_adjust_rules()
1116 			ps->levels[i].sclk =  in sumo_apply_state_adjust_rules()
1119 		ps->levels[i].ss_divider_index =  in sumo_apply_state_adjust_rules()
1120 			sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, sclk_in_sr);  in sumo_apply_state_adjust_rules()
1122 		ps->levels[i].ds_divider_index =  in sumo_apply_state_adjust_rules()
1123 			sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, SUMO_MINIMUM_ENGINE_CLOCK);  in sumo_apply_state_adjust_rules()
1125 		if (ps->levels[i].ds_divider_index > ps->levels[i].ss_divider_index + 1)  in sumo_apply_state_adjust_rules()
1126 			ps->levels[i].ds_divider_index = ps->levels[i].ss_divider_index + 1;  in sumo_apply_state_adjust_rules()
1128 		if (ps->levels[i].ss_divider_index == ps->levels[i].ds_divider_index) {  in sumo_apply_state_adjust_rules()
1129 			if (ps->levels[i].ss_divider_index > 1)  in sumo_apply_state_adjust_rules()
1130 				ps->levels[i].ss_divider_index = ps->levels[i].ss_divider_index - 1;  in sumo_apply_state_adjust_rules()
1133 		if (ps->levels[i].ss_divider_index == 0)  in sumo_apply_state_adjust_rules()
1134 			ps->levels[i].ds_divider_index = 0;  in sumo_apply_state_adjust_rules()
1136 		if (ps->levels[i].ds_divider_index == 0)  in sumo_apply_state_adjust_rules()
1137 			ps->levels[i].ss_divider_index = 0;  in sumo_apply_state_adjust_rules()
1140 			ps->levels[i].allow_gnb_slow = 1;  in sumo_apply_state_adjust_rules()
1143 			ps->levels[i].allow_gnb_slow = 0;  in sumo_apply_state_adjust_rules()
1145 			ps->levels[i].allow_gnb_slow = 0;  in sumo_apply_state_adjust_rules()
1147 			ps->levels[i].allow_gnb_slow = 1;  in sumo_apply_state_adjust_rules()
1399 	ps->levels[0] = pi->boot_pl;  in sumo_patch_boot_state()
1435 	struct sumo_pl *pl = &ps->levels[index];  in sumo_parse_pplib_clock_info()
1737 	pi->current_ps.levels[0] = pi->boot_pl;  in sumo_construct_boot_and_acpi_state()
1804 		struct sumo_pl *pl = &ps->levels[i];  in sumo_dpm_print_power_state()
1832 		pl = &ps->levels[current_index];  in sumo_dpm_debugfs_print_current_performance_level()
1856 		pl = &ps->levels[current_index];  in sumo_dpm_get_current_sclk()
1883 		pl = &ps->levels[current_index];  in sumo_dpm_get_current_vddc()
1907 		return requested_state->levels[0].sclk;  in sumo_dpm_get_sclk()
1909 		return requested_state->levels[requested_state->num_levels - 1].sclk;  in sumo_dpm_get_sclk()