Lines Matching +full:0 +full:x00000000 +full:- +full:0 +full:x03ffffff
161 #define DC_HPDx_CONTROL(x) (DC_HPD1_CONTROL + (x * 0xc))
162 #define DC_HPDx_INT_CONTROL(x) (DC_HPD1_INT_CONTROL + (x * 0xc))
163 #define DC_HPDx_INT_STATUS_REG(x) (DC_HPD1_INT_STATUS + (x * 0xc))
167 (0x8000 << 16) | (0x98f4 >> 2),
168 0x00000000,
169 (0x8040 << 16) | (0x98f4 >> 2),
170 0x00000000,
171 (0x8000 << 16) | (0xe80 >> 2),
172 0x00000000,
173 (0x8040 << 16) | (0xe80 >> 2),
174 0x00000000,
175 (0x8000 << 16) | (0x89bc >> 2),
176 0x00000000,
177 (0x8040 << 16) | (0x89bc >> 2),
178 0x00000000,
179 (0x8000 << 16) | (0x8c1c >> 2),
180 0x00000000,
181 (0x8040 << 16) | (0x8c1c >> 2),
182 0x00000000,
183 (0x9c00 << 16) | (0x98f0 >> 2),
184 0x00000000,
185 (0x9c00 << 16) | (0xe7c >> 2),
186 0x00000000,
187 (0x8000 << 16) | (0x9148 >> 2),
188 0x00000000,
189 (0x8040 << 16) | (0x9148 >> 2),
190 0x00000000,
191 (0x9c00 << 16) | (0x9150 >> 2),
192 0x00000000,
193 (0x9c00 << 16) | (0x897c >> 2),
194 0x00000000,
195 (0x9c00 << 16) | (0x8d8c >> 2),
196 0x00000000,
197 (0x9c00 << 16) | (0xac54 >> 2),
198 0X00000000,
199 0x3,
200 (0x9c00 << 16) | (0x98f8 >> 2),
201 0x00000000,
202 (0x9c00 << 16) | (0x9910 >> 2),
203 0x00000000,
204 (0x9c00 << 16) | (0x9914 >> 2),
205 0x00000000,
206 (0x9c00 << 16) | (0x9918 >> 2),
207 0x00000000,
208 (0x9c00 << 16) | (0x991c >> 2),
209 0x00000000,
210 (0x9c00 << 16) | (0x9920 >> 2),
211 0x00000000,
212 (0x9c00 << 16) | (0x9924 >> 2),
213 0x00000000,
214 (0x9c00 << 16) | (0x9928 >> 2),
215 0x00000000,
216 (0x9c00 << 16) | (0x992c >> 2),
217 0x00000000,
218 (0x9c00 << 16) | (0x9930 >> 2),
219 0x00000000,
220 (0x9c00 << 16) | (0x9934 >> 2),
221 0x00000000,
222 (0x9c00 << 16) | (0x9938 >> 2),
223 0x00000000,
224 (0x9c00 << 16) | (0x993c >> 2),
225 0x00000000,
226 (0x9c00 << 16) | (0x9940 >> 2),
227 0x00000000,
228 (0x9c00 << 16) | (0x9944 >> 2),
229 0x00000000,
230 (0x9c00 << 16) | (0x9948 >> 2),
231 0x00000000,
232 (0x9c00 << 16) | (0x994c >> 2),
233 0x00000000,
234 (0x9c00 << 16) | (0x9950 >> 2),
235 0x00000000,
236 (0x9c00 << 16) | (0x9954 >> 2),
237 0x00000000,
238 (0x9c00 << 16) | (0x9958 >> 2),
239 0x00000000,
240 (0x9c00 << 16) | (0x995c >> 2),
241 0x00000000,
242 (0x9c00 << 16) | (0x9960 >> 2),
243 0x00000000,
244 (0x9c00 << 16) | (0x9964 >> 2),
245 0x00000000,
246 (0x9c00 << 16) | (0x9968 >> 2),
247 0x00000000,
248 (0x9c00 << 16) | (0x996c >> 2),
249 0x00000000,
250 (0x9c00 << 16) | (0x9970 >> 2),
251 0x00000000,
252 (0x9c00 << 16) | (0x9974 >> 2),
253 0x00000000,
254 (0x9c00 << 16) | (0x9978 >> 2),
255 0x00000000,
256 (0x9c00 << 16) | (0x997c >> 2),
257 0x00000000,
258 (0x9c00 << 16) | (0x9980 >> 2),
259 0x00000000,
260 (0x9c00 << 16) | (0x9984 >> 2),
261 0x00000000,
262 (0x9c00 << 16) | (0x9988 >> 2),
263 0x00000000,
264 (0x9c00 << 16) | (0x998c >> 2),
265 0x00000000,
266 (0x9c00 << 16) | (0x8c00 >> 2),
267 0x00000000,
268 (0x9c00 << 16) | (0x8c14 >> 2),
269 0x00000000,
270 (0x9c00 << 16) | (0x8c04 >> 2),
271 0x00000000,
272 (0x9c00 << 16) | (0x8c08 >> 2),
273 0x00000000,
274 (0x8000 << 16) | (0x9b7c >> 2),
275 0x00000000,
276 (0x8040 << 16) | (0x9b7c >> 2),
277 0x00000000,
278 (0x8000 << 16) | (0xe84 >> 2),
279 0x00000000,
280 (0x8040 << 16) | (0xe84 >> 2),
281 0x00000000,
282 (0x8000 << 16) | (0x89c0 >> 2),
283 0x00000000,
284 (0x8040 << 16) | (0x89c0 >> 2),
285 0x00000000,
286 (0x8000 << 16) | (0x914c >> 2),
287 0x00000000,
288 (0x8040 << 16) | (0x914c >> 2),
289 0x00000000,
290 (0x8000 << 16) | (0x8c20 >> 2),
291 0x00000000,
292 (0x8040 << 16) | (0x8c20 >> 2),
293 0x00000000,
294 (0x8000 << 16) | (0x9354 >> 2),
295 0x00000000,
296 (0x8040 << 16) | (0x9354 >> 2),
297 0x00000000,
298 (0x9c00 << 16) | (0x9060 >> 2),
299 0x00000000,
300 (0x9c00 << 16) | (0x9364 >> 2),
301 0x00000000,
302 (0x9c00 << 16) | (0x9100 >> 2),
303 0x00000000,
304 (0x9c00 << 16) | (0x913c >> 2),
305 0x00000000,
306 (0x8000 << 16) | (0x90e0 >> 2),
307 0x00000000,
308 (0x8000 << 16) | (0x90e4 >> 2),
309 0x00000000,
310 (0x8000 << 16) | (0x90e8 >> 2),
311 0x00000000,
312 (0x8040 << 16) | (0x90e0 >> 2),
313 0x00000000,
314 (0x8040 << 16) | (0x90e4 >> 2),
315 0x00000000,
316 (0x8040 << 16) | (0x90e8 >> 2),
317 0x00000000,
318 (0x9c00 << 16) | (0x8bcc >> 2),
319 0x00000000,
320 (0x9c00 << 16) | (0x8b24 >> 2),
321 0x00000000,
322 (0x9c00 << 16) | (0x88c4 >> 2),
323 0x00000000,
324 (0x9c00 << 16) | (0x8e50 >> 2),
325 0x00000000,
326 (0x9c00 << 16) | (0x8c0c >> 2),
327 0x00000000,
328 (0x9c00 << 16) | (0x8e58 >> 2),
329 0x00000000,
330 (0x9c00 << 16) | (0x8e5c >> 2),
331 0x00000000,
332 (0x9c00 << 16) | (0x9508 >> 2),
333 0x00000000,
334 (0x9c00 << 16) | (0x950c >> 2),
335 0x00000000,
336 (0x9c00 << 16) | (0x9494 >> 2),
337 0x00000000,
338 (0x9c00 << 16) | (0xac0c >> 2),
339 0x00000000,
340 (0x9c00 << 16) | (0xac10 >> 2),
341 0x00000000,
342 (0x9c00 << 16) | (0xac14 >> 2),
343 0x00000000,
344 (0x9c00 << 16) | (0xae00 >> 2),
345 0x00000000,
346 (0x9c00 << 16) | (0xac08 >> 2),
347 0x00000000,
348 (0x9c00 << 16) | (0x88d4 >> 2),
349 0x00000000,
350 (0x9c00 << 16) | (0x88c8 >> 2),
351 0x00000000,
352 (0x9c00 << 16) | (0x88cc >> 2),
353 0x00000000,
354 (0x9c00 << 16) | (0x89b0 >> 2),
355 0x00000000,
356 (0x9c00 << 16) | (0x8b10 >> 2),
357 0x00000000,
358 (0x9c00 << 16) | (0x8a14 >> 2),
359 0x00000000,
360 (0x9c00 << 16) | (0x9830 >> 2),
361 0x00000000,
362 (0x9c00 << 16) | (0x9834 >> 2),
363 0x00000000,
364 (0x9c00 << 16) | (0x9838 >> 2),
365 0x00000000,
366 (0x9c00 << 16) | (0x9a10 >> 2),
367 0x00000000,
368 (0x8000 << 16) | (0x9870 >> 2),
369 0x00000000,
370 (0x8000 << 16) | (0x9874 >> 2),
371 0x00000000,
372 (0x8001 << 16) | (0x9870 >> 2),
373 0x00000000,
374 (0x8001 << 16) | (0x9874 >> 2),
375 0x00000000,
376 (0x8040 << 16) | (0x9870 >> 2),
377 0x00000000,
378 (0x8040 << 16) | (0x9874 >> 2),
379 0x00000000,
380 (0x8041 << 16) | (0x9870 >> 2),
381 0x00000000,
382 (0x8041 << 16) | (0x9874 >> 2),
383 0x00000000,
384 0x00000000
389 0xc424, 0xffffffff, 0x00601005,
390 0xc47c, 0xffffffff, 0x10104040,
391 0xc488, 0xffffffff, 0x0100000a,
392 0xc314, 0xffffffff, 0x00000800,
393 0xc30c, 0xffffffff, 0x800000f4,
394 0xf4a8, 0xffffffff, 0x00000000
399 0x9a10, 0x00010000, 0x00018208,
400 0x9830, 0xffffffff, 0x00000000,
401 0x9834, 0xf00fffff, 0x00000400,
402 0x9838, 0x0002021c, 0x00020200,
403 0xc78, 0x00000080, 0x00000000,
404 0xd030, 0x000300c0, 0x00800040,
405 0xd830, 0x000300c0, 0x00800040,
406 0x5bb0, 0x000000f0, 0x00000070,
407 0x5bc0, 0x00200000, 0x50100000,
408 0x7030, 0x31000311, 0x00000011,
409 0x277c, 0x00000003, 0x000007ff,
410 0x240c, 0x000007ff, 0x00000000,
411 0x8a14, 0xf000001f, 0x00000007,
412 0x8b24, 0xffffffff, 0x00ffffff,
413 0x8b10, 0x0000ff0f, 0x00000000,
414 0x28a4c, 0x07ffffff, 0x4e000000,
415 0x28350, 0x3f3f3fff, 0x2a00126a,
416 0x30, 0x000000ff, 0x0040,
417 0x34, 0x00000040, 0x00004040,
418 0x9100, 0x07ffffff, 0x03000000,
419 0x8e88, 0x01ff1f3f, 0x00000000,
420 0x8e84, 0x01ff1f3f, 0x00000000,
421 0x9060, 0x0000007f, 0x00000020,
422 0x9508, 0x00010000, 0x00010000,
423 0xac14, 0x00000200, 0x000002fb,
424 0xac10, 0xffffffff, 0x0000543b,
425 0xac0c, 0xffffffff, 0xa9210876,
426 0x88d0, 0xffffffff, 0x000fff40,
427 0x88d4, 0x0000001f, 0x00000010,
428 0x1410, 0x20000000, 0x20fffed8,
429 0x15c0, 0x000c0fc0, 0x000c0400
434 0xc64, 0x00000001, 0x00000001
439 0xc424, 0xffffffff, 0x00601004,
440 0xc47c, 0xffffffff, 0x10102020,
441 0xc488, 0xffffffff, 0x01000020,
442 0xc314, 0xffffffff, 0x00000800,
443 0xc30c, 0xffffffff, 0x800000a4
448 0x9a10, 0x00010000, 0x00018208,
449 0x9830, 0xffffffff, 0x00000000,
450 0x9834, 0xf00fffff, 0x00000400,
451 0x9838, 0x0002021c, 0x00020200,
452 0xc78, 0x00000080, 0x00000000,
453 0xd030, 0x000300c0, 0x00800040,
454 0xd830, 0x000300c0, 0x00800040,
455 0x5bb0, 0x000000f0, 0x00000070,
456 0x5bc0, 0x00200000, 0x50100000,
457 0x7030, 0x31000311, 0x00000011,
458 0x2ae4, 0x00073ffe, 0x000022a2,
459 0x240c, 0x000007ff, 0x00000000,
460 0x8a14, 0xf000001f, 0x00000007,
461 0x8b24, 0xffffffff, 0x00ffffff,
462 0x8b10, 0x0000ff0f, 0x00000000,
463 0x28a4c, 0x07ffffff, 0x4e000000,
464 0x28350, 0x3f3f3fff, 0x2a00126a,
465 0x30, 0x000000ff, 0x0040,
466 0x34, 0x00000040, 0x00004040,
467 0x9100, 0x07ffffff, 0x03000000,
468 0x9060, 0x0000007f, 0x00000020,
469 0x9508, 0x00010000, 0x00010000,
470 0xac14, 0x000003ff, 0x000000f7,
471 0xac10, 0xffffffff, 0x00000000,
472 0xac0c, 0xffffffff, 0x32761054,
473 0x88d4, 0x0000001f, 0x00000010,
474 0x15c0, 0x000c0fc0, 0x000c0400
479 0xc424, 0xffffffff, 0x033f1005,
480 0xc47c, 0xffffffff, 0x10808020,
481 0xc488, 0xffffffff, 0x00800008,
482 0xc314, 0xffffffff, 0x00001000,
483 0xc30c, 0xffffffff, 0x80010014
488 0x9a10, 0x00010000, 0x00018208,
489 0x9830, 0xffffffff, 0x00000000,
490 0x9834, 0xf00fffff, 0x00000400,
491 0x9838, 0x0002021c, 0x00020200,
492 0xc78, 0x00000080, 0x00000000,
493 0xd030, 0x000300c0, 0x00800040,
494 0xd030, 0x000300c0, 0x00800040,
495 0xd830, 0x000300c0, 0x00800040,
496 0xd830, 0x000300c0, 0x00800040,
497 0x5bb0, 0x000000f0, 0x00000070,
498 0x5bc0, 0x00200000, 0x50100000,
499 0x7030, 0x31000311, 0x00000011,
500 0x2ae4, 0x00073ffe, 0x000022a2,
501 0x2ae4, 0x00073ffe, 0x000022a2,
502 0x2ae4, 0x00073ffe, 0x000022a2,
503 0x240c, 0x000007ff, 0x00000000,
504 0x240c, 0x000007ff, 0x00000000,
505 0x240c, 0x000007ff, 0x00000000,
506 0x8a14, 0xf000001f, 0x00000007,
507 0x8a14, 0xf000001f, 0x00000007,
508 0x8a14, 0xf000001f, 0x00000007,
509 0x8b24, 0xffffffff, 0x00ffffff,
510 0x8b10, 0x0000ff0f, 0x00000000,
511 0x28a4c, 0x07ffffff, 0x4e000000,
512 0x28350, 0x3f3f3fff, 0x0000124a,
513 0x28350, 0x3f3f3fff, 0x0000124a,
514 0x28350, 0x3f3f3fff, 0x0000124a,
515 0x30, 0x000000ff, 0x0040,
516 0x34, 0x00000040, 0x00004040,
517 0x9100, 0x07ffffff, 0x03000000,
518 0x9100, 0x07ffffff, 0x03000000,
519 0x8e88, 0x01ff1f3f, 0x00000000,
520 0x8e88, 0x01ff1f3f, 0x00000000,
521 0x8e88, 0x01ff1f3f, 0x00000000,
522 0x8e84, 0x01ff1f3f, 0x00000000,
523 0x8e84, 0x01ff1f3f, 0x00000000,
524 0x8e84, 0x01ff1f3f, 0x00000000,
525 0x9060, 0x0000007f, 0x00000020,
526 0x9508, 0x00010000, 0x00010000,
527 0xac14, 0x000003ff, 0x00000003,
528 0xac14, 0x000003ff, 0x00000003,
529 0xac14, 0x000003ff, 0x00000003,
530 0xac10, 0xffffffff, 0x00000000,
531 0xac10, 0xffffffff, 0x00000000,
532 0xac10, 0xffffffff, 0x00000000,
533 0xac0c, 0xffffffff, 0x00001032,
534 0xac0c, 0xffffffff, 0x00001032,
535 0xac0c, 0xffffffff, 0x00001032,
536 0x88d4, 0x0000001f, 0x00000010,
537 0x88d4, 0x0000001f, 0x00000010,
538 0x88d4, 0x0000001f, 0x00000010,
539 0x15c0, 0x000c0fc0, 0x000c0400
544 0xc424, 0xffffffff, 0x00601005,
545 0xc47c, 0xffffffff, 0x10104040,
546 0xc488, 0xffffffff, 0x0100000a,
547 0xc314, 0xffffffff, 0x00000800,
548 0xc30c, 0xffffffff, 0x800000f4
553 0x9a10, 0x00010000, 0x00018208,
554 0x9830, 0xffffffff, 0x00000000,
555 0x9834, 0xf00fffff, 0x00000400,
556 0x9838, 0x0002021c, 0x00020200,
557 0xc78, 0x00000080, 0x00000000,
558 0xd030, 0x000300c0, 0x00800040,
559 0xd830, 0x000300c0, 0x00800040,
560 0x5bb0, 0x000000f0, 0x00000070,
561 0x5bc0, 0x00200000, 0x50100000,
562 0x7030, 0x31000311, 0x00000011,
563 0x2ae4, 0x00073ffe, 0x000022a2,
564 0x240c, 0x000007ff, 0x00000000,
565 0x8a14, 0xf000001f, 0x00000007,
566 0x8b24, 0xffffffff, 0x00ffffff,
567 0x8b10, 0x0000ff0f, 0x00000000,
568 0x28a4c, 0x07ffffff, 0x4e000000,
569 0x28350, 0x3f3f3fff, 0x00000082,
570 0x30, 0x000000ff, 0x0040,
571 0x34, 0x00000040, 0x00004040,
572 0x9100, 0x07ffffff, 0x03000000,
573 0x9060, 0x0000007f, 0x00000020,
574 0x9508, 0x00010000, 0x00010000,
575 0xac14, 0x000003ff, 0x000000f3,
576 0xac10, 0xffffffff, 0x00000000,
577 0xac0c, 0xffffffff, 0x00003210,
578 0x88d4, 0x0000001f, 0x00000010,
579 0x15c0, 0x000c0fc0, 0x000c0400
584 0x9a10, 0x00010000, 0x00018208,
585 0x9830, 0xffffffff, 0x00000000,
586 0x9834, 0xf00fffff, 0x00000400,
587 0x9838, 0x0002021c, 0x00020200,
588 0xd0c0, 0xff000fff, 0x00000100,
589 0xd030, 0x000300c0, 0x00800040,
590 0xd8c0, 0xff000fff, 0x00000100,
591 0xd830, 0x000300c0, 0x00800040,
592 0x2ae4, 0x00073ffe, 0x000022a2,
593 0x240c, 0x000007ff, 0x00000000,
594 0x8a14, 0xf000001f, 0x00000007,
595 0x8b24, 0xffffffff, 0x00ffffff,
596 0x8b10, 0x0000ff0f, 0x00000000,
597 0x28a4c, 0x07ffffff, 0x4e000000,
598 0x28350, 0x3f3f3fff, 0x00000000,
599 0x30, 0x000000ff, 0x0040,
600 0x34, 0x00000040, 0x00004040,
601 0x9100, 0x03e00000, 0x03600000,
602 0x9060, 0x0000007f, 0x00000020,
603 0x9508, 0x00010000, 0x00010000,
604 0xac14, 0x000003ff, 0x000000f1,
605 0xac10, 0xffffffff, 0x00000000,
606 0xac0c, 0xffffffff, 0x00003210,
607 0x88d4, 0x0000001f, 0x00000010,
608 0x15c0, 0x000c0fc0, 0x000c0400
613 0x98f8, 0xffffffff, 0x02010001
618 0xc400, 0xffffffff, 0xfffffffc,
619 0x802c, 0xffffffff, 0xe0000000,
620 0x9a60, 0xffffffff, 0x00000100,
621 0x92a4, 0xffffffff, 0x00000100,
622 0xc164, 0xffffffff, 0x00000100,
623 0x9774, 0xffffffff, 0x00000100,
624 0x8984, 0xffffffff, 0x06000100,
625 0x8a18, 0xffffffff, 0x00000100,
626 0x92a0, 0xffffffff, 0x00000100,
627 0xc380, 0xffffffff, 0x00000100,
628 0x8b28, 0xffffffff, 0x00000100,
629 0x9144, 0xffffffff, 0x00000100,
630 0x8d88, 0xffffffff, 0x00000100,
631 0x8d8c, 0xffffffff, 0x00000100,
632 0x9030, 0xffffffff, 0x00000100,
633 0x9034, 0xffffffff, 0x00000100,
634 0x9038, 0xffffffff, 0x00000100,
635 0x903c, 0xffffffff, 0x00000100,
636 0xad80, 0xffffffff, 0x00000100,
637 0xac54, 0xffffffff, 0x00000100,
638 0x897c, 0xffffffff, 0x06000100,
639 0x9868, 0xffffffff, 0x00000100,
640 0x9510, 0xffffffff, 0x00000100,
641 0xaf04, 0xffffffff, 0x00000100,
642 0xae04, 0xffffffff, 0x00000100,
643 0x949c, 0xffffffff, 0x00000100,
644 0x802c, 0xffffffff, 0xe0000000,
645 0x9160, 0xffffffff, 0x00010000,
646 0x9164, 0xffffffff, 0x00030002,
647 0x9168, 0xffffffff, 0x00040007,
648 0x916c, 0xffffffff, 0x00060005,
649 0x9170, 0xffffffff, 0x00090008,
650 0x9174, 0xffffffff, 0x00020001,
651 0x9178, 0xffffffff, 0x00040003,
652 0x917c, 0xffffffff, 0x00000007,
653 0x9180, 0xffffffff, 0x00060005,
654 0x9184, 0xffffffff, 0x00090008,
655 0x9188, 0xffffffff, 0x00030002,
656 0x918c, 0xffffffff, 0x00050004,
657 0x9190, 0xffffffff, 0x00000008,
658 0x9194, 0xffffffff, 0x00070006,
659 0x9198, 0xffffffff, 0x000a0009,
660 0x919c, 0xffffffff, 0x00040003,
661 0x91a0, 0xffffffff, 0x00060005,
662 0x91a4, 0xffffffff, 0x00000009,
663 0x91a8, 0xffffffff, 0x00080007,
664 0x91ac, 0xffffffff, 0x000b000a,
665 0x91b0, 0xffffffff, 0x00050004,
666 0x91b4, 0xffffffff, 0x00070006,
667 0x91b8, 0xffffffff, 0x0008000b,
668 0x91bc, 0xffffffff, 0x000a0009,
669 0x91c0, 0xffffffff, 0x000d000c,
670 0x91c4, 0xffffffff, 0x00060005,
671 0x91c8, 0xffffffff, 0x00080007,
672 0x91cc, 0xffffffff, 0x0000000b,
673 0x91d0, 0xffffffff, 0x000a0009,
674 0x91d4, 0xffffffff, 0x000d000c,
675 0x91d8, 0xffffffff, 0x00070006,
676 0x91dc, 0xffffffff, 0x00090008,
677 0x91e0, 0xffffffff, 0x0000000c,
678 0x91e4, 0xffffffff, 0x000b000a,
679 0x91e8, 0xffffffff, 0x000e000d,
680 0x91ec, 0xffffffff, 0x00080007,
681 0x91f0, 0xffffffff, 0x000a0009,
682 0x91f4, 0xffffffff, 0x0000000d,
683 0x91f8, 0xffffffff, 0x000c000b,
684 0x91fc, 0xffffffff, 0x000f000e,
685 0x9200, 0xffffffff, 0x00090008,
686 0x9204, 0xffffffff, 0x000b000a,
687 0x9208, 0xffffffff, 0x000c000f,
688 0x920c, 0xffffffff, 0x000e000d,
689 0x9210, 0xffffffff, 0x00110010,
690 0x9214, 0xffffffff, 0x000a0009,
691 0x9218, 0xffffffff, 0x000c000b,
692 0x921c, 0xffffffff, 0x0000000f,
693 0x9220, 0xffffffff, 0x000e000d,
694 0x9224, 0xffffffff, 0x00110010,
695 0x9228, 0xffffffff, 0x000b000a,
696 0x922c, 0xffffffff, 0x000d000c,
697 0x9230, 0xffffffff, 0x00000010,
698 0x9234, 0xffffffff, 0x000f000e,
699 0x9238, 0xffffffff, 0x00120011,
700 0x923c, 0xffffffff, 0x000c000b,
701 0x9240, 0xffffffff, 0x000e000d,
702 0x9244, 0xffffffff, 0x00000011,
703 0x9248, 0xffffffff, 0x0010000f,
704 0x924c, 0xffffffff, 0x00130012,
705 0x9250, 0xffffffff, 0x000d000c,
706 0x9254, 0xffffffff, 0x000f000e,
707 0x9258, 0xffffffff, 0x00100013,
708 0x925c, 0xffffffff, 0x00120011,
709 0x9260, 0xffffffff, 0x00150014,
710 0x9264, 0xffffffff, 0x000e000d,
711 0x9268, 0xffffffff, 0x0010000f,
712 0x926c, 0xffffffff, 0x00000013,
713 0x9270, 0xffffffff, 0x00120011,
714 0x9274, 0xffffffff, 0x00150014,
715 0x9278, 0xffffffff, 0x000f000e,
716 0x927c, 0xffffffff, 0x00110010,
717 0x9280, 0xffffffff, 0x00000014,
718 0x9284, 0xffffffff, 0x00130012,
719 0x9288, 0xffffffff, 0x00160015,
720 0x928c, 0xffffffff, 0x0010000f,
721 0x9290, 0xffffffff, 0x00120011,
722 0x9294, 0xffffffff, 0x00000015,
723 0x9298, 0xffffffff, 0x00140013,
724 0x929c, 0xffffffff, 0x00170016,
725 0x9150, 0xffffffff, 0x96940200,
726 0x8708, 0xffffffff, 0x00900100,
727 0xc478, 0xffffffff, 0x00000080,
728 0xc404, 0xffffffff, 0x0020003f,
729 0x30, 0xffffffff, 0x0000001c,
730 0x34, 0x000f0000, 0x000f0000,
731 0x160c, 0xffffffff, 0x00000100,
732 0x1024, 0xffffffff, 0x00000100,
733 0x102c, 0x00000101, 0x00000000,
734 0x20a8, 0xffffffff, 0x00000104,
735 0x264c, 0x000c0000, 0x000c0000,
736 0x2648, 0x000c0000, 0x000c0000,
737 0x55e4, 0xff000fff, 0x00000100,
738 0x55e8, 0x00000001, 0x00000001,
739 0x2f50, 0x00000001, 0x00000001,
740 0x30cc, 0xc0000fff, 0x00000104,
741 0xc1e4, 0x00000001, 0x00000001,
742 0xd0c0, 0xfffffff0, 0x00000100,
743 0xd8c0, 0xfffffff0, 0x00000100
748 0xc400, 0xffffffff, 0xfffffffc,
749 0x802c, 0xffffffff, 0xe0000000,
750 0x9a60, 0xffffffff, 0x00000100,
751 0x92a4, 0xffffffff, 0x00000100,
752 0xc164, 0xffffffff, 0x00000100,
753 0x9774, 0xffffffff, 0x00000100,
754 0x8984, 0xffffffff, 0x06000100,
755 0x8a18, 0xffffffff, 0x00000100,
756 0x92a0, 0xffffffff, 0x00000100,
757 0xc380, 0xffffffff, 0x00000100,
758 0x8b28, 0xffffffff, 0x00000100,
759 0x9144, 0xffffffff, 0x00000100,
760 0x8d88, 0xffffffff, 0x00000100,
761 0x8d8c, 0xffffffff, 0x00000100,
762 0x9030, 0xffffffff, 0x00000100,
763 0x9034, 0xffffffff, 0x00000100,
764 0x9038, 0xffffffff, 0x00000100,
765 0x903c, 0xffffffff, 0x00000100,
766 0xad80, 0xffffffff, 0x00000100,
767 0xac54, 0xffffffff, 0x00000100,
768 0x897c, 0xffffffff, 0x06000100,
769 0x9868, 0xffffffff, 0x00000100,
770 0x9510, 0xffffffff, 0x00000100,
771 0xaf04, 0xffffffff, 0x00000100,
772 0xae04, 0xffffffff, 0x00000100,
773 0x949c, 0xffffffff, 0x00000100,
774 0x802c, 0xffffffff, 0xe0000000,
775 0x9160, 0xffffffff, 0x00010000,
776 0x9164, 0xffffffff, 0x00030002,
777 0x9168, 0xffffffff, 0x00040007,
778 0x916c, 0xffffffff, 0x00060005,
779 0x9170, 0xffffffff, 0x00090008,
780 0x9174, 0xffffffff, 0x00020001,
781 0x9178, 0xffffffff, 0x00040003,
782 0x917c, 0xffffffff, 0x00000007,
783 0x9180, 0xffffffff, 0x00060005,
784 0x9184, 0xffffffff, 0x00090008,
785 0x9188, 0xffffffff, 0x00030002,
786 0x918c, 0xffffffff, 0x00050004,
787 0x9190, 0xffffffff, 0x00000008,
788 0x9194, 0xffffffff, 0x00070006,
789 0x9198, 0xffffffff, 0x000a0009,
790 0x919c, 0xffffffff, 0x00040003,
791 0x91a0, 0xffffffff, 0x00060005,
792 0x91a4, 0xffffffff, 0x00000009,
793 0x91a8, 0xffffffff, 0x00080007,
794 0x91ac, 0xffffffff, 0x000b000a,
795 0x91b0, 0xffffffff, 0x00050004,
796 0x91b4, 0xffffffff, 0x00070006,
797 0x91b8, 0xffffffff, 0x0008000b,
798 0x91bc, 0xffffffff, 0x000a0009,
799 0x91c0, 0xffffffff, 0x000d000c,
800 0x9200, 0xffffffff, 0x00090008,
801 0x9204, 0xffffffff, 0x000b000a,
802 0x9208, 0xffffffff, 0x000c000f,
803 0x920c, 0xffffffff, 0x000e000d,
804 0x9210, 0xffffffff, 0x00110010,
805 0x9214, 0xffffffff, 0x000a0009,
806 0x9218, 0xffffffff, 0x000c000b,
807 0x921c, 0xffffffff, 0x0000000f,
808 0x9220, 0xffffffff, 0x000e000d,
809 0x9224, 0xffffffff, 0x00110010,
810 0x9228, 0xffffffff, 0x000b000a,
811 0x922c, 0xffffffff, 0x000d000c,
812 0x9230, 0xffffffff, 0x00000010,
813 0x9234, 0xffffffff, 0x000f000e,
814 0x9238, 0xffffffff, 0x00120011,
815 0x923c, 0xffffffff, 0x000c000b,
816 0x9240, 0xffffffff, 0x000e000d,
817 0x9244, 0xffffffff, 0x00000011,
818 0x9248, 0xffffffff, 0x0010000f,
819 0x924c, 0xffffffff, 0x00130012,
820 0x9250, 0xffffffff, 0x000d000c,
821 0x9254, 0xffffffff, 0x000f000e,
822 0x9258, 0xffffffff, 0x00100013,
823 0x925c, 0xffffffff, 0x00120011,
824 0x9260, 0xffffffff, 0x00150014,
825 0x9150, 0xffffffff, 0x96940200,
826 0x8708, 0xffffffff, 0x00900100,
827 0xc478, 0xffffffff, 0x00000080,
828 0xc404, 0xffffffff, 0x0020003f,
829 0x30, 0xffffffff, 0x0000001c,
830 0x34, 0x000f0000, 0x000f0000,
831 0x160c, 0xffffffff, 0x00000100,
832 0x1024, 0xffffffff, 0x00000100,
833 0x102c, 0x00000101, 0x00000000,
834 0x20a8, 0xffffffff, 0x00000104,
835 0x55e4, 0xff000fff, 0x00000100,
836 0x55e8, 0x00000001, 0x00000001,
837 0x2f50, 0x00000001, 0x00000001,
838 0x30cc, 0xc0000fff, 0x00000104,
839 0xc1e4, 0x00000001, 0x00000001,
840 0xd0c0, 0xfffffff0, 0x00000100,
841 0xd8c0, 0xfffffff0, 0x00000100
846 0xc400, 0xffffffff, 0xfffffffc,
847 0x802c, 0xffffffff, 0xe0000000,
848 0x9a60, 0xffffffff, 0x00000100,
849 0x92a4, 0xffffffff, 0x00000100,
850 0xc164, 0xffffffff, 0x00000100,
851 0x9774, 0xffffffff, 0x00000100,
852 0x8984, 0xffffffff, 0x06000100,
853 0x8a18, 0xffffffff, 0x00000100,
854 0x92a0, 0xffffffff, 0x00000100,
855 0xc380, 0xffffffff, 0x00000100,
856 0x8b28, 0xffffffff, 0x00000100,
857 0x9144, 0xffffffff, 0x00000100,
858 0x8d88, 0xffffffff, 0x00000100,
859 0x8d8c, 0xffffffff, 0x00000100,
860 0x9030, 0xffffffff, 0x00000100,
861 0x9034, 0xffffffff, 0x00000100,
862 0x9038, 0xffffffff, 0x00000100,
863 0x903c, 0xffffffff, 0x00000100,
864 0xad80, 0xffffffff, 0x00000100,
865 0xac54, 0xffffffff, 0x00000100,
866 0x897c, 0xffffffff, 0x06000100,
867 0x9868, 0xffffffff, 0x00000100,
868 0x9510, 0xffffffff, 0x00000100,
869 0xaf04, 0xffffffff, 0x00000100,
870 0xae04, 0xffffffff, 0x00000100,
871 0x949c, 0xffffffff, 0x00000100,
872 0x802c, 0xffffffff, 0xe0000000,
873 0x9160, 0xffffffff, 0x00010000,
874 0x9164, 0xffffffff, 0x00030002,
875 0x9168, 0xffffffff, 0x00040007,
876 0x916c, 0xffffffff, 0x00060005,
877 0x9170, 0xffffffff, 0x00090008,
878 0x9174, 0xffffffff, 0x00020001,
879 0x9178, 0xffffffff, 0x00040003,
880 0x917c, 0xffffffff, 0x00000007,
881 0x9180, 0xffffffff, 0x00060005,
882 0x9184, 0xffffffff, 0x00090008,
883 0x9188, 0xffffffff, 0x00030002,
884 0x918c, 0xffffffff, 0x00050004,
885 0x9190, 0xffffffff, 0x00000008,
886 0x9194, 0xffffffff, 0x00070006,
887 0x9198, 0xffffffff, 0x000a0009,
888 0x919c, 0xffffffff, 0x00040003,
889 0x91a0, 0xffffffff, 0x00060005,
890 0x91a4, 0xffffffff, 0x00000009,
891 0x91a8, 0xffffffff, 0x00080007,
892 0x91ac, 0xffffffff, 0x000b000a,
893 0x91b0, 0xffffffff, 0x00050004,
894 0x91b4, 0xffffffff, 0x00070006,
895 0x91b8, 0xffffffff, 0x0008000b,
896 0x91bc, 0xffffffff, 0x000a0009,
897 0x91c0, 0xffffffff, 0x000d000c,
898 0x9200, 0xffffffff, 0x00090008,
899 0x9204, 0xffffffff, 0x000b000a,
900 0x9208, 0xffffffff, 0x000c000f,
901 0x920c, 0xffffffff, 0x000e000d,
902 0x9210, 0xffffffff, 0x00110010,
903 0x9214, 0xffffffff, 0x000a0009,
904 0x9218, 0xffffffff, 0x000c000b,
905 0x921c, 0xffffffff, 0x0000000f,
906 0x9220, 0xffffffff, 0x000e000d,
907 0x9224, 0xffffffff, 0x00110010,
908 0x9228, 0xffffffff, 0x000b000a,
909 0x922c, 0xffffffff, 0x000d000c,
910 0x9230, 0xffffffff, 0x00000010,
911 0x9234, 0xffffffff, 0x000f000e,
912 0x9238, 0xffffffff, 0x00120011,
913 0x923c, 0xffffffff, 0x000c000b,
914 0x9240, 0xffffffff, 0x000e000d,
915 0x9244, 0xffffffff, 0x00000011,
916 0x9248, 0xffffffff, 0x0010000f,
917 0x924c, 0xffffffff, 0x00130012,
918 0x9250, 0xffffffff, 0x000d000c,
919 0x9254, 0xffffffff, 0x000f000e,
920 0x9258, 0xffffffff, 0x00100013,
921 0x925c, 0xffffffff, 0x00120011,
922 0x9260, 0xffffffff, 0x00150014,
923 0x9150, 0xffffffff, 0x96940200,
924 0x8708, 0xffffffff, 0x00900100,
925 0xc478, 0xffffffff, 0x00000080,
926 0xc404, 0xffffffff, 0x0020003f,
927 0x30, 0xffffffff, 0x0000001c,
928 0x34, 0x000f0000, 0x000f0000,
929 0x160c, 0xffffffff, 0x00000100,
930 0x1024, 0xffffffff, 0x00000100,
931 0x102c, 0x00000101, 0x00000000,
932 0x20a8, 0xffffffff, 0x00000104,
933 0x264c, 0x000c0000, 0x000c0000,
934 0x2648, 0x000c0000, 0x000c0000,
935 0x55e4, 0xff000fff, 0x00000100,
936 0x55e8, 0x00000001, 0x00000001,
937 0x2f50, 0x00000001, 0x00000001,
938 0x30cc, 0xc0000fff, 0x00000104,
939 0xc1e4, 0x00000001, 0x00000001,
940 0xd0c0, 0xfffffff0, 0x00000100,
941 0xd8c0, 0xfffffff0, 0x00000100
946 0xc400, 0xffffffff, 0xfffffffc,
947 0x802c, 0xffffffff, 0xe0000000,
948 0x9a60, 0xffffffff, 0x00000100,
949 0x92a4, 0xffffffff, 0x00000100,
950 0xc164, 0xffffffff, 0x00000100,
951 0x9774, 0xffffffff, 0x00000100,
952 0x8984, 0xffffffff, 0x06000100,
953 0x8a18, 0xffffffff, 0x00000100,
954 0x92a0, 0xffffffff, 0x00000100,
955 0xc380, 0xffffffff, 0x00000100,
956 0x8b28, 0xffffffff, 0x00000100,
957 0x9144, 0xffffffff, 0x00000100,
958 0x8d88, 0xffffffff, 0x00000100,
959 0x8d8c, 0xffffffff, 0x00000100,
960 0x9030, 0xffffffff, 0x00000100,
961 0x9034, 0xffffffff, 0x00000100,
962 0x9038, 0xffffffff, 0x00000100,
963 0x903c, 0xffffffff, 0x00000100,
964 0xad80, 0xffffffff, 0x00000100,
965 0xac54, 0xffffffff, 0x00000100,
966 0x897c, 0xffffffff, 0x06000100,
967 0x9868, 0xffffffff, 0x00000100,
968 0x9510, 0xffffffff, 0x00000100,
969 0xaf04, 0xffffffff, 0x00000100,
970 0xae04, 0xffffffff, 0x00000100,
971 0x949c, 0xffffffff, 0x00000100,
972 0x802c, 0xffffffff, 0xe0000000,
973 0x9160, 0xffffffff, 0x00010000,
974 0x9164, 0xffffffff, 0x00030002,
975 0x9168, 0xffffffff, 0x00040007,
976 0x916c, 0xffffffff, 0x00060005,
977 0x9170, 0xffffffff, 0x00090008,
978 0x9174, 0xffffffff, 0x00020001,
979 0x9178, 0xffffffff, 0x00040003,
980 0x917c, 0xffffffff, 0x00000007,
981 0x9180, 0xffffffff, 0x00060005,
982 0x9184, 0xffffffff, 0x00090008,
983 0x9188, 0xffffffff, 0x00030002,
984 0x918c, 0xffffffff, 0x00050004,
985 0x9190, 0xffffffff, 0x00000008,
986 0x9194, 0xffffffff, 0x00070006,
987 0x9198, 0xffffffff, 0x000a0009,
988 0x919c, 0xffffffff, 0x00040003,
989 0x91a0, 0xffffffff, 0x00060005,
990 0x91a4, 0xffffffff, 0x00000009,
991 0x91a8, 0xffffffff, 0x00080007,
992 0x91ac, 0xffffffff, 0x000b000a,
993 0x91b0, 0xffffffff, 0x00050004,
994 0x91b4, 0xffffffff, 0x00070006,
995 0x91b8, 0xffffffff, 0x0008000b,
996 0x91bc, 0xffffffff, 0x000a0009,
997 0x91c0, 0xffffffff, 0x000d000c,
998 0x91c4, 0xffffffff, 0x00060005,
999 0x91c8, 0xffffffff, 0x00080007,
1000 0x91cc, 0xffffffff, 0x0000000b,
1001 0x91d0, 0xffffffff, 0x000a0009,
1002 0x91d4, 0xffffffff, 0x000d000c,
1003 0x9150, 0xffffffff, 0x96940200,
1004 0x8708, 0xffffffff, 0x00900100,
1005 0xc478, 0xffffffff, 0x00000080,
1006 0xc404, 0xffffffff, 0x0020003f,
1007 0x30, 0xffffffff, 0x0000001c,
1008 0x34, 0x000f0000, 0x000f0000,
1009 0x160c, 0xffffffff, 0x00000100,
1010 0x1024, 0xffffffff, 0x00000100,
1011 0x102c, 0x00000101, 0x00000000,
1012 0x20a8, 0xffffffff, 0x00000104,
1013 0x264c, 0x000c0000, 0x000c0000,
1014 0x2648, 0x000c0000, 0x000c0000,
1015 0x55e4, 0xff000fff, 0x00000100,
1016 0x55e8, 0x00000001, 0x00000001,
1017 0x2f50, 0x00000001, 0x00000001,
1018 0x30cc, 0xc0000fff, 0x00000104,
1019 0xc1e4, 0x00000001, 0x00000001,
1020 0xd0c0, 0xfffffff0, 0x00000100,
1021 0xd8c0, 0xfffffff0, 0x00000100
1026 0xc400, 0xffffffff, 0xfffffffc,
1027 0x802c, 0xffffffff, 0xe0000000,
1028 0x9a60, 0xffffffff, 0x00000100,
1029 0x92a4, 0xffffffff, 0x00000100,
1030 0xc164, 0xffffffff, 0x00000100,
1031 0x9774, 0xffffffff, 0x00000100,
1032 0x8984, 0xffffffff, 0x06000100,
1033 0x8a18, 0xffffffff, 0x00000100,
1034 0x92a0, 0xffffffff, 0x00000100,
1035 0xc380, 0xffffffff, 0x00000100,
1036 0x8b28, 0xffffffff, 0x00000100,
1037 0x9144, 0xffffffff, 0x00000100,
1038 0x8d88, 0xffffffff, 0x00000100,
1039 0x8d8c, 0xffffffff, 0x00000100,
1040 0x9030, 0xffffffff, 0x00000100,
1041 0x9034, 0xffffffff, 0x00000100,
1042 0x9038, 0xffffffff, 0x00000100,
1043 0x903c, 0xffffffff, 0x00000100,
1044 0xad80, 0xffffffff, 0x00000100,
1045 0xac54, 0xffffffff, 0x00000100,
1046 0x897c, 0xffffffff, 0x06000100,
1047 0x9868, 0xffffffff, 0x00000100,
1048 0x9510, 0xffffffff, 0x00000100,
1049 0xaf04, 0xffffffff, 0x00000100,
1050 0xae04, 0xffffffff, 0x00000100,
1051 0x949c, 0xffffffff, 0x00000100,
1052 0x802c, 0xffffffff, 0xe0000000,
1053 0x9160, 0xffffffff, 0x00010000,
1054 0x9164, 0xffffffff, 0x00030002,
1055 0x9168, 0xffffffff, 0x00040007,
1056 0x916c, 0xffffffff, 0x00060005,
1057 0x9170, 0xffffffff, 0x00090008,
1058 0x9174, 0xffffffff, 0x00020001,
1059 0x9178, 0xffffffff, 0x00040003,
1060 0x917c, 0xffffffff, 0x00000007,
1061 0x9180, 0xffffffff, 0x00060005,
1062 0x9184, 0xffffffff, 0x00090008,
1063 0x9188, 0xffffffff, 0x00030002,
1064 0x918c, 0xffffffff, 0x00050004,
1065 0x9190, 0xffffffff, 0x00000008,
1066 0x9194, 0xffffffff, 0x00070006,
1067 0x9198, 0xffffffff, 0x000a0009,
1068 0x919c, 0xffffffff, 0x00040003,
1069 0x91a0, 0xffffffff, 0x00060005,
1070 0x91a4, 0xffffffff, 0x00000009,
1071 0x91a8, 0xffffffff, 0x00080007,
1072 0x91ac, 0xffffffff, 0x000b000a,
1073 0x91b0, 0xffffffff, 0x00050004,
1074 0x91b4, 0xffffffff, 0x00070006,
1075 0x91b8, 0xffffffff, 0x0008000b,
1076 0x91bc, 0xffffffff, 0x000a0009,
1077 0x91c0, 0xffffffff, 0x000d000c,
1078 0x91c4, 0xffffffff, 0x00060005,
1079 0x91c8, 0xffffffff, 0x00080007,
1080 0x91cc, 0xffffffff, 0x0000000b,
1081 0x91d0, 0xffffffff, 0x000a0009,
1082 0x91d4, 0xffffffff, 0x000d000c,
1083 0x9150, 0xffffffff, 0x96940200,
1084 0x8708, 0xffffffff, 0x00900100,
1085 0xc478, 0xffffffff, 0x00000080,
1086 0xc404, 0xffffffff, 0x0020003f,
1087 0x30, 0xffffffff, 0x0000001c,
1088 0x34, 0x000f0000, 0x000f0000,
1089 0x160c, 0xffffffff, 0x00000100,
1090 0x1024, 0xffffffff, 0x00000100,
1091 0x20a8, 0xffffffff, 0x00000104,
1092 0x264c, 0x000c0000, 0x000c0000,
1093 0x2648, 0x000c0000, 0x000c0000,
1094 0x2f50, 0x00000001, 0x00000001,
1095 0x30cc, 0xc0000fff, 0x00000104,
1096 0xc1e4, 0x00000001, 0x00000001,
1097 0xd0c0, 0xfffffff0, 0x00000100,
1098 0xd8c0, 0xfffffff0, 0x00000100
1103 0x353c, 0xffffffff, 0x40000,
1104 0x3538, 0xffffffff, 0x200010ff,
1105 0x353c, 0xffffffff, 0x0,
1106 0x353c, 0xffffffff, 0x0,
1107 0x353c, 0xffffffff, 0x0,
1108 0x353c, 0xffffffff, 0x0,
1109 0x353c, 0xffffffff, 0x0,
1110 0x353c, 0xffffffff, 0x7007,
1111 0x3538, 0xffffffff, 0x300010ff,
1112 0x353c, 0xffffffff, 0x0,
1113 0x353c, 0xffffffff, 0x0,
1114 0x353c, 0xffffffff, 0x0,
1115 0x353c, 0xffffffff, 0x0,
1116 0x353c, 0xffffffff, 0x0,
1117 0x353c, 0xffffffff, 0x400000,
1118 0x3538, 0xffffffff, 0x100010ff,
1119 0x353c, 0xffffffff, 0x0,
1120 0x353c, 0xffffffff, 0x0,
1121 0x353c, 0xffffffff, 0x0,
1122 0x353c, 0xffffffff, 0x0,
1123 0x353c, 0xffffffff, 0x0,
1124 0x353c, 0xffffffff, 0x120200,
1125 0x3538, 0xffffffff, 0x500010ff,
1126 0x353c, 0xffffffff, 0x0,
1127 0x353c, 0xffffffff, 0x0,
1128 0x353c, 0xffffffff, 0x0,
1129 0x353c, 0xffffffff, 0x0,
1130 0x353c, 0xffffffff, 0x0,
1131 0x353c, 0xffffffff, 0x1e1e16,
1132 0x3538, 0xffffffff, 0x600010ff,
1133 0x353c, 0xffffffff, 0x0,
1134 0x353c, 0xffffffff, 0x0,
1135 0x353c, 0xffffffff, 0x0,
1136 0x353c, 0xffffffff, 0x0,
1137 0x353c, 0xffffffff, 0x0,
1138 0x353c, 0xffffffff, 0x171f1e,
1139 0x3538, 0xffffffff, 0x700010ff,
1140 0x353c, 0xffffffff, 0x0,
1141 0x353c, 0xffffffff, 0x0,
1142 0x353c, 0xffffffff, 0x0,
1143 0x353c, 0xffffffff, 0x0,
1144 0x353c, 0xffffffff, 0x0,
1145 0x353c, 0xffffffff, 0x0,
1146 0x3538, 0xffffffff, 0x9ff,
1147 0x3500, 0xffffffff, 0x0,
1148 0x3504, 0xffffffff, 0x10000800,
1149 0x3504, 0xffffffff, 0xf,
1150 0x3504, 0xffffffff, 0xf,
1151 0x3500, 0xffffffff, 0x4,
1152 0x3504, 0xffffffff, 0x1000051e,
1153 0x3504, 0xffffffff, 0xffff,
1154 0x3504, 0xffffffff, 0xffff,
1155 0x3500, 0xffffffff, 0x8,
1156 0x3504, 0xffffffff, 0x80500,
1157 0x3500, 0xffffffff, 0x12,
1158 0x3504, 0xffffffff, 0x9050c,
1159 0x3500, 0xffffffff, 0x1d,
1160 0x3504, 0xffffffff, 0xb052c,
1161 0x3500, 0xffffffff, 0x2a,
1162 0x3504, 0xffffffff, 0x1053e,
1163 0x3500, 0xffffffff, 0x2d,
1164 0x3504, 0xffffffff, 0x10546,
1165 0x3500, 0xffffffff, 0x30,
1166 0x3504, 0xffffffff, 0xa054e,
1167 0x3500, 0xffffffff, 0x3c,
1168 0x3504, 0xffffffff, 0x1055f,
1169 0x3500, 0xffffffff, 0x3f,
1170 0x3504, 0xffffffff, 0x10567,
1171 0x3500, 0xffffffff, 0x42,
1172 0x3504, 0xffffffff, 0x1056f,
1173 0x3500, 0xffffffff, 0x45,
1174 0x3504, 0xffffffff, 0x10572,
1175 0x3500, 0xffffffff, 0x48,
1176 0x3504, 0xffffffff, 0x20575,
1177 0x3500, 0xffffffff, 0x4c,
1178 0x3504, 0xffffffff, 0x190801,
1179 0x3500, 0xffffffff, 0x67,
1180 0x3504, 0xffffffff, 0x1082a,
1181 0x3500, 0xffffffff, 0x6a,
1182 0x3504, 0xffffffff, 0x1b082d,
1183 0x3500, 0xffffffff, 0x87,
1184 0x3504, 0xffffffff, 0x310851,
1185 0x3500, 0xffffffff, 0xba,
1186 0x3504, 0xffffffff, 0x891,
1187 0x3500, 0xffffffff, 0xbc,
1188 0x3504, 0xffffffff, 0x893,
1189 0x3500, 0xffffffff, 0xbe,
1190 0x3504, 0xffffffff, 0x20895,
1191 0x3500, 0xffffffff, 0xc2,
1192 0x3504, 0xffffffff, 0x20899,
1193 0x3500, 0xffffffff, 0xc6,
1194 0x3504, 0xffffffff, 0x2089d,
1195 0x3500, 0xffffffff, 0xca,
1196 0x3504, 0xffffffff, 0x8a1,
1197 0x3500, 0xffffffff, 0xcc,
1198 0x3504, 0xffffffff, 0x8a3,
1199 0x3500, 0xffffffff, 0xce,
1200 0x3504, 0xffffffff, 0x308a5,
1201 0x3500, 0xffffffff, 0xd3,
1202 0x3504, 0xffffffff, 0x6d08cd,
1203 0x3500, 0xffffffff, 0x142,
1204 0x3504, 0xffffffff, 0x2000095a,
1205 0x3504, 0xffffffff, 0x1,
1206 0x3500, 0xffffffff, 0x144,
1207 0x3504, 0xffffffff, 0x301f095b,
1208 0x3500, 0xffffffff, 0x165,
1209 0x3504, 0xffffffff, 0xc094d,
1210 0x3500, 0xffffffff, 0x173,
1211 0x3504, 0xffffffff, 0xf096d,
1212 0x3500, 0xffffffff, 0x184,
1213 0x3504, 0xffffffff, 0x15097f,
1214 0x3500, 0xffffffff, 0x19b,
1215 0x3504, 0xffffffff, 0xc0998,
1216 0x3500, 0xffffffff, 0x1a9,
1217 0x3504, 0xffffffff, 0x409a7,
1218 0x3500, 0xffffffff, 0x1af,
1219 0x3504, 0xffffffff, 0xcdc,
1220 0x3500, 0xffffffff, 0x1b1,
1221 0x3504, 0xffffffff, 0x800,
1222 0x3508, 0xffffffff, 0x6c9b2000,
1223 0x3510, 0xfc00, 0x2000,
1224 0x3544, 0xffffffff, 0xfc0,
1225 0x28d4, 0x00000100, 0x100
1230 switch (rdev->family) { in si_init_golden_registers()
1298 * si_get_allowed_info_register - fetch the register for the info ioctl
1304 * Returns 0 for success or -EINVAL for an invalid register
1321 return 0; in si_get_allowed_info_register()
1323 return -EINVAL; in si_get_allowed_info_register()
1331 * si_get_xclk - get the xclk
1340 u32 reference_clock = rdev->clock.spll.reference_freq; in si_get_xclk()
1358 int actual_temp = 0; in si_get_temp()
1363 if (temp & 0x200) in si_get_temp()
1366 actual_temp = temp & 0x1ff; in si_get_temp()
1376 {0x0000006f, 0x03044000},
1377 {0x00000070, 0x0480c018},
1378 {0x00000071, 0x00000040},
1379 {0x00000072, 0x01000000},
1380 {0x00000074, 0x000000ff},
1381 {0x00000075, 0x00143400},
1382 {0x00000076, 0x08ec0800},
1383 {0x00000077, 0x040000cc},
1384 {0x00000079, 0x00000000},
1385 {0x0000007a, 0x21000409},
1386 {0x0000007c, 0x00000000},
1387 {0x0000007d, 0xe8000000},
1388 {0x0000007e, 0x044408a8},
1389 {0x0000007f, 0x00000003},
1390 {0x00000080, 0x00000000},
1391 {0x00000081, 0x01000000},
1392 {0x00000082, 0x02000000},
1393 {0x00000083, 0x00000000},
1394 {0x00000084, 0xe3f3e4f4},
1395 {0x00000085, 0x00052024},
1396 {0x00000087, 0x00000000},
1397 {0x00000088, 0x66036603},
1398 {0x00000089, 0x01000000},
1399 {0x0000008b, 0x1c0a0000},
1400 {0x0000008c, 0xff010000},
1401 {0x0000008e, 0xffffefff},
1402 {0x0000008f, 0xfff3efff},
1403 {0x00000090, 0xfff3efbf},
1404 {0x00000094, 0x00101101},
1405 {0x00000095, 0x00000fff},
1406 {0x00000096, 0x00116fff},
1407 {0x00000097, 0x60010000},
1408 {0x00000098, 0x10010000},
1409 {0x00000099, 0x00006000},
1410 {0x0000009a, 0x00001000},
1411 {0x0000009f, 0x00a77400}
1415 {0x0000006f, 0x03044000},
1416 {0x00000070, 0x0480c018},
1417 {0x00000071, 0x00000040},
1418 {0x00000072, 0x01000000},
1419 {0x00000074, 0x000000ff},
1420 {0x00000075, 0x00143400},
1421 {0x00000076, 0x08ec0800},
1422 {0x00000077, 0x040000cc},
1423 {0x00000079, 0x00000000},
1424 {0x0000007a, 0x21000409},
1425 {0x0000007c, 0x00000000},
1426 {0x0000007d, 0xe8000000},
1427 {0x0000007e, 0x044408a8},
1428 {0x0000007f, 0x00000003},
1429 {0x00000080, 0x00000000},
1430 {0x00000081, 0x01000000},
1431 {0x00000082, 0x02000000},
1432 {0x00000083, 0x00000000},
1433 {0x00000084, 0xe3f3e4f4},
1434 {0x00000085, 0x00052024},
1435 {0x00000087, 0x00000000},
1436 {0x00000088, 0x66036603},
1437 {0x00000089, 0x01000000},
1438 {0x0000008b, 0x1c0a0000},
1439 {0x0000008c, 0xff010000},
1440 {0x0000008e, 0xffffefff},
1441 {0x0000008f, 0xfff3efff},
1442 {0x00000090, 0xfff3efbf},
1443 {0x00000094, 0x00101101},
1444 {0x00000095, 0x00000fff},
1445 {0x00000096, 0x00116fff},
1446 {0x00000097, 0x60010000},
1447 {0x00000098, 0x10010000},
1448 {0x00000099, 0x00006000},
1449 {0x0000009a, 0x00001000},
1450 {0x0000009f, 0x00a47400}
1454 {0x0000006f, 0x03044000},
1455 {0x00000070, 0x0480c018},
1456 {0x00000071, 0x00000040},
1457 {0x00000072, 0x01000000},
1458 {0x00000074, 0x000000ff},
1459 {0x00000075, 0x00143400},
1460 {0x00000076, 0x08ec0800},
1461 {0x00000077, 0x040000cc},
1462 {0x00000079, 0x00000000},
1463 {0x0000007a, 0x21000409},
1464 {0x0000007c, 0x00000000},
1465 {0x0000007d, 0xe8000000},
1466 {0x0000007e, 0x044408a8},
1467 {0x0000007f, 0x00000003},
1468 {0x00000080, 0x00000000},
1469 {0x00000081, 0x01000000},
1470 {0x00000082, 0x02000000},
1471 {0x00000083, 0x00000000},
1472 {0x00000084, 0xe3f3e4f4},
1473 {0x00000085, 0x00052024},
1474 {0x00000087, 0x00000000},
1475 {0x00000088, 0x66036603},
1476 {0x00000089, 0x01000000},
1477 {0x0000008b, 0x1c0a0000},
1478 {0x0000008c, 0xff010000},
1479 {0x0000008e, 0xffffefff},
1480 {0x0000008f, 0xfff3efff},
1481 {0x00000090, 0xfff3efbf},
1482 {0x00000094, 0x00101101},
1483 {0x00000095, 0x00000fff},
1484 {0x00000096, 0x00116fff},
1485 {0x00000097, 0x60010000},
1486 {0x00000098, 0x10010000},
1487 {0x00000099, 0x00006000},
1488 {0x0000009a, 0x00001000},
1489 {0x0000009f, 0x00a37400}
1493 {0x0000006f, 0x03044000},
1494 {0x00000070, 0x0480c018},
1495 {0x00000071, 0x00000040},
1496 {0x00000072, 0x01000000},
1497 {0x00000074, 0x000000ff},
1498 {0x00000075, 0x00143400},
1499 {0x00000076, 0x08ec0800},
1500 {0x00000077, 0x040000cc},
1501 {0x00000079, 0x00000000},
1502 {0x0000007a, 0x21000409},
1503 {0x0000007c, 0x00000000},
1504 {0x0000007d, 0xe8000000},
1505 {0x0000007e, 0x044408a8},
1506 {0x0000007f, 0x00000003},
1507 {0x00000080, 0x00000000},
1508 {0x00000081, 0x01000000},
1509 {0x00000082, 0x02000000},
1510 {0x00000083, 0x00000000},
1511 {0x00000084, 0xe3f3e4f4},
1512 {0x00000085, 0x00052024},
1513 {0x00000087, 0x00000000},
1514 {0x00000088, 0x66036603},
1515 {0x00000089, 0x01000000},
1516 {0x0000008b, 0x1c0a0000},
1517 {0x0000008c, 0xff010000},
1518 {0x0000008e, 0xffffefff},
1519 {0x0000008f, 0xfff3efff},
1520 {0x00000090, 0xfff3efbf},
1521 {0x00000094, 0x00101101},
1522 {0x00000095, 0x00000fff},
1523 {0x00000096, 0x00116fff},
1524 {0x00000097, 0x60010000},
1525 {0x00000098, 0x10010000},
1526 {0x00000099, 0x00006000},
1527 {0x0000009a, 0x00001000},
1528 {0x0000009f, 0x00a17730}
1532 {0x0000006f, 0x03044000},
1533 {0x00000070, 0x0480c018},
1534 {0x00000071, 0x00000040},
1535 {0x00000072, 0x01000000},
1536 {0x00000074, 0x000000ff},
1537 {0x00000075, 0x00143400},
1538 {0x00000076, 0x08ec0800},
1539 {0x00000077, 0x040000cc},
1540 {0x00000079, 0x00000000},
1541 {0x0000007a, 0x21000409},
1542 {0x0000007c, 0x00000000},
1543 {0x0000007d, 0xe8000000},
1544 {0x0000007e, 0x044408a8},
1545 {0x0000007f, 0x00000003},
1546 {0x00000080, 0x00000000},
1547 {0x00000081, 0x01000000},
1548 {0x00000082, 0x02000000},
1549 {0x00000083, 0x00000000},
1550 {0x00000084, 0xe3f3e4f4},
1551 {0x00000085, 0x00052024},
1552 {0x00000087, 0x00000000},
1553 {0x00000088, 0x66036603},
1554 {0x00000089, 0x01000000},
1555 {0x0000008b, 0x1c0a0000},
1556 {0x0000008c, 0xff010000},
1557 {0x0000008e, 0xffffefff},
1558 {0x0000008f, 0xfff3efff},
1559 {0x00000090, 0xfff3efbf},
1560 {0x00000094, 0x00101101},
1561 {0x00000095, 0x00000fff},
1562 {0x00000096, 0x00116fff},
1563 {0x00000097, 0x60010000},
1564 {0x00000098, 0x10010000},
1565 {0x00000099, 0x00006000},
1566 {0x0000009a, 0x00001000},
1567 {0x0000009f, 0x00a07730}
1580 if (!rdev->mc_fw) in si_mc_load_microcode()
1581 return -EINVAL; in si_mc_load_microcode()
1583 if (rdev->new_fw) { in si_mc_load_microcode()
1585 (const struct mc_firmware_header_v1_0 *)rdev->mc_fw->data; in si_mc_load_microcode()
1587 radeon_ucode_print_mc_hdr(&hdr->header); in si_mc_load_microcode()
1588 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); in si_mc_load_microcode()
1590 (rdev->mc_fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); in si_mc_load_microcode()
1591 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; in si_mc_load_microcode()
1593 (rdev->mc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); in si_mc_load_microcode()
1595 ucode_size = rdev->mc_fw->size / 4; in si_mc_load_microcode()
1597 switch (rdev->family) { in si_mc_load_microcode()
1620 fw_data = (const __be32 *)rdev->mc_fw->data; in si_mc_load_microcode()
1625 if (running == 0) { in si_mc_load_microcode()
1627 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); in si_mc_load_microcode()
1628 WREG32(MC_SEQ_SUP_CNTL, 0x00000010); in si_mc_load_microcode()
1631 for (i = 0; i < regs_size; i++) { in si_mc_load_microcode()
1632 if (rdev->new_fw) { in si_mc_load_microcode()
1641 for (i = 0; i < ucode_size; i++) { in si_mc_load_microcode()
1642 if (rdev->new_fw) in si_mc_load_microcode()
1649 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); in si_mc_load_microcode()
1650 WREG32(MC_SEQ_SUP_CNTL, 0x00000004); in si_mc_load_microcode()
1651 WREG32(MC_SEQ_SUP_CNTL, 0x00000001); in si_mc_load_microcode()
1654 for (i = 0; i < rdev->usec_timeout; i++) { in si_mc_load_microcode()
1659 for (i = 0; i < rdev->usec_timeout; i++) { in si_mc_load_microcode()
1666 return 0; in si_mc_load_microcode()
1677 int new_fw = 0; in si_init_microcode()
1684 switch (rdev->family) { in si_init_microcode()
1698 if ((rdev->pdev->revision == 0x81) && in si_init_microcode()
1699 ((rdev->pdev->device == 0x6810) || in si_init_microcode()
1700 (rdev->pdev->device == 0x6811))) in si_init_microcode()
1713 if (((rdev->pdev->device == 0x6820) && in si_init_microcode()
1714 ((rdev->pdev->revision == 0x81) || in si_init_microcode()
1715 (rdev->pdev->revision == 0x83))) || in si_init_microcode()
1716 ((rdev->pdev->device == 0x6821) && in si_init_microcode()
1717 ((rdev->pdev->revision == 0x83) || in si_init_microcode()
1718 (rdev->pdev->revision == 0x87))) || in si_init_microcode()
1719 ((rdev->pdev->revision == 0x87) && in si_init_microcode()
1720 ((rdev->pdev->device == 0x6823) || in si_init_microcode()
1721 (rdev->pdev->device == 0x682b)))) in si_init_microcode()
1734 if (((rdev->pdev->revision == 0x81) && in si_init_microcode()
1735 ((rdev->pdev->device == 0x6600) || in si_init_microcode()
1736 (rdev->pdev->device == 0x6604) || in si_init_microcode()
1737 (rdev->pdev->device == 0x6605) || in si_init_microcode()
1738 (rdev->pdev->device == 0x6610))) || in si_init_microcode()
1739 ((rdev->pdev->revision == 0x83) && in si_init_microcode()
1740 (rdev->pdev->device == 0x6610))) in si_init_microcode()
1752 if (((rdev->pdev->revision == 0x81) && in si_init_microcode()
1753 (rdev->pdev->device == 0x6660)) || in si_init_microcode()
1754 ((rdev->pdev->revision == 0x83) && in si_init_microcode()
1755 ((rdev->pdev->device == 0x6660) || in si_init_microcode()
1756 (rdev->pdev->device == 0x6663) || in si_init_microcode()
1757 (rdev->pdev->device == 0x6665) || in si_init_microcode()
1758 (rdev->pdev->device == 0x6667)))) in si_init_microcode()
1760 else if ((rdev->pdev->revision == 0xc3) && in si_init_microcode()
1761 (rdev->pdev->device == 0x6665)) in si_init_microcode()
1775 if (((RREG32(MC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58) in si_init_microcode()
1781 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev); in si_init_microcode()
1784 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev); in si_init_microcode()
1787 if (rdev->pfp_fw->size != pfp_req_size) { in si_init_microcode()
1789 rdev->pfp_fw->size, fw_name); in si_init_microcode()
1790 err = -EINVAL; in si_init_microcode()
1794 err = radeon_ucode_validate(rdev->pfp_fw); in si_init_microcode()
1805 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); in si_init_microcode()
1808 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); in si_init_microcode()
1811 if (rdev->me_fw->size != me_req_size) { in si_init_microcode()
1813 rdev->me_fw->size, fw_name); in si_init_microcode()
1814 err = -EINVAL; in si_init_microcode()
1817 err = radeon_ucode_validate(rdev->me_fw); in si_init_microcode()
1828 err = request_firmware(&rdev->ce_fw, fw_name, rdev->dev); in si_init_microcode()
1831 err = request_firmware(&rdev->ce_fw, fw_name, rdev->dev); in si_init_microcode()
1834 if (rdev->ce_fw->size != ce_req_size) { in si_init_microcode()
1836 rdev->ce_fw->size, fw_name); in si_init_microcode()
1837 err = -EINVAL; in si_init_microcode()
1840 err = radeon_ucode_validate(rdev->ce_fw); in si_init_microcode()
1851 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev); in si_init_microcode()
1854 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev); in si_init_microcode()
1857 if (rdev->rlc_fw->size != rlc_req_size) { in si_init_microcode()
1859 rdev->rlc_fw->size, fw_name); in si_init_microcode()
1860 err = -EINVAL; in si_init_microcode()
1863 err = radeon_ucode_validate(rdev->rlc_fw); in si_init_microcode()
1877 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev); in si_init_microcode()
1880 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev); in si_init_microcode()
1883 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev); in si_init_microcode()
1887 if ((rdev->mc_fw->size != mc_req_size) && in si_init_microcode()
1888 (rdev->mc_fw->size != mc2_req_size)) { in si_init_microcode()
1890 rdev->mc_fw->size, fw_name); in si_init_microcode()
1891 err = -EINVAL; in si_init_microcode()
1893 DRM_INFO("%s: %zu bytes\n", fw_name, rdev->mc_fw->size); in si_init_microcode()
1895 err = radeon_ucode_validate(rdev->mc_fw); in si_init_microcode()
1911 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev); in si_init_microcode()
1914 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev); in si_init_microcode()
1917 release_firmware(rdev->smc_fw); in si_init_microcode()
1918 rdev->smc_fw = NULL; in si_init_microcode()
1919 err = 0; in si_init_microcode()
1920 } else if (rdev->smc_fw->size != smc_req_size) { in si_init_microcode()
1922 rdev->smc_fw->size, fw_name); in si_init_microcode()
1923 err = -EINVAL; in si_init_microcode()
1926 err = radeon_ucode_validate(rdev->smc_fw); in si_init_microcode()
1936 if (new_fw == 0) { in si_init_microcode()
1937 rdev->new_fw = false; in si_init_microcode()
1940 err = -EINVAL; in si_init_microcode()
1942 rdev->new_fw = true; in si_init_microcode()
1946 if (err != -EINVAL) in si_init_microcode()
1949 release_firmware(rdev->pfp_fw); in si_init_microcode()
1950 rdev->pfp_fw = NULL; in si_init_microcode()
1951 release_firmware(rdev->me_fw); in si_init_microcode()
1952 rdev->me_fw = NULL; in si_init_microcode()
1953 release_firmware(rdev->ce_fw); in si_init_microcode()
1954 rdev->ce_fw = NULL; in si_init_microcode()
1955 release_firmware(rdev->rlc_fw); in si_init_microcode()
1956 rdev->rlc_fw = NULL; in si_init_microcode()
1957 release_firmware(rdev->mc_fw); in si_init_microcode()
1958 rdev->mc_fw = NULL; in si_init_microcode()
1959 release_firmware(rdev->smc_fw); in si_init_microcode()
1960 rdev->smc_fw = NULL; in si_init_microcode()
1972 u32 pipe_offset = radeon_crtc->crtc_id * 0x20; in dce6_line_buffer_adjust()
1979 * 0 - half lb in dce6_line_buffer_adjust()
1980 * 2 - whole lb, other crtc must be disabled in dce6_line_buffer_adjust()
1984 * non-linked crtcs for maximum line buffer allocation. in dce6_line_buffer_adjust()
1986 if (radeon_crtc->base.enabled && mode) { in dce6_line_buffer_adjust()
1988 tmp = 0; /* 1/2 */ in dce6_line_buffer_adjust()
1995 tmp = 0; in dce6_line_buffer_adjust()
1996 buffer_alloc = 0; in dce6_line_buffer_adjust()
1999 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, in dce6_line_buffer_adjust()
2004 for (i = 0; i < rdev->usec_timeout; i++) { in dce6_line_buffer_adjust()
2011 if (radeon_crtc->base.enabled && mode) { in dce6_line_buffer_adjust()
2013 case 0: in dce6_line_buffer_adjust()
2022 return 0; in dce6_line_buffer_adjust()
2030 case 0: in si_get_number_of_dram_channels()
2076 yclk.full = dfixed_const(wm->yclk); in dce6_dram_bandwidth()
2078 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce6_dram_bandwidth()
2096 yclk.full = dfixed_const(wm->yclk); in dce6_dram_bandwidth_for_display()
2098 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce6_dram_bandwidth_for_display()
2116 sclk.full = dfixed_const(wm->sclk); in dce6_data_return_bandwidth()
2142 disp_clk.full = dfixed_const(wm->disp_clk); in dce6_dmif_request_bandwidth()
2148 sclk.full = dfixed_const(wm->sclk); in dce6_dmif_request_bandwidth()
2188 line_time.full = dfixed_const(wm->active_time + wm->blank_time); in dce6_average_bandwidth()
2190 bpp.full = dfixed_const(wm->bytes_per_pixel); in dce6_average_bandwidth()
2191 src_width.full = dfixed_const(wm->src_width); in dce6_average_bandwidth()
2193 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); in dce6_average_bandwidth()
2206 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ in dce6_latency_watermark()
2207 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + in dce6_latency_watermark()
2208 (wm->num_heads * cursor_line_pair_return_time); in dce6_latency_watermark()
2214 if (wm->num_heads == 0) in dce6_latency_watermark()
2215 return 0; in dce6_latency_watermark()
2219 if ((wm->vsc.full > a.full) || in dce6_latency_watermark()
2220 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || in dce6_latency_watermark()
2221 (wm->vtaps >= 5) || in dce6_latency_watermark()
2222 ((wm->vsc.full >= a.full) && wm->interlaced)) in dce6_latency_watermark()
2228 b.full = dfixed_const(wm->num_heads); in dce6_latency_watermark()
2230 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); in dce6_latency_watermark()
2233 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); in dce6_latency_watermark()
2235 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); in dce6_latency_watermark()
2242 if (line_fill_time < wm->active_time) in dce6_latency_watermark()
2245 return latency + (line_fill_time - wm->active_time); in dce6_latency_watermark()
2252 (dce6_dram_bandwidth_for_display(wm) / wm->num_heads)) in dce6_average_bandwidth_vs_dram_bandwidth_for_display()
2261 (dce6_available_bandwidth(wm) / wm->num_heads)) in dce6_average_bandwidth_vs_available_bandwidth()
2269 u32 lb_partitions = wm->lb_size / wm->src_width; in dce6_check_latency_hiding()
2270 u32 line_time = wm->active_time + wm->blank_time; in dce6_check_latency_hiding()
2276 if (wm->vsc.full > a.full) in dce6_check_latency_hiding()
2279 if (lb_partitions <= (wm->vtaps + 1)) in dce6_check_latency_hiding()
2285 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); in dce6_check_latency_hiding()
2297 struct drm_display_mode *mode = &radeon_crtc->base.mode; in dce6_program_watermarks()
2301 u32 line_time = 0; in dce6_program_watermarks()
2302 u32 latency_watermark_a = 0, latency_watermark_b = 0; in dce6_program_watermarks()
2303 u32 priority_a_mark = 0, priority_b_mark = 0; in dce6_program_watermarks()
2309 if (radeon_crtc->base.enabled && num_heads && mode) { in dce6_program_watermarks()
2310 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000, in dce6_program_watermarks()
2311 (u32)mode->clock); in dce6_program_watermarks()
2312 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000, in dce6_program_watermarks()
2313 (u32)mode->clock); in dce6_program_watermarks()
2315 priority_a_cnt = 0; in dce6_program_watermarks()
2316 priority_b_cnt = 0; in dce6_program_watermarks()
2318 if (rdev->family == CHIP_ARUBA) in dce6_program_watermarks()
2324 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { in dce6_program_watermarks()
2330 wm_high.yclk = rdev->pm.current_mclk * 10; in dce6_program_watermarks()
2331 wm_high.sclk = rdev->pm.current_sclk * 10; in dce6_program_watermarks()
2334 wm_high.disp_clk = mode->clock; in dce6_program_watermarks()
2335 wm_high.src_width = mode->crtc_hdisplay; in dce6_program_watermarks()
2337 wm_high.blank_time = line_time - wm_high.active_time; in dce6_program_watermarks()
2339 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce6_program_watermarks()
2341 wm_high.vsc = radeon_crtc->vsc; in dce6_program_watermarks()
2343 if (radeon_crtc->rmx_type != RMX_OFF) in dce6_program_watermarks()
2351 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { in dce6_program_watermarks()
2357 wm_low.yclk = rdev->pm.current_mclk * 10; in dce6_program_watermarks()
2358 wm_low.sclk = rdev->pm.current_sclk * 10; in dce6_program_watermarks()
2361 wm_low.disp_clk = mode->clock; in dce6_program_watermarks()
2362 wm_low.src_width = mode->crtc_hdisplay; in dce6_program_watermarks()
2364 wm_low.blank_time = line_time - wm_low.active_time; in dce6_program_watermarks()
2366 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce6_program_watermarks()
2368 wm_low.vsc = radeon_crtc->vsc; in dce6_program_watermarks()
2370 if (radeon_crtc->rmx_type != RMX_OFF) in dce6_program_watermarks()
2387 (rdev->disp_priority == 2)) { in dce6_program_watermarks()
2395 (rdev->disp_priority == 2)) { in dce6_program_watermarks()
2402 b.full = dfixed_const(mode->clock); in dce6_program_watermarks()
2406 c.full = dfixed_mul(c, radeon_crtc->hsc); in dce6_program_watermarks()
2414 b.full = dfixed_const(mode->clock); in dce6_program_watermarks()
2418 c.full = dfixed_mul(c, radeon_crtc->hsc); in dce6_program_watermarks()
2426 radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); in dce6_program_watermarks()
2430 arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset); in dce6_program_watermarks()
2434 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp); in dce6_program_watermarks()
2435 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, in dce6_program_watermarks()
2439 tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset); in dce6_program_watermarks()
2442 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp); in dce6_program_watermarks()
2443 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, in dce6_program_watermarks()
2447 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3); in dce6_program_watermarks()
2450 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt); in dce6_program_watermarks()
2451 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt); in dce6_program_watermarks()
2454 radeon_crtc->line_time = line_time; in dce6_program_watermarks()
2455 radeon_crtc->wm_high = latency_watermark_a; in dce6_program_watermarks()
2456 radeon_crtc->wm_low = latency_watermark_b; in dce6_program_watermarks()
2463 u32 num_heads = 0, lb_size; in dce6_bandwidth_update()
2466 if (!rdev->mode_info.mode_config_initialized) in dce6_bandwidth_update()
2471 for (i = 0; i < rdev->num_crtc; i++) { in dce6_bandwidth_update()
2472 if (rdev->mode_info.crtcs[i]->base.enabled) in dce6_bandwidth_update()
2475 for (i = 0; i < rdev->num_crtc; i += 2) { in dce6_bandwidth_update()
2476 mode0 = &rdev->mode_info.crtcs[i]->base.mode; in dce6_bandwidth_update()
2477 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode; in dce6_bandwidth_update()
2478 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1); in dce6_bandwidth_update()
2479 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads); in dce6_bandwidth_update()
2480 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0); in dce6_bandwidth_update()
2481 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads); in dce6_bandwidth_update()
2490 u32 *tile = rdev->config.si.tile_mode_array; in si_tiling_mode_table_init()
2492 ARRAY_SIZE(rdev->config.si.tile_mode_array); in si_tiling_mode_table_init()
2495 switch (rdev->config.si.mem_row_size_in_kb) { in si_tiling_mode_table_init()
2508 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in si_tiling_mode_table_init()
2509 tile[reg_offset] = 0; in si_tiling_mode_table_init()
2511 switch(rdev->family) { in si_tiling_mode_table_init()
2514 /* non-AA compressed depth or any compressed stencil */ in si_tiling_mode_table_init()
2515 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2550 /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */ in si_tiling_mode_table_init()
2559 /* Uncompressed 16bpp depth - and stencil buffer allocated with it */ in si_tiling_mode_table_init()
2568 /* Uncompressed 32bpp depth - and stencil buffer allocated with it */ in si_tiling_mode_table_init()
2722 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in si_tiling_mode_table_init()
2729 /* non-AA compressed depth or any compressed stencil */ in si_tiling_mode_table_init()
2730 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2765 /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */ in si_tiling_mode_table_init()
2774 /* Uncompressed 16bpp depth - and stencil buffer allocated with it */ in si_tiling_mode_table_init()
2783 /* Uncompressed 32bpp depth - and stencil buffer allocated with it */ in si_tiling_mode_table_init()
2937 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in si_tiling_mode_table_init()
2942 DRM_ERROR("unknown asic: 0x%x\n", rdev->family); in si_tiling_mode_table_init()
2951 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in si_select_se_sh()
2953 else if (se_num == 0xffffffff) in si_select_se_sh()
2955 else if (sh_num == 0xffffffff) in si_select_se_sh()
2964 u32 i, mask = 0; in si_create_bitmask()
2966 for (i = 0; i < bit_width; i++) { in si_create_bitmask()
2981 data = 0; in si_get_cu_enabled()
2998 for (i = 0; i < se_num; i++) { in si_setup_spi()
2999 for (j = 0; j < sh_per_se; j++) { in si_setup_spi()
3005 for (k = 0; k < 16; k++) { in si_setup_spi()
3015 si_select_se_sh(rdev, 0xffffffff, 0xffffffff); in si_setup_spi()
3028 data = 0; in si_get_rb_disabled()
3044 u32 disabled_rbs = 0; in si_setup_rb()
3045 u32 enabled_rbs = 0; in si_setup_rb()
3047 for (i = 0; i < se_num; i++) { in si_setup_rb()
3048 for (j = 0; j < sh_per_se; j++) { in si_setup_rb()
3054 si_select_se_sh(rdev, 0xffffffff, 0xffffffff); in si_setup_rb()
3057 for (i = 0; i < max_rb_num_per_se * se_num; i++) { in si_setup_rb()
3063 rdev->config.si.backend_enable_mask = enabled_rbs; in si_setup_rb()
3065 for (i = 0; i < se_num; i++) { in si_setup_rb()
3066 si_select_se_sh(rdev, i, 0xffffffff); in si_setup_rb()
3067 data = 0; in si_setup_rb()
3068 for (j = 0; j < sh_per_se; j++) { in si_setup_rb()
3085 si_select_se_sh(rdev, 0xffffffff, 0xffffffff); in si_setup_rb()
3090 u32 gb_addr_config = 0; in si_gpu_init()
3097 switch (rdev->family) { in si_gpu_init()
3099 rdev->config.si.max_shader_engines = 2; in si_gpu_init()
3100 rdev->config.si.max_tile_pipes = 12; in si_gpu_init()
3101 rdev->config.si.max_cu_per_sh = 8; in si_gpu_init()
3102 rdev->config.si.max_sh_per_se = 2; in si_gpu_init()
3103 rdev->config.si.max_backends_per_se = 4; in si_gpu_init()
3104 rdev->config.si.max_texture_channel_caches = 12; in si_gpu_init()
3105 rdev->config.si.max_gprs = 256; in si_gpu_init()
3106 rdev->config.si.max_gs_threads = 32; in si_gpu_init()
3107 rdev->config.si.max_hw_contexts = 8; in si_gpu_init()
3109 rdev->config.si.sc_prim_fifo_size_frontend = 0x20; in si_gpu_init()
3110 rdev->config.si.sc_prim_fifo_size_backend = 0x100; in si_gpu_init()
3111 rdev->config.si.sc_hiz_tile_fifo_size = 0x30; in si_gpu_init()
3112 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; in si_gpu_init()
3116 rdev->config.si.max_shader_engines = 2; in si_gpu_init()
3117 rdev->config.si.max_tile_pipes = 8; in si_gpu_init()
3118 rdev->config.si.max_cu_per_sh = 5; in si_gpu_init()
3119 rdev->config.si.max_sh_per_se = 2; in si_gpu_init()
3120 rdev->config.si.max_backends_per_se = 4; in si_gpu_init()
3121 rdev->config.si.max_texture_channel_caches = 8; in si_gpu_init()
3122 rdev->config.si.max_gprs = 256; in si_gpu_init()
3123 rdev->config.si.max_gs_threads = 32; in si_gpu_init()
3124 rdev->config.si.max_hw_contexts = 8; in si_gpu_init()
3126 rdev->config.si.sc_prim_fifo_size_frontend = 0x20; in si_gpu_init()
3127 rdev->config.si.sc_prim_fifo_size_backend = 0x100; in si_gpu_init()
3128 rdev->config.si.sc_hiz_tile_fifo_size = 0x30; in si_gpu_init()
3129 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; in si_gpu_init()
3134 rdev->config.si.max_shader_engines = 1; in si_gpu_init()
3135 rdev->config.si.max_tile_pipes = 4; in si_gpu_init()
3136 rdev->config.si.max_cu_per_sh = 5; in si_gpu_init()
3137 rdev->config.si.max_sh_per_se = 2; in si_gpu_init()
3138 rdev->config.si.max_backends_per_se = 4; in si_gpu_init()
3139 rdev->config.si.max_texture_channel_caches = 4; in si_gpu_init()
3140 rdev->config.si.max_gprs = 256; in si_gpu_init()
3141 rdev->config.si.max_gs_threads = 32; in si_gpu_init()
3142 rdev->config.si.max_hw_contexts = 8; in si_gpu_init()
3144 rdev->config.si.sc_prim_fifo_size_frontend = 0x20; in si_gpu_init()
3145 rdev->config.si.sc_prim_fifo_size_backend = 0x40; in si_gpu_init()
3146 rdev->config.si.sc_hiz_tile_fifo_size = 0x30; in si_gpu_init()
3147 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; in si_gpu_init()
3151 rdev->config.si.max_shader_engines = 1; in si_gpu_init()
3152 rdev->config.si.max_tile_pipes = 4; in si_gpu_init()
3153 rdev->config.si.max_cu_per_sh = 6; in si_gpu_init()
3154 rdev->config.si.max_sh_per_se = 1; in si_gpu_init()
3155 rdev->config.si.max_backends_per_se = 2; in si_gpu_init()
3156 rdev->config.si.max_texture_channel_caches = 4; in si_gpu_init()
3157 rdev->config.si.max_gprs = 256; in si_gpu_init()
3158 rdev->config.si.max_gs_threads = 16; in si_gpu_init()
3159 rdev->config.si.max_hw_contexts = 8; in si_gpu_init()
3161 rdev->config.si.sc_prim_fifo_size_frontend = 0x20; in si_gpu_init()
3162 rdev->config.si.sc_prim_fifo_size_backend = 0x40; in si_gpu_init()
3163 rdev->config.si.sc_hiz_tile_fifo_size = 0x30; in si_gpu_init()
3164 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; in si_gpu_init()
3168 rdev->config.si.max_shader_engines = 1; in si_gpu_init()
3169 rdev->config.si.max_tile_pipes = 4; in si_gpu_init()
3170 rdev->config.si.max_cu_per_sh = 5; in si_gpu_init()
3171 rdev->config.si.max_sh_per_se = 1; in si_gpu_init()
3172 rdev->config.si.max_backends_per_se = 1; in si_gpu_init()
3173 rdev->config.si.max_texture_channel_caches = 2; in si_gpu_init()
3174 rdev->config.si.max_gprs = 256; in si_gpu_init()
3175 rdev->config.si.max_gs_threads = 16; in si_gpu_init()
3176 rdev->config.si.max_hw_contexts = 8; in si_gpu_init()
3178 rdev->config.si.sc_prim_fifo_size_frontend = 0x20; in si_gpu_init()
3179 rdev->config.si.sc_prim_fifo_size_backend = 0x40; in si_gpu_init()
3180 rdev->config.si.sc_hiz_tile_fifo_size = 0x30; in si_gpu_init()
3181 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; in si_gpu_init()
3187 for (i = 0, j = 0; i < 32; i++, j += 0x18) { in si_gpu_init()
3188 WREG32((0x2c14 + j), 0x00000000); in si_gpu_init()
3189 WREG32((0x2c18 + j), 0x00000000); in si_gpu_init()
3190 WREG32((0x2c1c + j), 0x00000000); in si_gpu_init()
3191 WREG32((0x2c20 + j), 0x00000000); in si_gpu_init()
3192 WREG32((0x2c24 + j), 0x00000000); in si_gpu_init()
3195 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); in si_gpu_init()
3206 rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes; in si_gpu_init()
3207 rdev->config.si.mem_max_burst_length_bytes = 256; in si_gpu_init()
3209 rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; in si_gpu_init()
3210 if (rdev->config.si.mem_row_size_in_kb > 4) in si_gpu_init()
3211 rdev->config.si.mem_row_size_in_kb = 4; in si_gpu_init()
3213 rdev->config.si.shader_engine_tile_size = 32; in si_gpu_init()
3214 rdev->config.si.num_gpus = 1; in si_gpu_init()
3215 rdev->config.si.multi_gpu_tile_size = 64; in si_gpu_init()
3219 switch (rdev->config.si.mem_row_size_in_kb) { in si_gpu_init()
3222 gb_addr_config |= ROW_SIZE(0); in si_gpu_init()
3234 * bits 3:0 num_pipes in si_gpu_init()
3239 rdev->config.si.tile_config = 0; in si_gpu_init()
3240 switch (rdev->config.si.num_tile_pipes) { in si_gpu_init()
3242 rdev->config.si.tile_config |= (0 << 0); in si_gpu_init()
3245 rdev->config.si.tile_config |= (1 << 0); in si_gpu_init()
3248 rdev->config.si.tile_config |= (2 << 0); in si_gpu_init()
3253 rdev->config.si.tile_config |= (3 << 0); in si_gpu_init()
3257 case 0: /* four banks */ in si_gpu_init()
3258 rdev->config.si.tile_config |= 0 << 4; in si_gpu_init()
3261 rdev->config.si.tile_config |= 1 << 4; in si_gpu_init()
3265 rdev->config.si.tile_config |= 2 << 4; in si_gpu_init()
3268 rdev->config.si.tile_config |= in si_gpu_init()
3270 rdev->config.si.tile_config |= in si_gpu_init()
3279 if (rdev->has_uvd) { in si_gpu_init()
3287 si_setup_rb(rdev, rdev->config.si.max_shader_engines, in si_gpu_init()
3288 rdev->config.si.max_sh_per_se, in si_gpu_init()
3289 rdev->config.si.max_backends_per_se); in si_gpu_init()
3291 si_setup_spi(rdev, rdev->config.si.max_shader_engines, in si_gpu_init()
3292 rdev->config.si.max_sh_per_se, in si_gpu_init()
3293 rdev->config.si.max_cu_per_sh); in si_gpu_init()
3295 rdev->config.si.active_cus = 0; in si_gpu_init()
3296 for (i = 0; i < rdev->config.si.max_shader_engines; i++) { in si_gpu_init()
3297 for (j = 0; j < rdev->config.si.max_sh_per_se; j++) { in si_gpu_init()
3298 rdev->config.si.active_cus += in si_gpu_init()
3304 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | in si_gpu_init()
3305 ROQ_IB2_START(0x2b))); in si_gpu_init()
3306 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60)); in si_gpu_init()
3313 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_frontend) | in si_gpu_init()
3314 SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_backend) | in si_gpu_init()
3315 SC_HIZ_TILE_FIFO_SIZE(rdev->config.si.sc_hiz_tile_fifo_size) | in si_gpu_init()
3316 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.si.sc_earlyz_tile_fifo_size))); in si_gpu_init()
3320 WREG32(CP_PERFMON_CNTL, 0); in si_gpu_init()
3322 WREG32(SQ_CONFIG, 0); in si_gpu_init()
3331 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); in si_gpu_init()
3333 WREG32(CB_PERFCOUNTER0_SELECT0, 0); in si_gpu_init()
3334 WREG32(CB_PERFCOUNTER0_SELECT1, 0); in si_gpu_init()
3335 WREG32(CB_PERFCOUNTER1_SELECT0, 0); in si_gpu_init()
3336 WREG32(CB_PERFCOUNTER1_SELECT1, 0); in si_gpu_init()
3337 WREG32(CB_PERFCOUNTER2_SELECT0, 0); in si_gpu_init()
3338 WREG32(CB_PERFCOUNTER2_SELECT1, 0); in si_gpu_init()
3339 WREG32(CB_PERFCOUNTER3_SELECT0, 0); in si_gpu_init()
3340 WREG32(CB_PERFCOUNTER3_SELECT1, 0); in si_gpu_init()
3361 rdev->scratch.num_reg = 7; in si_scratch_init()
3362 rdev->scratch.reg_base = SCRATCH_REG0; in si_scratch_init()
3363 for (i = 0; i < rdev->scratch.num_reg; i++) { in si_scratch_init()
3364 rdev->scratch.free[i] = true; in si_scratch_init()
3365 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); in si_scratch_init()
3372 struct radeon_ring *ring = &rdev->ring[fence->ring]; in si_fence_ring_emit()
3373 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in si_fence_ring_emit()
3377 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2); in si_fence_ring_emit()
3378 radeon_ring_write(ring, 0); in si_fence_ring_emit()
3384 radeon_ring_write(ring, 0xFFFFFFFF); in si_fence_ring_emit()
3385 radeon_ring_write(ring, 0); in si_fence_ring_emit()
3387 /* EVENT_WRITE_EOP - flush caches, send int */ in si_fence_ring_emit()
3391 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); in si_fence_ring_emit()
3392 radeon_ring_write(ring, fence->seq); in si_fence_ring_emit()
3393 radeon_ring_write(ring, 0); in si_fence_ring_emit()
3401 struct radeon_ring *ring = &rdev->ring[ib->ring]; in si_ring_ib_execute()
3402 unsigned vm_id = ib->vm ? ib->vm->ids[ib->ring].id : 0; in si_ring_ib_execute()
3405 if (ib->is_const_ib) { in si_ring_ib_execute()
3407 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in si_ring_ib_execute()
3408 radeon_ring_write(ring, 0); in si_ring_ib_execute()
3413 if (ring->rptr_save_reg) { in si_ring_ib_execute()
3414 next_rptr = ring->wptr + 3 + 4 + 8; in si_ring_ib_execute()
3416 radeon_ring_write(ring, ((ring->rptr_save_reg - in si_ring_ib_execute()
3419 } else if (rdev->wb.enabled) { in si_ring_ib_execute()
3420 next_rptr = ring->wptr + 5 + 4 + 8; in si_ring_ib_execute()
3423 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); in si_ring_ib_execute()
3424 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); in si_ring_ib_execute()
3434 (2 << 0) | in si_ring_ib_execute()
3436 (ib->gpu_addr & 0xFFFFFFFC)); in si_ring_ib_execute()
3437 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); in si_ring_ib_execute()
3438 radeon_ring_write(ring, ib->length_dw | (vm_id << 24)); in si_ring_ib_execute()
3440 if (!ib->is_const_ib) { in si_ring_ib_execute()
3443 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2); in si_ring_ib_execute()
3450 radeon_ring_write(ring, 0xFFFFFFFF); in si_ring_ib_execute()
3451 radeon_ring_write(ring, 0); in si_ring_ib_execute()
3462 WREG32(CP_ME_CNTL, 0); in si_cp_enable()
3464 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) in si_cp_enable()
3465 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); in si_cp_enable()
3467 WREG32(SCRATCH_UMSK, 0); in si_cp_enable()
3468 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in si_cp_enable()
3469 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; in si_cp_enable()
3470 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; in si_cp_enable()
3479 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw) in si_cp_load_microcode()
3480 return -EINVAL; in si_cp_load_microcode()
3484 if (rdev->new_fw) { in si_cp_load_microcode()
3486 (const struct gfx_firmware_header_v1_0 *)rdev->pfp_fw->data; in si_cp_load_microcode()
3488 (const struct gfx_firmware_header_v1_0 *)rdev->ce_fw->data; in si_cp_load_microcode()
3490 (const struct gfx_firmware_header_v1_0 *)rdev->me_fw->data; in si_cp_load_microcode()
3494 radeon_ucode_print_gfx_hdr(&pfp_hdr->header); in si_cp_load_microcode()
3495 radeon_ucode_print_gfx_hdr(&ce_hdr->header); in si_cp_load_microcode()
3496 radeon_ucode_print_gfx_hdr(&me_hdr->header); in si_cp_load_microcode()
3500 (rdev->pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); in si_cp_load_microcode()
3501 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; in si_cp_load_microcode()
3502 WREG32(CP_PFP_UCODE_ADDR, 0); in si_cp_load_microcode()
3503 for (i = 0; i < fw_size; i++) in si_cp_load_microcode()
3505 WREG32(CP_PFP_UCODE_ADDR, 0); in si_cp_load_microcode()
3509 (rdev->ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); in si_cp_load_microcode()
3510 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; in si_cp_load_microcode()
3511 WREG32(CP_CE_UCODE_ADDR, 0); in si_cp_load_microcode()
3512 for (i = 0; i < fw_size; i++) in si_cp_load_microcode()
3514 WREG32(CP_CE_UCODE_ADDR, 0); in si_cp_load_microcode()
3518 (rdev->me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); in si_cp_load_microcode()
3519 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; in si_cp_load_microcode()
3520 WREG32(CP_ME_RAM_WADDR, 0); in si_cp_load_microcode()
3521 for (i = 0; i < fw_size; i++) in si_cp_load_microcode()
3523 WREG32(CP_ME_RAM_WADDR, 0); in si_cp_load_microcode()
3528 fw_data = (const __be32 *)rdev->pfp_fw->data; in si_cp_load_microcode()
3529 WREG32(CP_PFP_UCODE_ADDR, 0); in si_cp_load_microcode()
3530 for (i = 0; i < SI_PFP_UCODE_SIZE; i++) in si_cp_load_microcode()
3532 WREG32(CP_PFP_UCODE_ADDR, 0); in si_cp_load_microcode()
3535 fw_data = (const __be32 *)rdev->ce_fw->data; in si_cp_load_microcode()
3536 WREG32(CP_CE_UCODE_ADDR, 0); in si_cp_load_microcode()
3537 for (i = 0; i < SI_CE_UCODE_SIZE; i++) in si_cp_load_microcode()
3539 WREG32(CP_CE_UCODE_ADDR, 0); in si_cp_load_microcode()
3542 fw_data = (const __be32 *)rdev->me_fw->data; in si_cp_load_microcode()
3543 WREG32(CP_ME_RAM_WADDR, 0); in si_cp_load_microcode()
3544 for (i = 0; i < SI_PM4_UCODE_SIZE; i++) in si_cp_load_microcode()
3546 WREG32(CP_ME_RAM_WADDR, 0); in si_cp_load_microcode()
3549 WREG32(CP_PFP_UCODE_ADDR, 0); in si_cp_load_microcode()
3550 WREG32(CP_CE_UCODE_ADDR, 0); in si_cp_load_microcode()
3551 WREG32(CP_ME_RAM_WADDR, 0); in si_cp_load_microcode()
3552 WREG32(CP_ME_RAM_RADDR, 0); in si_cp_load_microcode()
3553 return 0; in si_cp_load_microcode()
3558 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in si_cp_start()
3568 radeon_ring_write(ring, 0x1); in si_cp_start()
3569 radeon_ring_write(ring, 0x0); in si_cp_start()
3570 radeon_ring_write(ring, rdev->config.si.max_hw_contexts - 1); in si_cp_start()
3572 radeon_ring_write(ring, 0); in si_cp_start()
3573 radeon_ring_write(ring, 0); in si_cp_start()
3578 radeon_ring_write(ring, 0xc000); in si_cp_start()
3579 radeon_ring_write(ring, 0xe000); in si_cp_start()
3591 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in si_cp_start()
3594 for (i = 0; i < si_default_size; i++) in si_cp_start()
3597 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in si_cp_start()
3601 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in si_cp_start()
3602 radeon_ring_write(ring, 0); in si_cp_start()
3605 radeon_ring_write(ring, 0x00000316); in si_cp_start()
3606 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ in si_cp_start()
3607 radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */ in si_cp_start()
3612 ring = &rdev->ring[i]; in si_cp_start()
3616 radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0)); in si_cp_start()
3617 radeon_ring_write(ring, 0); in si_cp_start()
3622 return 0; in si_cp_start()
3630 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in si_cp_fini()
3632 radeon_scratch_free(rdev, ring->rptr_save_reg); in si_cp_fini()
3634 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; in si_cp_fini()
3636 radeon_scratch_free(rdev, ring->rptr_save_reg); in si_cp_fini()
3638 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; in si_cp_fini()
3640 radeon_scratch_free(rdev, ring->rptr_save_reg); in si_cp_fini()
3652 WREG32(CP_SEM_WAIT_TIMER, 0x0); in si_cp_resume()
3653 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); in si_cp_resume()
3656 WREG32(CP_RB_WPTR_DELAY, 0); in si_cp_resume()
3658 WREG32(CP_DEBUG, 0); in si_cp_resume()
3659 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); in si_cp_resume()
3661 /* ring 0 - compute and gfx */ in si_cp_resume()
3663 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in si_cp_resume()
3664 rb_bufsz = order_base_2(ring->ring_size / 8); in si_cp_resume()
3673 ring->wptr = 0; in si_cp_resume()
3674 WREG32(CP_RB0_WPTR, ring->wptr); in si_cp_resume()
3677 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); in si_cp_resume()
3678 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); in si_cp_resume()
3680 if (rdev->wb.enabled) in si_cp_resume()
3681 WREG32(SCRATCH_UMSK, 0xff); in si_cp_resume()
3684 WREG32(SCRATCH_UMSK, 0); in si_cp_resume()
3690 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8); in si_cp_resume()
3692 /* ring1 - compute only */ in si_cp_resume()
3694 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; in si_cp_resume()
3695 rb_bufsz = order_base_2(ring->ring_size / 8); in si_cp_resume()
3704 ring->wptr = 0; in si_cp_resume()
3705 WREG32(CP_RB1_WPTR, ring->wptr); in si_cp_resume()
3708 WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC); in si_cp_resume()
3709 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF); in si_cp_resume()
3714 WREG32(CP_RB1_BASE, ring->gpu_addr >> 8); in si_cp_resume()
3716 /* ring2 - compute only */ in si_cp_resume()
3718 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; in si_cp_resume()
3719 rb_bufsz = order_base_2(ring->ring_size / 8); in si_cp_resume()
3728 ring->wptr = 0; in si_cp_resume()
3729 WREG32(CP_RB2_WPTR, ring->wptr); in si_cp_resume()
3732 WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC); in si_cp_resume()
3733 WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF); in si_cp_resume()
3738 WREG32(CP_RB2_BASE, ring->gpu_addr >> 8); in si_cp_resume()
3742 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true; in si_cp_resume()
3743 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = true; in si_cp_resume()
3744 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = true; in si_cp_resume()
3745 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); in si_cp_resume()
3747 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in si_cp_resume()
3748 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; in si_cp_resume()
3749 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; in si_cp_resume()
3752 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP1_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]); in si_cp_resume()
3754 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; in si_cp_resume()
3756 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP2_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]); in si_cp_resume()
3758 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; in si_cp_resume()
3763 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) in si_cp_resume()
3764 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); in si_cp_resume()
3766 return 0; in si_cp_resume()
3771 u32 reset_mask = 0; in si_gpu_check_soft_reset()
3796 /* DMA_STATUS_REG 0 */ in si_gpu_check_soft_reset()
3843 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask); in si_gpu_check_soft_reset()
3853 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; in si_gpu_soft_reset()
3856 if (reset_mask == 0) in si_gpu_soft_reset()
3859 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); in si_gpu_soft_reset()
3862 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", in si_gpu_soft_reset()
3864 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", in si_gpu_soft_reset()
3894 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in si_gpu_soft_reset()
3948 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); in si_gpu_soft_reset()
3962 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in si_gpu_soft_reset()
3994 for (i = 0; i < rdev->usec_timeout; i++) { in si_set_clk_bypass_mode()
4035 dev_info(rdev->dev, "GPU pci config reset\n"); in si_gpu_pci_config_reset()
4063 dev_warn(rdev->dev, "Wait for MC idle timed out !\n"); in si_gpu_pci_config_reset()
4071 pci_clear_master(rdev->pdev); in si_gpu_pci_config_reset()
4075 for (i = 0; i < rdev->usec_timeout; i++) { in si_gpu_pci_config_reset()
4076 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff) in si_gpu_pci_config_reset()
4088 return 0; in si_asic_reset()
4110 return 0; in si_asic_reset()
4114 * si_gfx_is_lockup - Check if the GFX engine is locked up
4143 for (i = 0, j = 0; i < 32; i++, j += 0x18) { in si_mc_program()
4144 WREG32((0x2c14 + j), 0x00000000); in si_mc_program()
4145 WREG32((0x2c18 + j), 0x00000000); in si_mc_program()
4146 WREG32((0x2c1c + j), 0x00000000); in si_mc_program()
4147 WREG32((0x2c20 + j), 0x00000000); in si_mc_program()
4148 WREG32((0x2c24 + j), 0x00000000); in si_mc_program()
4150 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); in si_mc_program()
4154 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in si_mc_program()
4161 rdev->mc.vram_start >> 12); in si_mc_program()
4163 rdev->mc.vram_end >> 12); in si_mc_program()
4165 rdev->vram_scratch.gpu_addr >> 12); in si_mc_program()
4166 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; in si_mc_program()
4167 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); in si_mc_program()
4170 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); in si_mc_program()
4172 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); in si_mc_program()
4173 WREG32(MC_VM_AGP_BASE, 0); in si_mc_program()
4174 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); in si_mc_program()
4175 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); in si_mc_program()
4177 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in si_mc_program()
4190 if (mc->mc_vram_size > 0xFFC0000000ULL) { in si_vram_gtt_location()
4192 dev_warn(rdev->dev, "limiting VRAM\n"); in si_vram_gtt_location()
4193 mc->real_vram_size = 0xFFC0000000ULL; in si_vram_gtt_location()
4194 mc->mc_vram_size = 0xFFC0000000ULL; in si_vram_gtt_location()
4196 radeon_vram_location(rdev, &rdev->mc, 0); in si_vram_gtt_location()
4197 rdev->mc.gtt_base_align = 0; in si_vram_gtt_location()
4207 rdev->mc.vram_is_ddr = true; in si_mc_init()
4218 case 0: in si_mc_init()
4247 rdev->mc.vram_width = numchan * chansize; in si_mc_init()
4248 /* Could aper size report 0 ? */ in si_mc_init()
4249 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); in si_mc_init()
4250 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); in si_mc_init()
4254 if (tmp & 0xffff0000) { in si_mc_init()
4255 DRM_INFO("Probable bad vram size: 0x%08x\n", tmp); in si_mc_init()
4256 if (tmp & 0xffff) in si_mc_init()
4257 tmp &= 0xffff; in si_mc_init()
4259 rdev->mc.mc_vram_size = tmp * 1024ULL * 1024ULL; in si_mc_init()
4260 rdev->mc.real_vram_size = rdev->mc.mc_vram_size; in si_mc_init()
4261 rdev->mc.visible_vram_size = rdev->mc.aper_size; in si_mc_init()
4262 si_vram_gtt_location(rdev, &rdev->mc); in si_mc_init()
4265 return 0; in si_mc_init()
4274 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); in si_pcie_gart_tlb_flush()
4276 /* bits 0-15 are the VM contexts0-15 */ in si_pcie_gart_tlb_flush()
4284 if (rdev->gart.robj == NULL) { in si_pcie_gart_enable()
4285 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); in si_pcie_gart_enable()
4286 return -EINVAL; in si_pcie_gart_enable()
4293 (0xA << 7) | in si_pcie_gart_enable()
4311 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); in si_pcie_gart_enable()
4312 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); in si_pcie_gart_enable()
4313 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in si_pcie_gart_enable()
4315 (u32)(rdev->dummy_page.addr >> 12)); in si_pcie_gart_enable()
4316 WREG32(VM_CONTEXT0_CNTL2, 0); in si_pcie_gart_enable()
4317 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in si_pcie_gart_enable()
4320 WREG32(0x15D4, 0); in si_pcie_gart_enable()
4321 WREG32(0x15D8, 0); in si_pcie_gart_enable()
4322 WREG32(0x15DC, 0); in si_pcie_gart_enable()
4324 /* empty context1-15 */ in si_pcie_gart_enable()
4326 WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); in si_pcie_gart_enable()
4327 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn - 1); in si_pcie_gart_enable()
4335 rdev->vm_manager.saved_table_addr[i]); in si_pcie_gart_enable()
4337 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2), in si_pcie_gart_enable()
4338 rdev->vm_manager.saved_table_addr[i]); in si_pcie_gart_enable()
4341 /* enable context1-15 */ in si_pcie_gart_enable()
4343 (u32)(rdev->dummy_page.addr >> 12)); in si_pcie_gart_enable()
4346 PAGE_TABLE_BLOCK_SIZE(radeon_vm_block_size - 9) | in si_pcie_gart_enable()
4361 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", in si_pcie_gart_enable()
4362 (unsigned)(rdev->mc.gtt_size >> 20), in si_pcie_gart_enable()
4363 (unsigned long long)rdev->gart.table_addr); in si_pcie_gart_enable()
4364 rdev->gart.ready = true; in si_pcie_gart_enable()
4365 return 0; in si_pcie_gart_enable()
4377 reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2); in si_pcie_gart_disable()
4378 rdev->vm_manager.saved_table_addr[i] = RREG32(reg); in si_pcie_gart_disable()
4382 WREG32(VM_CONTEXT0_CNTL, 0); in si_pcie_gart_disable()
4383 WREG32(VM_CONTEXT1_CNTL, 0); in si_pcie_gart_disable()
4392 WREG32(VM_L2_CNTL2, 0); in si_pcie_gart_disable()
4394 L2_CACHE_BIGK_FRAGMENT_SIZE(0)); in si_pcie_gart_disable()
4409 if (reg >= 0x28000) in si_vm_reg_valid()
4413 if (reg >= 0xB000 && reg < 0xC000) in si_vm_reg_valid()
4447 DRM_ERROR("Invalid register 0x%x in CS\n", reg); in si_vm_reg_valid()
4455 switch (pkt->opcode) { in si_vm_packet3_ce_check()
4468 DRM_ERROR("Invalid CE packet3: 0x%x\n", pkt->opcode); in si_vm_packet3_ce_check()
4469 return -EINVAL; in si_vm_packet3_ce_check()
4471 return 0; in si_vm_packet3_ce_check()
4482 if (((info & 0x60000000) >> 29) == 0) { in si_vm_packet3_cp_dma_check()
4488 return -EINVAL; in si_vm_packet3_cp_dma_check()
4491 for (i = 0; i < (command & 0x1fffff); i++) { in si_vm_packet3_cp_dma_check()
4495 return -EINVAL; in si_vm_packet3_cp_dma_check()
4503 if (((info & 0x00300000) >> 20) == 0) { in si_vm_packet3_cp_dma_check()
4509 return -EINVAL; in si_vm_packet3_cp_dma_check()
4512 for (i = 0; i < (command & 0x1fffff); i++) { in si_vm_packet3_cp_dma_check()
4516 return -EINVAL; in si_vm_packet3_cp_dma_check()
4522 return 0; in si_vm_packet3_cp_dma_check()
4529 u32 idx = pkt->idx + 1; in si_vm_packet3_gfx_check()
4533 switch (pkt->opcode) { in si_vm_packet3_gfx_check()
4581 if ((idx_value & 0xf00) == 0) { in si_vm_packet3_gfx_check()
4584 return -EINVAL; in si_vm_packet3_gfx_check()
4588 if ((idx_value & 0xf00) == 0) { in si_vm_packet3_gfx_check()
4590 if (idx_value & 0x10000) { in si_vm_packet3_gfx_check()
4592 return -EINVAL; in si_vm_packet3_gfx_check()
4594 for (i = 0; i < (pkt->count - 2); i++) { in si_vm_packet3_gfx_check()
4597 return -EINVAL; in si_vm_packet3_gfx_check()
4603 if (idx_value & 0x100) { in si_vm_packet3_gfx_check()
4606 return -EINVAL; in si_vm_packet3_gfx_check()
4610 if (idx_value & 0x2) { in si_vm_packet3_gfx_check()
4613 return -EINVAL; in si_vm_packet3_gfx_check()
4618 end_reg = 4 * pkt->count + start_reg - 4; in si_vm_packet3_gfx_check()
4623 return -EINVAL; in si_vm_packet3_gfx_check()
4625 for (i = 0; i < pkt->count; i++) { in si_vm_packet3_gfx_check()
4628 return -EINVAL; in si_vm_packet3_gfx_check()
4637 DRM_ERROR("Invalid GFX packet3: 0x%x\n", pkt->opcode); in si_vm_packet3_gfx_check()
4638 return -EINVAL; in si_vm_packet3_gfx_check()
4640 return 0; in si_vm_packet3_gfx_check()
4647 u32 idx = pkt->idx + 1; in si_vm_packet3_compute_check()
4651 switch (pkt->opcode) { in si_vm_packet3_compute_check()
4684 if ((idx_value & 0xf00) == 0) { in si_vm_packet3_compute_check()
4687 return -EINVAL; in si_vm_packet3_compute_check()
4691 if ((idx_value & 0xf00) == 0) { in si_vm_packet3_compute_check()
4693 if (idx_value & 0x10000) { in si_vm_packet3_compute_check()
4695 return -EINVAL; in si_vm_packet3_compute_check()
4697 for (i = 0; i < (pkt->count - 2); i++) { in si_vm_packet3_compute_check()
4700 return -EINVAL; in si_vm_packet3_compute_check()
4706 if (idx_value & 0x100) { in si_vm_packet3_compute_check()
4709 return -EINVAL; in si_vm_packet3_compute_check()
4713 if (idx_value & 0x2) { in si_vm_packet3_compute_check()
4716 return -EINVAL; in si_vm_packet3_compute_check()
4725 DRM_ERROR("Invalid Compute packet3: 0x%x\n", pkt->opcode); in si_vm_packet3_compute_check()
4726 return -EINVAL; in si_vm_packet3_compute_check()
4728 return 0; in si_vm_packet3_compute_check()
4733 int ret = 0; in si_ib_parse()
4734 u32 idx = 0, i; in si_ib_parse()
4739 pkt.type = RADEON_CP_PACKET_GET_TYPE(ib->ptr[idx]); in si_ib_parse()
4740 pkt.count = RADEON_CP_PACKET_GET_COUNT(ib->ptr[idx]); in si_ib_parse()
4741 pkt.one_reg_wr = 0; in si_ib_parse()
4744 dev_err(rdev->dev, "Packet0 not allowed!\n"); in si_ib_parse()
4745 ret = -EINVAL; in si_ib_parse()
4751 pkt.opcode = RADEON_CP_PACKET3_GET_OPCODE(ib->ptr[idx]); in si_ib_parse()
4752 if (ib->is_const_ib) in si_ib_parse()
4753 ret = si_vm_packet3_ce_check(rdev, ib->ptr, &pkt); in si_ib_parse()
4755 switch (ib->ring) { in si_ib_parse()
4757 ret = si_vm_packet3_gfx_check(rdev, ib->ptr, &pkt); in si_ib_parse()
4761 ret = si_vm_packet3_compute_check(rdev, ib->ptr, &pkt); in si_ib_parse()
4764 dev_err(rdev->dev, "Non-PM4 ring %d !\n", ib->ring); in si_ib_parse()
4765 ret = -EINVAL; in si_ib_parse()
4772 dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type); in si_ib_parse()
4773 ret = -EINVAL; in si_ib_parse()
4777 for (i = 0; i < ib->length_dw; i++) { in si_ib_parse()
4779 printk("\t0x%08x <---\n", ib->ptr[i]); in si_ib_parse()
4781 printk("\t0x%08x\n", ib->ptr[i]); in si_ib_parse()
4785 } while (idx < ib->length_dw); in si_ib_parse()
4796 rdev->vm_manager.nvm = 16; in si_vm_init()
4798 rdev->vm_manager.vram_base_offset = 0; in si_vm_init()
4800 return 0; in si_vm_init()
4808 * si_vm_decode_fault - print human readable fault info
4824 if (rdev->family == CHIP_TAHITI) { in si_vm_decode_fault()
4901 case 0: in si_vm_decode_fault()
5065 printk("VM fault (0x%02x, vmid %d) at page %u, %s from %s (%d)\n", in si_vm_decode_fault()
5077 WRITE_DATA_DST_SEL(0))); in si_vm_flush()
5084 (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm_id - 8) << 2)) >> 2); in si_vm_flush()
5086 radeon_ring_write(ring, 0); in si_vm_flush()
5092 WRITE_DATA_DST_SEL(0))); in si_vm_flush()
5094 radeon_ring_write(ring, 0); in si_vm_flush()
5095 radeon_ring_write(ring, 0x1); in si_vm_flush()
5097 /* bits 0-15 are the VM contexts0-15 */ in si_vm_flush()
5100 WRITE_DATA_DST_SEL(0))); in si_vm_flush()
5102 radeon_ring_write(ring, 0); in si_vm_flush()
5107 radeon_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */ in si_vm_flush()
5108 WAIT_REG_MEM_ENGINE(0))); /* me */ in si_vm_flush()
5110 radeon_ring_write(ring, 0); in si_vm_flush()
5111 radeon_ring_write(ring, 0); /* ref */ in si_vm_flush()
5112 radeon_ring_write(ring, 0); /* mask */ in si_vm_flush()
5113 radeon_ring_write(ring, 0x20); /* poll interval */ in si_vm_flush()
5116 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in si_vm_flush()
5117 radeon_ring_write(ring, 0x0); in si_vm_flush()
5127 for (i = 0; i < rdev->usec_timeout; i++) { in si_wait_for_rlc_serdes()
5128 if (RREG32(RLC_SERDES_MASTER_BUSY_0) == 0) in si_wait_for_rlc_serdes()
5133 for (i = 0; i < rdev->usec_timeout; i++) { in si_wait_for_rlc_serdes()
5134 if (RREG32(RLC_SERDES_MASTER_BUSY_1) == 0) in si_wait_for_rlc_serdes()
5158 for (i = 0; i < rdev->usec_timeout; i++) { in si_enable_gui_idle_interrupt()
5176 tmp &= ~0x7ffff800; in si_set_uvd_dcm()
5179 tmp |= 0x7ffff800; in si_set_uvd_dcm()
5180 tmp2 = 0; in si_set_uvd_dcm()
5230 if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_SDMA)) in si_enable_dma_pg()
5242 WREG32(DMA_PGFSM_WRITE, 0x00002000); in si_init_dma_pg()
5243 WREG32(DMA_PGFSM_CONFIG, 0x100010ff); in si_init_dma_pg()
5245 for (tmp = 0; tmp < 5; tmp++) in si_init_dma_pg()
5246 WREG32(DMA_PGFSM_WRITE, 0); in si_init_dma_pg()
5254 if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG)) { in si_enable_gfx_cgpg()
5255 tmp = RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10); in si_enable_gfx_cgpg()
5278 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in si_init_gfx_cgpg()
5284 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_gfx_cgpg()
5289 tmp |= GRBM_REG_SGIT(0x700); in si_init_gfx_cgpg()
5296 u32 mask = 0, tmp, tmp1; in si_get_cu_active_bitmap()
5302 si_select_se_sh(rdev, 0xffffffff, 0xffffffff); in si_get_cu_active_bitmap()
5304 tmp &= 0xffff0000; in si_get_cu_active_bitmap()
5309 for (i = 0; i < rdev->config.si.max_cu_per_sh; i ++) { in si_get_cu_active_bitmap()
5319 u32 i, j, k, active_cu_number = 0; in si_init_ao_cu_mask()
5321 u32 tmp = 0; in si_init_ao_cu_mask()
5323 for (i = 0; i < rdev->config.si.max_shader_engines; i++) { in si_init_ao_cu_mask()
5324 for (j = 0; j < rdev->config.si.max_sh_per_se; j++) { in si_init_ao_cu_mask()
5326 cu_bitmap = 0; in si_init_ao_cu_mask()
5327 counter = 0; in si_init_ao_cu_mask()
5328 for (k = 0; k < rdev->config.si.max_cu_per_sh; k++) { in si_init_ao_cu_mask()
5357 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CGCG)) { in si_enable_cgcg()
5360 WREG32(RLC_GCPM_GENERAL_3, 0x00000080); in si_enable_cgcg()
5364 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); in si_enable_cgcg()
5365 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); in si_enable_cgcg()
5366 WREG32(RLC_SERDES_WR_CTRL, 0x00b000ff); in si_enable_cgcg()
5372 WREG32(RLC_SERDES_WR_CTRL, 0x007000ff); in si_enable_cgcg()
5393 u32 data, orig, tmp = 0; in si_enable_mgcg()
5395 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_MGCG)) { in si_enable_mgcg()
5397 data = 0x96940200; in si_enable_mgcg()
5401 if (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CP_LS) { in si_enable_mgcg()
5409 data &= 0xffffffc0; in si_enable_mgcg()
5415 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); in si_enable_mgcg()
5416 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); in si_enable_mgcg()
5417 WREG32(RLC_SERDES_WR_CTRL, 0x00d000ff); in si_enable_mgcg()
5422 data |= 0x00000003; in si_enable_mgcg()
5438 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); in si_enable_mgcg()
5439 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); in si_enable_mgcg()
5440 WREG32(RLC_SERDES_WR_CTRL, 0x00e000ff); in si_enable_mgcg()
5451 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_UVD_MGCG)) { in si_enable_uvd_mgcg()
5453 tmp |= 0x3fff; in si_enable_uvd_mgcg()
5461 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_0, 0); in si_enable_uvd_mgcg()
5462 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_1, 0); in si_enable_uvd_mgcg()
5465 tmp &= ~0x3fff; in si_enable_uvd_mgcg()
5473 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_0, 0xffffffff); in si_enable_uvd_mgcg()
5474 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_1, 0xffffffff); in si_enable_uvd_mgcg()
5497 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { in si_enable_mc_ls()
5499 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_MC_LS)) in si_enable_mc_ls()
5514 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { in si_enable_mc_mgcg()
5516 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_MC_MGCG)) in si_enable_mc_mgcg()
5531 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_SDMA_MGCG)) { in si_enable_dma_mgcg()
5532 for (i = 0; i < 2; i++) { in si_enable_dma_mgcg()
5533 if (i == 0) in si_enable_dma_mgcg()
5541 WREG32(DMA_CLK_CTRL + offset, 0x00000100); in si_enable_dma_mgcg()
5544 for (i = 0; i < 2; i++) { in si_enable_dma_mgcg()
5545 if (i == 0) in si_enable_dma_mgcg()
5555 data = 0xff000000; in si_enable_dma_mgcg()
5569 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_BIF_LS)) in si_enable_bif_mgls()
5587 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_HDP_MGCG)) in si_enable_hdp_mgcg()
5603 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_HDP_LS)) in si_enable_hdp_ls()
5642 if (rdev->has_uvd) { in si_update_cg()
5660 if (rdev->has_uvd) { in si_init_cg()
5668 if (rdev->has_uvd) { in si_fini_cg()
5680 u32 count = 0; in si_get_csb_size()
5684 if (rdev->rlc.cs_data == NULL) in si_get_csb_size()
5685 return 0; in si_get_csb_size()
5692 for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) { in si_get_csb_size()
5693 for (ext = sect->section; ext->extent != NULL; ++ext) { in si_get_csb_size()
5694 if (sect->id == SECT_CONTEXT) in si_get_csb_size()
5695 count += 2 + ext->reg_count; in si_get_csb_size()
5697 return 0; in si_get_csb_size()
5712 u32 count = 0, i; in si_get_csb_buffer()
5716 if (rdev->rlc.cs_data == NULL) in si_get_csb_buffer()
5721 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in si_get_csb_buffer()
5725 buffer[count++] = cpu_to_le32(0x80000000); in si_get_csb_buffer()
5726 buffer[count++] = cpu_to_le32(0x80000000); in si_get_csb_buffer()
5728 for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) { in si_get_csb_buffer()
5729 for (ext = sect->section; ext->extent != NULL; ++ext) { in si_get_csb_buffer()
5730 if (sect->id == SECT_CONTEXT) { in si_get_csb_buffer()
5732 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); in si_get_csb_buffer()
5733 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000); in si_get_csb_buffer()
5734 for (i = 0; i < ext->reg_count; i++) in si_get_csb_buffer()
5735 buffer[count++] = cpu_to_le32(ext->extent[i]); in si_get_csb_buffer()
5743 buffer[count++] = cpu_to_le32(PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); in si_get_csb_buffer()
5744 switch (rdev->family) { in si_get_csb_buffer()
5747 buffer[count++] = cpu_to_le32(0x2a00126a); in si_get_csb_buffer()
5750 buffer[count++] = cpu_to_le32(0x0000124a); in si_get_csb_buffer()
5753 buffer[count++] = cpu_to_le32(0x00000082); in si_get_csb_buffer()
5756 buffer[count++] = cpu_to_le32(0x00000000); in si_get_csb_buffer()
5759 buffer[count++] = cpu_to_le32(0x00000000); in si_get_csb_buffer()
5763 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in si_get_csb_buffer()
5766 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); in si_get_csb_buffer()
5767 buffer[count++] = cpu_to_le32(0); in si_get_csb_buffer()
5772 if (rdev->pg_flags) { in si_init_pg()
5773 if (rdev->pg_flags & RADEON_PG_SUPPORT_SDMA) { in si_init_pg()
5777 if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG) { in si_init_pg()
5780 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in si_init_pg()
5781 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_pg()
5786 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in si_init_pg()
5787 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_pg()
5793 if (rdev->pg_flags) { in si_fini_pg()
5816 WREG32(RLC_CNTL, 0); in si_rlc_stop()
5838 if ((tmp & 0xF0000000) == 0xB0000000) in si_lbpw_supported()
5855 si_select_se_sh(rdev, 0xffffffff, 0xffffffff); in si_enable_lbpw()
5856 WREG32(SPI_LB_CU_MASK, 0x00ff); in si_enable_lbpw()
5864 if (!rdev->rlc_fw) in si_rlc_resume()
5865 return -EINVAL; in si_rlc_resume()
5875 WREG32(RLC_RL_BASE, 0); in si_rlc_resume()
5876 WREG32(RLC_RL_SIZE, 0); in si_rlc_resume()
5877 WREG32(RLC_LB_CNTL, 0); in si_rlc_resume()
5878 WREG32(RLC_LB_CNTR_MAX, 0xffffffff); in si_rlc_resume()
5879 WREG32(RLC_LB_CNTR_INIT, 0); in si_rlc_resume()
5880 WREG32(RLC_LB_INIT_CU_MASK, 0xffffffff); in si_rlc_resume()
5882 WREG32(RLC_MC_CNTL, 0); in si_rlc_resume()
5883 WREG32(RLC_UCODE_CNTL, 0); in si_rlc_resume()
5885 if (rdev->new_fw) { in si_rlc_resume()
5887 (const struct rlc_firmware_header_v1_0 *)rdev->rlc_fw->data; in si_rlc_resume()
5888 u32 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; in si_rlc_resume()
5890 (rdev->rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); in si_rlc_resume()
5892 radeon_ucode_print_rlc_hdr(&hdr->header); in si_rlc_resume()
5894 for (i = 0; i < fw_size; i++) { in si_rlc_resume()
5900 (const __be32 *)rdev->rlc_fw->data; in si_rlc_resume()
5901 for (i = 0; i < SI_RLC_UCODE_SIZE; i++) { in si_rlc_resume()
5906 WREG32(RLC_UCODE_ADDR, 0); in si_rlc_resume()
5912 return 0; in si_rlc_resume()
5924 rdev->ih.enabled = true; in si_enable_interrupts()
5936 /* set rptr, wptr to 0 */ in si_disable_interrupts()
5937 WREG32(IH_RB_RPTR, 0); in si_disable_interrupts()
5938 WREG32(IH_RB_WPTR, 0); in si_disable_interrupts()
5939 rdev->ih.enabled = false; in si_disable_interrupts()
5940 rdev->ih.rptr = 0; in si_disable_interrupts()
5951 WREG32(CP_INT_CNTL_RING1, 0); in si_disable_interrupt_state()
5952 WREG32(CP_INT_CNTL_RING2, 0); in si_disable_interrupt_state()
5957 WREG32(GRBM_INT_CNTL, 0); in si_disable_interrupt_state()
5958 WREG32(SRBM_INT_CNTL, 0); in si_disable_interrupt_state()
5959 for (i = 0; i < rdev->num_crtc; i++) in si_disable_interrupt_state()
5960 WREG32(INT_MASK + crtc_offsets[i], 0); in si_disable_interrupt_state()
5961 for (i = 0; i < rdev->num_crtc; i++) in si_disable_interrupt_state()
5962 WREG32(GRPH_INT_CONTROL + crtc_offsets[i], 0); in si_disable_interrupt_state()
5965 WREG32(DAC_AUTODETECT_INT_CONTROL, 0); in si_disable_interrupt_state()
5967 for (i = 0; i < 6; i++) in si_disable_interrupt_state()
5975 int ret = 0; in si_irq_init()
5996 WREG32(INTERRUPT_CNTL2, rdev->dummy_page.addr >> 8); in si_irq_init()
5998 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi in si_irq_init()
5999 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN in si_irq_init()
6002 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */ in si_irq_init()
6006 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); in si_irq_init()
6007 rb_bufsz = order_base_2(rdev->ih.ring_size / 4); in si_irq_init()
6013 if (rdev->wb.enabled) in si_irq_init()
6017 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); in si_irq_init()
6018 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); in si_irq_init()
6022 /* set rptr, wptr to 0 */ in si_irq_init()
6023 WREG32(IH_RB_RPTR, 0); in si_irq_init()
6024 WREG32(IH_RB_WPTR, 0); in si_irq_init()
6027 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0); in si_irq_init()
6029 if (rdev->msi_enabled) in si_irq_init()
6036 pci_set_master(rdev->pdev); in si_irq_init()
6049 u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0; in si_irq_set()
6050 u32 grbm_int_cntl = 0; in si_irq_set()
6052 u32 thermal_int = 0; in si_irq_set()
6054 if (!rdev->irq.installed) { in si_irq_set()
6056 return -EINVAL; in si_irq_set()
6059 if (!rdev->ih.enabled) { in si_irq_set()
6063 return 0; in si_irq_set()
6076 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { in si_irq_set()
6080 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) { in si_irq_set()
6084 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) { in si_irq_set()
6088 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) { in si_irq_set()
6093 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) { in si_irq_set()
6107 if (rdev->irq.dpm_thermal) { in si_irq_set()
6112 for (i = 0; i < rdev->num_crtc; i++) { in si_irq_set()
6115 rdev->irq.crtc_vblank_int[i] || in si_irq_set()
6116 atomic_read(&rdev->irq.pflip[i]), "vblank", i); in si_irq_set()
6119 for (i = 0; i < rdev->num_crtc; i++) in si_irq_set()
6123 for (i = 0; i < 6; i++) { in si_irq_set()
6127 rdev->irq.hpd[i], "HPD", i); in si_irq_set()
6136 return 0; in si_irq_set()
6143 u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int; in si_irq_ack()
6144 u32 *grph_int = rdev->irq.stat_regs.evergreen.grph_int; in si_irq_ack()
6149 for (i = 0; i < 6; i++) { in si_irq_ack()
6151 if (i < rdev->num_crtc) in si_irq_ack()
6156 for (i = 0; i < rdev->num_crtc; i += 2) { in si_irq_ack()
6173 for (i = 0; i < 6; i++) { in si_irq_ack()
6178 for (i = 0; i < 6; i++) { in si_irq_ack()
6209 if (rdev->wb.enabled) in si_get_ih_wptr()
6210 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); in si_get_ih_wptr()
6220 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", in si_get_ih_wptr()
6221 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask); in si_get_ih_wptr()
6222 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; in si_get_ih_wptr()
6227 return (wptr & rdev->ih.ptr_mask); in si_get_ih_wptr()
6232 * [7:0] - interrupt source id
6233 * [31:8] - reserved
6234 * [59:32] - interrupt source data
6235 * [63:60] - reserved
6236 * [71:64] - RINGID
6237 * [79:72] - VMID
6238 * [127:80] - reserved
6242 u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int; in si_irq_process()
6255 if (!rdev->ih.enabled || rdev->shutdown) in si_irq_process()
6262 if (atomic_xchg(&rdev->ih.lock, 1)) in si_irq_process()
6265 rptr = rdev->ih.rptr; in si_irq_process()
6277 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; in si_irq_process()
6278 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; in si_irq_process()
6279 ring_id = le32_to_cpu(rdev->ih.ring[ring_index + 2]) & 0xff; in si_irq_process()
6288 crtc_idx = src_id - 1; in si_irq_process()
6290 if (src_data == 0) { /* vblank */ in si_irq_process()
6294 if (rdev->irq.crtc_vblank_int[crtc_idx]) { in si_irq_process()
6295 drm_handle_vblank(rdev->ddev, crtc_idx); in si_irq_process()
6296 rdev->pm.vblank_sync = true; in si_irq_process()
6297 wake_up(&rdev->irq.vblank_queue); in si_irq_process()
6299 if (atomic_read(&rdev->irq.pflip[crtc_idx])) { in si_irq_process()
6314 DRM_DEBUG("IH: D%d %s - IH event w/o asserted irq bit?\n", in si_irq_process()
6328 DRM_DEBUG("IH: D%d flip\n", ((src_id - 8) >> 1) + 1); in si_irq_process()
6329 if (radeon_use_pflipirq > 0) in si_irq_process()
6330 radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1); in si_irq_process()
6340 hpd_idx = src_data - 6; in si_irq_process()
6358 DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR)); in si_irq_process()
6359 WREG32(SRBM_INT_ACK, 0x1); in si_irq_process()
6362 DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data); in si_irq_process()
6371 if (addr == 0x0 && status == 0x0) in si_irq_process()
6373 dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data); in si_irq_process()
6374 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", in si_irq_process()
6376 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", in si_irq_process()
6392 case 0: in si_irq_process()
6409 rdev->pm.dpm.thermal.high_to_low = false; in si_irq_process()
6414 rdev->pm.dpm.thermal.high_to_low = true; in si_irq_process()
6431 rptr &= rdev->ih.ptr_mask; in si_irq_process()
6435 schedule_work(&rdev->dp_work); in si_irq_process()
6437 schedule_delayed_work(&rdev->hotplug_work, 0); in si_irq_process()
6438 if (queue_thermal && rdev->pm.dpm_enabled) in si_irq_process()
6439 schedule_work(&rdev->pm.dpm.thermal.work); in si_irq_process()
6440 rdev->ih.rptr = rptr; in si_irq_process()
6441 atomic_set(&rdev->ih.lock, 0); in si_irq_process()
6458 if (!rdev->has_uvd) in si_uvd_init()
6463 dev_err(rdev->dev, "failed UVD (%d) init.\n", r); in si_uvd_init()
6465 * At this point rdev->uvd.vcpu_bo is NULL which trickles down in si_uvd_init()
6470 rdev->has_uvd = false; in si_uvd_init()
6473 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL; in si_uvd_init()
6474 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096); in si_uvd_init()
6481 if (!rdev->has_uvd) in si_uvd_start()
6486 dev_err(rdev->dev, "failed UVD resume (%d).\n", r); in si_uvd_start()
6491 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r); in si_uvd_start()
6497 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; in si_uvd_start()
6505 if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size) in si_uvd_resume()
6508 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; in si_uvd_resume()
6509 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0)); in si_uvd_resume()
6511 dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r); in si_uvd_resume()
6516 dev_err(rdev->dev, "failed initializing UVD (%d).\n", r); in si_uvd_resume()
6525 if (!rdev->has_vce) in si_vce_init()
6530 dev_err(rdev->dev, "failed VCE (%d) init.\n", r); in si_vce_init()
6532 * At this point rdev->vce.vcpu_bo is NULL which trickles down in si_vce_init()
6537 rdev->has_vce = false; in si_vce_init()
6540 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_obj = NULL; in si_vce_init()
6541 r600_ring_init(rdev, &rdev->ring[TN_RING_TYPE_VCE1_INDEX], 4096); in si_vce_init()
6542 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_obj = NULL; in si_vce_init()
6543 r600_ring_init(rdev, &rdev->ring[TN_RING_TYPE_VCE2_INDEX], 4096); in si_vce_init()
6550 if (!rdev->has_vce) in si_vce_start()
6555 dev_err(rdev->dev, "failed VCE resume (%d).\n", r); in si_vce_start()
6560 dev_err(rdev->dev, "failed VCE resume (%d).\n", r); in si_vce_start()
6565 dev_err(rdev->dev, "failed initializing VCE1 fences (%d).\n", r); in si_vce_start()
6570 dev_err(rdev->dev, "failed initializing VCE2 fences (%d).\n", r); in si_vce_start()
6576 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size = 0; in si_vce_start()
6577 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_size = 0; in si_vce_start()
6585 if (!rdev->has_vce || !rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size) in si_vce_resume()
6588 ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX]; in si_vce_resume()
6589 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, VCE_CMD_NO_OP); in si_vce_resume()
6591 dev_err(rdev->dev, "failed initializing VCE1 ring (%d).\n", r); in si_vce_resume()
6594 ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX]; in si_vce_resume()
6595 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, VCE_CMD_NO_OP); in si_vce_resume()
6597 dev_err(rdev->dev, "failed initializing VCE1 ring (%d).\n", r); in si_vce_resume()
6602 dev_err(rdev->dev, "failed initializing VCE (%d).\n", r); in si_vce_resume()
6624 if (!rdev->pm.dpm_enabled) { in si_startup()
6638 if (rdev->family == CHIP_VERDE) { in si_startup()
6639 rdev->rlc.reg_list = verde_rlc_save_restore_register_list; in si_startup()
6640 rdev->rlc.reg_list_size = in si_startup()
6643 rdev->rlc.cs_data = si_cs_data; in si_startup()
6657 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in si_startup()
6663 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in si_startup()
6669 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in si_startup()
6675 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); in si_startup()
6681 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); in si_startup()
6689 if (!rdev->irq.installed) { in si_startup()
6703 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in si_startup()
6704 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, in si_startup()
6709 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; in si_startup()
6710 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET, in si_startup()
6715 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; in si_startup()
6716 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET, in si_startup()
6721 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; in si_startup()
6722 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, in si_startup()
6723 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0)); in si_startup()
6727 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; in si_startup()
6728 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET, in si_startup()
6729 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0)); in si_startup()
6749 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); in si_startup()
6755 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r); in si_startup()
6763 return 0; in si_startup()
6775 atom_asic_init(rdev->mode_info.atom_context); in si_resume()
6780 if (rdev->pm.pm_method == PM_METHOD_DPM) in si_resume()
6783 rdev->accel_working = true; in si_resume()
6787 rdev->accel_working = false; in si_resume()
6802 if (rdev->has_uvd) { in si_suspend()
6806 if (rdev->has_vce) in si_suspend()
6813 return 0; in si_suspend()
6824 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in si_init()
6830 return -EINVAL; in si_init()
6833 if (!rdev->is_atom_bios) { in si_init()
6834 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n"); in si_init()
6835 return -EINVAL; in si_init()
6843 if (!rdev->bios) { in si_init()
6844 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); in si_init()
6845 return -EINVAL; in si_init()
6848 atom_asic_init(rdev->mode_info.atom_context); in si_init()
6857 radeon_get_clock_info(rdev->ddev); in si_init()
6871 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw || in si_init()
6872 !rdev->rlc_fw || !rdev->mc_fw) { in si_init()
6883 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in si_init()
6884 ring->ring_obj = NULL; in si_init()
6887 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; in si_init()
6888 ring->ring_obj = NULL; in si_init()
6891 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; in si_init()
6892 ring->ring_obj = NULL; in si_init()
6895 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; in si_init()
6896 ring->ring_obj = NULL; in si_init()
6899 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; in si_init()
6900 ring->ring_obj = NULL; in si_init()
6906 rdev->ih.ring_obj = NULL; in si_init()
6913 rdev->accel_working = true; in si_init()
6916 dev_err(rdev->dev, "disabling GPU acceleration\n"); in si_init()
6926 rdev->accel_working = false; in si_init()
6933 if (!rdev->mc_fw) { in si_init()
6935 return -EINVAL; in si_init()
6938 return 0; in si_init()
6954 if (rdev->has_uvd) { in si_fini()
6958 if (rdev->has_vce) in si_fini()
6966 kfree(rdev->bios); in si_fini()
6967 rdev->bios = NULL; in si_fini()
6971 * si_get_gpu_clock_counter - return GPU clock counter snapshot
6982 mutex_lock(&rdev->gpu_clock_mutex); in si_get_gpu_clock_counter()
6986 mutex_unlock(&rdev->gpu_clock_mutex); in si_get_gpu_clock_counter()
6992 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in si_set_uvd_clocks()
7005 return 0; in si_set_uvd_clocks()
7009 16384, 0x03FFFFFF, 0, 128, 5, in si_set_uvd_clocks()
7014 /* set RESET_ANTI_MUX to 0 */ in si_set_uvd_clocks()
7015 WREG32_P(CG_UPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK); in si_set_uvd_clocks()
7021 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK); in si_set_uvd_clocks()
7024 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in si_set_uvd_clocks()
7036 WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK); in si_set_uvd_clocks()
7041 /* set ref divider to 0 */ in si_set_uvd_clocks()
7042 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK); in si_set_uvd_clocks()
7045 WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9); in si_set_uvd_clocks()
7058 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in si_set_uvd_clocks()
7063 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); in si_set_uvd_clocks()
7076 return 0; in si_set_uvd_clocks()
7081 struct pci_dev *root = rdev->pdev->bus->self; in si_pcie_gen3_enable()
7087 if (pci_is_root_bus(rdev->pdev->bus)) in si_pcie_gen3_enable()
7090 if (radeon_pcie_gen2 == 0) in si_pcie_gen3_enable()
7093 if (rdev->flags & RADEON_IS_IGP) in si_pcie_gen3_enable()
7096 if (!(rdev->flags & RADEON_IS_PCIE)) in si_pcie_gen3_enable()
7115 DRM_INFO("enabling PCIE gen 3 link speeds, disable with radeon.pcie_gen2=0\n"); in si_pcie_gen3_enable()
7121 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); in si_pcie_gen3_enable()
7124 if (!pci_is_pcie(root) || !pci_is_pcie(rdev->pdev)) in si_pcie_gen3_enable()
7128 /* re-try equalization if gen3 is not already enabled */ in si_pcie_gen3_enable()
7136 pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL, in si_pcie_gen3_enable()
7143 pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL, in si_pcie_gen3_enable()
7160 for (i = 0; i < 10; i++) { in si_pcie_gen3_enable()
7162 pcie_capability_read_word(rdev->pdev, in si_pcie_gen3_enable()
7170 pcie_capability_read_word(rdev->pdev, in si_pcie_gen3_enable()
7176 pcie_capability_read_word(rdev->pdev, in si_pcie_gen3_enable()
7199 pcie_capability_read_word(rdev->pdev, in si_pcie_gen3_enable()
7204 pcie_capability_write_word(rdev->pdev, in si_pcie_gen3_enable()
7220 pcie_capability_read_word(rdev->pdev, in si_pcie_gen3_enable()
7228 pcie_capability_write_word(rdev->pdev, in si_pcie_gen3_enable()
7244 pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL2, &tmp16); in si_pcie_gen3_enable()
7252 pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL2, tmp16); in si_pcie_gen3_enable()
7258 for (i = 0; i < rdev->usec_timeout; i++) { in si_pcie_gen3_enable()
7260 if ((speed_cntl & LC_INITIATE_LINK_SPEED_CHANGE) == 0) in si_pcie_gen3_enable()
7272 if (radeon_aspm == 0) in si_program_aspm()
7275 if (!(rdev->flags & RADEON_IS_PCIE)) in si_program_aspm()
7280 data |= LC_XMIT_N_FTS(0x24) | LC_XMIT_N_FTS_OVERRIDE_EN; in si_program_aspm()
7333 if ((rdev->family != CHIP_OLAND) && (rdev->family != CHIP_HAINAN)) { in si_program_aspm()
7382 if ((rdev->family == CHIP_OLAND) || (rdev->family == CHIP_HAINAN)) in si_program_aspm()
7389 if ((rdev->family == CHIP_OLAND) || (rdev->family == CHIP_HAINAN)) in si_program_aspm()
7395 !pci_is_root_bus(rdev->pdev->bus)) { in si_program_aspm()
7396 struct pci_dev *root = rdev->pdev->bus->self; in si_program_aspm()
7476 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK); in si_vce_send_vcepll_ctlreq()
7484 for (i = 0; i < 100; ++i) { in si_vce_send_vcepll_ctlreq()
7492 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK); in si_vce_send_vcepll_ctlreq()
7496 return -ETIMEDOUT; in si_vce_send_vcepll_ctlreq()
7499 return 0; in si_vce_send_vcepll_ctlreq()
7504 unsigned fb_div = 0, evclk_div = 0, ecclk_div = 0; in si_set_vce_clocks()
7520 return 0; in si_set_vce_clocks()
7524 16384, 0x03FFFFFF, 0, 128, 5, in si_set_vce_clocks()
7529 /* set RESET_ANTI_MUX to 0 */ in si_set_vce_clocks()
7530 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK); in si_set_vce_clocks()
7536 /* toggle VCEPLL_SLEEP to 1 then back to 0 */ in si_set_vce_clocks()
7539 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_SLEEP_MASK); in si_set_vce_clocks()
7542 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK); in si_set_vce_clocks()
7554 WREG32_SMC_P(CG_VCEPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK); in si_set_vce_clocks()
7559 /* set ref divider to 0 */ in si_set_vce_clocks()
7560 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_REF_DIV_MASK); in si_set_vce_clocks()
7571 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK); in si_set_vce_clocks()
7576 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_BYPASS_EN_MASK); in si_set_vce_clocks()
7589 return 0; in si_set_vce_clocks()