Lines Matching +full:idle +full:- +full:wait +full:- +full:delay
39 #include <linux/io-64-nonatomic-lo-hi.h>
60 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
85 * avivo_wait_for_vblank - vblank wait asic callback.
88 * @crtc: crtc to wait for vblank on
90 * Wait for vblank on the requested crtc (r5xx-r7xx).
96 if (crtc >= rdev->num_crtc) in avivo_wait_for_vblank()
103 * wait for another frame. in avivo_wait_for_vblank()
122 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in rs600_page_flip()
123 struct drm_framebuffer *fb = radeon_crtc->base.primary->fb; in rs600_page_flip()
124 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); in rs600_page_flip()
129 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rs600_page_flip()
132 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, in rs600_page_flip()
135 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, in rs600_page_flip()
136 fb->pitches[0] / fb->format->cpp[0]); in rs600_page_flip()
138 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rs600_page_flip()
140 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rs600_page_flip()
143 /* Wait for update_pending to go high. */ in rs600_page_flip()
144 for (i = 0; i < rdev->usec_timeout; i++) { in rs600_page_flip()
145 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) in rs600_page_flip()
151 /* Unlock the lock, so double-buffering can take place inside vblank */ in rs600_page_flip()
153 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rs600_page_flip()
158 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in rs600_page_flip_pending()
161 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & in rs600_page_flip_pending()
167 struct drm_device *dev = encoder->dev; in avivo_program_fmt()
168 struct radeon_device *rdev = dev->dev_private; in avivo_program_fmt()
178 dither = radeon_connector->dither; in avivo_program_fmt()
182 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) in avivo_program_fmt()
211 switch (radeon_encoder->encoder_id) { in avivo_program_fmt()
231 int requested_index = rdev->pm.requested_power_state_index; in rs600_pm_misc()
232 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; in rs600_pm_misc()
233 struct radeon_voltage *voltage = &ps->clock_info[0].voltage; in rs600_pm_misc()
237 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) { in rs600_pm_misc()
238 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { in rs600_pm_misc()
239 tmp = RREG32(voltage->gpio.reg); in rs600_pm_misc()
240 if (voltage->active_high) in rs600_pm_misc()
241 tmp |= voltage->gpio.mask; in rs600_pm_misc()
243 tmp &= ~(voltage->gpio.mask); in rs600_pm_misc()
244 WREG32(voltage->gpio.reg, tmp); in rs600_pm_misc()
245 if (voltage->delay) in rs600_pm_misc()
246 udelay(voltage->delay); in rs600_pm_misc()
248 tmp = RREG32(voltage->gpio.reg); in rs600_pm_misc()
249 if (voltage->active_high) in rs600_pm_misc()
250 tmp &= ~voltage->gpio.mask; in rs600_pm_misc()
252 tmp |= voltage->gpio.mask; in rs600_pm_misc()
253 WREG32(voltage->gpio.reg, tmp); in rs600_pm_misc()
254 if (voltage->delay) in rs600_pm_misc()
255 udelay(voltage->delay); in rs600_pm_misc()
257 } else if (voltage->type == VOLTAGE_VDDC) in rs600_pm_misc()
258 radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC); in rs600_pm_misc()
263 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) { in rs600_pm_misc()
264 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) { in rs600_pm_misc()
267 } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) { in rs600_pm_misc()
278 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) { in rs600_pm_misc()
280 if (voltage->delay) { in rs600_pm_misc()
282 dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay); in rs600_pm_misc()
290 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN) in rs600_pm_misc()
298 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN) in rs600_pm_misc()
305 if (ps->misc & ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN) in rs600_pm_misc()
312 if ((rdev->flags & RADEON_IS_PCIE) && in rs600_pm_misc()
313 !(rdev->flags & RADEON_IS_IGP) && in rs600_pm_misc()
314 rdev->asic->pm.set_pcie_lanes && in rs600_pm_misc()
315 (ps->pcie_lanes != in rs600_pm_misc()
316 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { in rs600_pm_misc()
318 ps->pcie_lanes); in rs600_pm_misc()
319 DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes); in rs600_pm_misc()
325 struct drm_device *ddev = rdev->ddev; in rs600_pm_prepare()
331 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { in rs600_pm_prepare()
333 if (radeon_crtc->enabled) { in rs600_pm_prepare()
334 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); in rs600_pm_prepare()
336 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); in rs600_pm_prepare()
343 struct drm_device *ddev = rdev->ddev; in rs600_pm_finish()
349 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { in rs600_pm_finish()
351 if (radeon_crtc->enabled) { in rs600_pm_finish()
352 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); in rs600_pm_finish()
354 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); in rs600_pm_finish()
412 struct drm_device *dev = rdev->ddev; in rs600_hpd_init()
416 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { in rs600_hpd_init()
418 switch (radeon_connector->hpd.hpd) { in rs600_hpd_init()
430 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) in rs600_hpd_init()
431 enable |= 1 << radeon_connector->hpd.hpd; in rs600_hpd_init()
432 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); in rs600_hpd_init()
439 struct drm_device *dev = rdev->ddev; in rs600_hpd_fini()
443 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { in rs600_hpd_fini()
445 switch (radeon_connector->hpd.hpd) { in rs600_hpd_fini()
457 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) in rs600_hpd_fini()
458 disable |= 1 << radeon_connector->hpd.hpd; in rs600_hpd_fini()
476 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); in rs600_asic_reset()
484 pci_save_state(rdev->pdev); in rs600_asic_reset()
486 pci_clear_master(rdev->pdev); in rs600_asic_reset()
496 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); in rs600_asic_reset()
504 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); in rs600_asic_reset()
512 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); in rs600_asic_reset()
514 pci_restore_state(rdev->pdev); in rs600_asic_reset()
515 /* Check if GPU is idle */ in rs600_asic_reset()
517 dev_err(rdev->dev, "failed to reset GPU\n"); in rs600_asic_reset()
518 ret = -1; in rs600_asic_reset()
520 dev_info(rdev->dev, "GPU reset succeed\n"); in rs600_asic_reset()
550 if (rdev->gart.robj) { in rs600_gart_init()
559 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; in rs600_gart_init()
568 if (rdev->gart.robj == NULL) { in rs600_gart_enable()
569 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); in rs600_gart_enable()
570 return -EINVAL; in rs600_gart_enable()
605 rdev->gart.table_addr); in rs600_gart_enable()
606 WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start); in rs600_gart_enable()
607 WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end); in rs600_gart_enable()
611 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start); in rs600_gart_enable()
612 WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end); in rs600_gart_enable()
621 (unsigned)(rdev->mc.gtt_size >> 20), in rs600_gart_enable()
622 (unsigned long long)rdev->gart.table_addr); in rs600_gart_enable()
623 rdev->gart.ready = true; in rs600_gart_enable()
663 void __iomem *ptr = (void *)rdev->gart.ptr; in rs600_gart_set_page()
682 if (!rdev->irq.installed) { in rs600_irq_set()
685 return -EINVAL; in rs600_irq_set()
687 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { in rs600_irq_set()
690 if (rdev->irq.crtc_vblank_int[0] || in rs600_irq_set()
691 atomic_read(&rdev->irq.pflip[0])) { in rs600_irq_set()
694 if (rdev->irq.crtc_vblank_int[1] || in rs600_irq_set()
695 atomic_read(&rdev->irq.pflip[1])) { in rs600_irq_set()
698 if (rdev->irq.hpd[0]) { in rs600_irq_set()
701 if (rdev->irq.hpd[1]) { in rs600_irq_set()
704 if (rdev->irq.afmt[0]) { in rs600_irq_set()
727 rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); in rs600_irq_ack()
728 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_ack()
732 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_ack()
736 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_ack()
741 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_ack()
747 rdev->irq.stat_regs.r500.disp_int = 0; in rs600_irq_ack()
751 rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) & in rs600_irq_ack()
753 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { in rs600_irq_ack()
759 rdev->irq.stat_regs.r500.hdmi0_status = 0; in rs600_irq_ack()
774 /* Wait and acknowledge irq */ in rs600_irq_disable()
787 !rdev->irq.stat_regs.r500.disp_int && in rs600_irq_process()
788 !rdev->irq.stat_regs.r500.hdmi0_status) { in rs600_irq_process()
792 rdev->irq.stat_regs.r500.disp_int || in rs600_irq_process()
793 rdev->irq.stat_regs.r500.hdmi0_status) { in rs600_irq_process()
799 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_process()
800 if (rdev->irq.crtc_vblank_int[0]) { in rs600_irq_process()
801 drm_handle_vblank(rdev->ddev, 0); in rs600_irq_process()
802 rdev->pm.vblank_sync = true; in rs600_irq_process()
803 wake_up(&rdev->irq.vblank_queue); in rs600_irq_process()
805 if (atomic_read(&rdev->irq.pflip[0])) in rs600_irq_process()
808 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_process()
809 if (rdev->irq.crtc_vblank_int[1]) { in rs600_irq_process()
810 drm_handle_vblank(rdev->ddev, 1); in rs600_irq_process()
811 rdev->pm.vblank_sync = true; in rs600_irq_process()
812 wake_up(&rdev->irq.vblank_queue); in rs600_irq_process()
814 if (atomic_read(&rdev->irq.pflip[1])) in rs600_irq_process()
817 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_process()
821 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_process()
825 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { in rs600_irq_process()
832 schedule_delayed_work(&rdev->hotplug_work, 0); in rs600_irq_process()
834 schedule_work(&rdev->audio_work); in rs600_irq_process()
835 if (rdev->msi_enabled) { in rs600_irq_process()
836 switch (rdev->family) { in rs600_irq_process()
864 for (i = 0; i < rdev->usec_timeout; i++) { in rs600_mc_wait_for_idle()
869 return -1; in rs600_mc_wait_for_idle()
875 /* Wait for mc idle */ in rs600_gpu_init()
877 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); in rs600_gpu_init()
884 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); in rs600_mc_init()
885 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); in rs600_mc_init()
886 rdev->mc.vram_is_ddr = true; in rs600_mc_init()
887 rdev->mc.vram_width = 128; in rs600_mc_init()
888 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); in rs600_mc_init()
889 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; in rs600_mc_init()
890 rdev->mc.visible_vram_size = rdev->mc.aper_size; in rs600_mc_init()
891 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); in rs600_mc_init()
894 radeon_vram_location(rdev, &rdev->mc, base); in rs600_mc_init()
895 rdev->mc.gtt_base_align = 0; in rs600_mc_init()
896 radeon_gtt_location(rdev, &rdev->mc); in rs600_mc_init()
907 if (!rdev->mode_info.mode_config_initialized) in rs600_bandwidth_update()
912 if (rdev->mode_info.crtcs[0]->base.enabled) in rs600_bandwidth_update()
913 mode0 = &rdev->mode_info.crtcs[0]->base.mode; in rs600_bandwidth_update()
914 if (rdev->mode_info.crtcs[1]->base.enabled) in rs600_bandwidth_update()
915 mode1 = &rdev->mode_info.crtcs[1]->base.mode; in rs600_bandwidth_update()
919 if (rdev->disp_priority == 2) { in rs600_bandwidth_update()
936 spin_lock_irqsave(&rdev->mc_idx_lock, flags); in rs600_mc_rreg()
940 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); in rs600_mc_rreg()
948 spin_lock_irqsave(&rdev->mc_idx_lock, flags); in rs600_mc_wreg()
952 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); in rs600_mc_wreg()
957 rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm; in rs600_set_safe_registers()
958 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm); in rs600_set_safe_registers()
968 /* Wait for mc idle */ in rs600_mc_program()
970 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); in rs600_mc_program()
978 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | in rs600_mc_program()
979 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); in rs600_mc_program()
981 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); in rs600_mc_program()
1008 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in rs600_startup()
1013 if (!rdev->irq.installed) { in rs600_startup()
1020 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); in rs600_startup()
1024 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); in rs600_startup()
1030 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); in rs600_startup()
1036 dev_err(rdev->dev, "failed initializing audio\n"); in rs600_startup()
1053 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", in rs600_resume()
1058 atom_asic_init(rdev->mode_info.atom_context); in rs600_resume()
1064 rdev->accel_working = true; in rs600_resume()
1067 rdev->accel_working = false; in rs600_resume()
1096 kfree(rdev->bios); in rs600_fini()
1097 rdev->bios = NULL; in rs600_fini()
1115 return -EINVAL; in rs600_init()
1117 if (rdev->is_atom_bios) { in rs600_init()
1122 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n"); in rs600_init()
1123 return -EINVAL; in rs600_init()
1127 dev_warn(rdev->dev, in rs600_init()
1134 return -EINVAL; in rs600_init()
1137 radeon_get_clock_info(rdev->ddev); in rs600_init()
1155 rdev->accel_working = true; in rs600_init()
1159 dev_err(rdev->dev, "Disabling GPU acceleration\n"); in rs600_init()
1165 rdev->accel_working = false; in rs600_init()