1636 	u32 idx_value;  in r600_packet3_check()  local
1641 	idx_value = radeon_get_ib_value(p, idx);  in r600_packet3_check()
1674 			 (idx_value & 0xfffffff0) +  in r600_packet3_check()
1715 			 idx_value +  in r600_packet3_check()
1757 		if (idx_value & 0x10) {  in r600_packet3_check()
1772 		} else if (idx_value & 0x100) {  in r600_packet3_check()
1909 		start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET;  in r600_packet3_check()
1925 		start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET;  in r600_packet3_check()
1945 		start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET;  in r600_packet3_check()
2025 			start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET;  in r600_packet3_check()
2036 		start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET;  in r600_packet3_check()
2046 		start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_OFFSET;  in r600_packet3_check()
2056 		start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_OFFSET;  in r600_packet3_check()
2070 		start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_OFFSET;  in r600_packet3_check()
2089 		if (idx_value > 3) {  in r600_packet3_check()
2102 			if (reloc->robj != track->vgt_strmout_bo[idx_value]) {  in r600_packet3_check()
2108 			if (offset != track->vgt_strmout_bo_offset[idx_value]) {  in r600_packet3_check()
2110 					  offset, track->vgt_strmout_bo_offset[idx_value]);  in r600_packet3_check()
2138 		if (idx_value & 0x1) {  in r600_packet3_check()
2157 		if (((idx_value >> 1) & 0x3) == 2) {  in r600_packet3_check()
2210 		if (idx_value & 0x1) {  in r600_packet3_check()
2234 		if (idx_value & 0x2) {  in r600_packet3_check()
2382 	u32 idx, idx_value;  in r600_dma_cs_parse()  local
2437 				idx_value = radeon_get_ib_value(p, idx + 2);  in r600_dma_cs_parse()
2439 				if (idx_value & (1 << 31)) {  in r600_dma_cs_parse()