49 #define DC_HPDx_CONTROL(x)        (DC_HPD1_CONTROL     + (x * 0xc))
50 #define DC_HPDx_INT_CONTROL(x)    (DC_HPD1_INT_CONTROL + (x * 0xc))
51 #define DC_HPDx_INT_STATUS_REG(x) (DC_HPD1_INT_STATUS  + (x * 0xc))
61 	spin_lock_irqsave(&rdev->cg_idx_lock, flags);  in eg_cg_rreg()
62 	WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));  in eg_cg_rreg()
64 	spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);  in eg_cg_rreg()
72 	spin_lock_irqsave(&rdev->cg_idx_lock, flags);  in eg_cg_wreg()
73 	WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));  in eg_cg_wreg()
75 	spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);  in eg_cg_wreg()
83 	spin_lock_irqsave(&rdev->pif_idx_lock, flags);  in eg_pif_phy0_rreg()
84 	WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));  in eg_pif_phy0_rreg()
86 	spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);  in eg_pif_phy0_rreg()
94 	spin_lock_irqsave(&rdev->pif_idx_lock, flags);  in eg_pif_phy0_wreg()
95 	WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));  in eg_pif_phy0_wreg()
97 	spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);  in eg_pif_phy0_wreg()
105 	spin_lock_irqsave(&rdev->pif_idx_lock, flags);  in eg_pif_phy1_rreg()
106 	WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));  in eg_pif_phy1_rreg()
108 	spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);  in eg_pif_phy1_rreg()
116 	spin_lock_irqsave(&rdev->pif_idx_lock, flags);  in eg_pif_phy1_wreg()
117 	WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));  in eg_pif_phy1_wreg()
119 	spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);  in eg_pif_phy1_wreg()
136 	0x98fc,
137 	0x9830,
138 	0x9834,
139 	0x9838,
140 	0x9870,
141 	0x9874,
142 	0x8a14,
143 	0x8b24,
144 	0x8bcc,
145 	0x8b10,
146 	0x8d00,
147 	0x8d04,
148 	0x8c00,
149 	0x8c04,
150 	0x8c08,
151 	0x8c0c,
152 	0x8d8c,
153 	0x8c20,
154 	0x8c24,
155 	0x8c28,
156 	0x8c18,
157 	0x8c1c,
158 	0x8cf0,
159 	0x8e2c,
160 	0x8e38,
161 	0x8c30,
162 	0x9508,
163 	0x9688,
164 	0x9608,
165 	0x960c,
166 	0x9610,
167 	0x9614,
168 	0x88c4,
169 	0x88d4,
170 	0xa008,
171 	0x900c,
172 	0x9100,
173 	0x913c,
174 	0x98f8,
175 	0x98f4,
176 	0x9b7c,
177 	0x3f8c,
178 	0x8950,
179 	0x8954,
180 	0x8a18,
181 	0x8b28,
182 	0x9144,
183 	0x9148,
184 	0x914c,
185 	0x3f90,
186 	0x3f94,
187 	0x915c,
188 	0x9160,
189 	0x9178,
190 	0x917c,
191 	0x9180,
192 	0x918c,
193 	0x9190,
194 	0x9194,
195 	0x9198,
196 	0x919c,
197 	0x91a8,
198 	0x91ac,
199 	0x91b0,
200 	0x91b4,
201 	0x91b8,
202 	0x91c4,
203 	0x91c8,
204 	0x91cc,
205 	0x91d0,
206 	0x91d4,
207 	0x91e0,
208 	0x91e4,
209 	0x91ec,
210 	0x91f0,
211 	0x91f4,
212 	0x9200,
213 	0x9204,
214 	0x929c,
215 	0x9150,
216 	0x802c,
226 	0x3f90, 0xffff0000, 0xff000000,
227 	0x9148, 0xffff0000, 0xff000000,
228 	0x3f94, 0xffff0000, 0xff000000,
229 	0x914c, 0xffff0000, 0xff000000,
230 	0x9b7c, 0xffffffff, 0x00000000,
231 	0x8a14, 0xffffffff, 0x00000007,
232 	0x8b10, 0xffffffff, 0x00000000,
233 	0x960c, 0xffffffff, 0x54763210,
234 	0x88c4, 0xffffffff, 0x000000c2,
235 	0x88d4, 0xffffffff, 0x00000010,
236 	0x8974, 0xffffffff, 0x00000000,
237 	0xc78, 0x00000080, 0x00000080,
238 	0x5eb4, 0xffffffff, 0x00000002,
239 	0x5e78, 0xffffffff, 0x001000f0,
240 	0x6104, 0x01000300, 0x00000000,
241 	0x5bc0, 0x00300000, 0x00000000,
242 	0x7030, 0xffffffff, 0x00000011,
243 	0x7c30, 0xffffffff, 0x00000011,
244 	0x10830, 0xffffffff, 0x00000011,
245 	0x11430, 0xffffffff, 0x00000011,
246 	0x12030, 0xffffffff, 0x00000011,
247 	0x12c30, 0xffffffff, 0x00000011,
248 	0xd02c, 0xffffffff, 0x08421000,
249 	0x240c, 0xffffffff, 0x00000380,
250 	0x8b24, 0xffffffff, 0x00ff0fff,
251 	0x28a4c, 0x06000000, 0x06000000,
252 	0x10c, 0x00000001, 0x00000001,
253 	0x8d00, 0xffffffff, 0x100e4848,
254 	0x8d04, 0xffffffff, 0x00164745,
255 	0x8c00, 0xffffffff, 0xe4000003,
256 	0x8c04, 0xffffffff, 0x40600060,
257 	0x8c08, 0xffffffff, 0x001c001c,
258 	0x8cf0, 0xffffffff, 0x08e00620,
259 	0x8c20, 0xffffffff, 0x00800080,
260 	0x8c24, 0xffffffff, 0x00800080,
261 	0x8c18, 0xffffffff, 0x20202078,
262 	0x8c1c, 0xffffffff, 0x00001010,
263 	0x28350, 0xffffffff, 0x00000000,
264 	0xa008, 0xffffffff, 0x00010000,
265 	0x5c4, 0xffffffff, 0x00000001,
266 	0x9508, 0xffffffff, 0x00000002,
267 	0x913c, 0x0000000f, 0x0000000a
272 	0x2f4c, 0xffffffff, 0x00000000,
273 	0x54f4, 0xffffffff, 0x00000000,
274 	0x54f0, 0xffffffff, 0x00000000,
275 	0x5498, 0xffffffff, 0x00000000,
276 	0x549c, 0xffffffff, 0x00000000,
277 	0x5494, 0xffffffff, 0x00000000,
278 	0x53cc, 0xffffffff, 0x00000000,
279 	0x53c8, 0xffffffff, 0x00000000,
280 	0x53c4, 0xffffffff, 0x00000000,
281 	0x53c0, 0xffffffff, 0x00000000,
282 	0x53bc, 0xffffffff, 0x00000000,
283 	0x53b8, 0xffffffff, 0x00000000,
284 	0x53b4, 0xffffffff, 0x00000000,
285 	0x53b0, 0xffffffff, 0x00000000
290 	0x802c, 0xffffffff, 0xc0000000,
291 	0x5448, 0xffffffff, 0x00000100,
292 	0x55e4, 0xffffffff, 0x00000100,
293 	0x160c, 0xffffffff, 0x00000100,
294 	0x5644, 0xffffffff, 0x00000100,
295 	0xc164, 0xffffffff, 0x00000100,
296 	0x8a18, 0xffffffff, 0x00000100,
297 	0x897c, 0xffffffff, 0x06000100,
298 	0x8b28, 0xffffffff, 0x00000100,
299 	0x9144, 0xffffffff, 0x00000100,
300 	0x9a60, 0xffffffff, 0x00000100,
301 	0x9868, 0xffffffff, 0x00000100,
302 	0x8d58, 0xffffffff, 0x00000100,
303 	0x9510, 0xffffffff, 0x00000100,
304 	0x949c, 0xffffffff, 0x00000100,
305 	0x9654, 0xffffffff, 0x00000100,
306 	0x9030, 0xffffffff, 0x00000100,
307 	0x9034, 0xffffffff, 0x00000100,
308 	0x9038, 0xffffffff, 0x00000100,
309 	0x903c, 0xffffffff, 0x00000100,
310 	0x9040, 0xffffffff, 0x00000100,
311 	0xa200, 0xffffffff, 0x00000100,
312 	0xa204, 0xffffffff, 0x00000100,
313 	0xa208, 0xffffffff, 0x00000100,
314 	0xa20c, 0xffffffff, 0x00000100,
315 	0x971c, 0xffffffff, 0x00000100,
316 	0x977c, 0xffffffff, 0x00000100,
317 	0x3f80, 0xffffffff, 0x00000100,
318 	0xa210, 0xffffffff, 0x00000100,
319 	0xa214, 0xffffffff, 0x00000100,
320 	0x4d8, 0xffffffff, 0x00000100,
321 	0x9784, 0xffffffff, 0x00000100,
322 	0x9698, 0xffffffff, 0x00000100,
323 	0x4d4, 0xffffffff, 0x00000200,
324 	0x30cc, 0xffffffff, 0x00000100,
325 	0xd0c0, 0xffffffff, 0xff000100,
326 	0x802c, 0xffffffff, 0x40000000,
327 	0x915c, 0xffffffff, 0x00010000,
328 	0x9160, 0xffffffff, 0x00030002,
329 	0x9178, 0xffffffff, 0x00070000,
330 	0x917c, 0xffffffff, 0x00030002,
331 	0x9180, 0xffffffff, 0x00050004,
332 	0x918c, 0xffffffff, 0x00010006,
333 	0x9190, 0xffffffff, 0x00090008,
334 	0x9194, 0xffffffff, 0x00070000,
335 	0x9198, 0xffffffff, 0x00030002,
336 	0x919c, 0xffffffff, 0x00050004,
337 	0x91a8, 0xffffffff, 0x00010006,
338 	0x91ac, 0xffffffff, 0x00090008,
339 	0x91b0, 0xffffffff, 0x00070000,
340 	0x91b4, 0xffffffff, 0x00030002,
341 	0x91b8, 0xffffffff, 0x00050004,
342 	0x91c4, 0xffffffff, 0x00010006,
343 	0x91c8, 0xffffffff, 0x00090008,
344 	0x91cc, 0xffffffff, 0x00070000,
345 	0x91d0, 0xffffffff, 0x00030002,
346 	0x91d4, 0xffffffff, 0x00050004,
347 	0x91e0, 0xffffffff, 0x00010006,
348 	0x91e4, 0xffffffff, 0x00090008,
349 	0x91e8, 0xffffffff, 0x00000000,
350 	0x91ec, 0xffffffff, 0x00070000,
351 	0x91f0, 0xffffffff, 0x00030002,
352 	0x91f4, 0xffffffff, 0x00050004,
353 	0x9200, 0xffffffff, 0x00010006,
354 	0x9204, 0xffffffff, 0x00090008,
355 	0x9208, 0xffffffff, 0x00070000,
356 	0x920c, 0xffffffff, 0x00030002,
357 	0x9210, 0xffffffff, 0x00050004,
358 	0x921c, 0xffffffff, 0x00010006,
359 	0x9220, 0xffffffff, 0x00090008,
360 	0x9224, 0xffffffff, 0x00070000,
361 	0x9228, 0xffffffff, 0x00030002,
362 	0x922c, 0xffffffff, 0x00050004,
363 	0x9238, 0xffffffff, 0x00010006,
364 	0x923c, 0xffffffff, 0x00090008,
365 	0x9240, 0xffffffff, 0x00070000,
366 	0x9244, 0xffffffff, 0x00030002,
367 	0x9248, 0xffffffff, 0x00050004,
368 	0x9254, 0xffffffff, 0x00010006,
369 	0x9258, 0xffffffff, 0x00090008,
370 	0x925c, 0xffffffff, 0x00070000,
371 	0x9260, 0xffffffff, 0x00030002,
372 	0x9264, 0xffffffff, 0x00050004,
373 	0x9270, 0xffffffff, 0x00010006,
374 	0x9274, 0xffffffff, 0x00090008,
375 	0x9278, 0xffffffff, 0x00070000,
376 	0x927c, 0xffffffff, 0x00030002,
377 	0x9280, 0xffffffff, 0x00050004,
378 	0x928c, 0xffffffff, 0x00010006,
379 	0x9290, 0xffffffff, 0x00090008,
380 	0x9294, 0xffffffff, 0x00000000,
381 	0x929c, 0xffffffff, 0x00000001,
382 	0x802c, 0xffffffff, 0x40010000,
383 	0x915c, 0xffffffff, 0x00010000,
384 	0x9160, 0xffffffff, 0x00030002,
385 	0x9178, 0xffffffff, 0x00070000,
386 	0x917c, 0xffffffff, 0x00030002,
387 	0x9180, 0xffffffff, 0x00050004,
388 	0x918c, 0xffffffff, 0x00010006,
389 	0x9190, 0xffffffff, 0x00090008,
390 	0x9194, 0xffffffff, 0x00070000,
391 	0x9198, 0xffffffff, 0x00030002,
392 	0x919c, 0xffffffff, 0x00050004,
393 	0x91a8, 0xffffffff, 0x00010006,
394 	0x91ac, 0xffffffff, 0x00090008,
395 	0x91b0, 0xffffffff, 0x00070000,
396 	0x91b4, 0xffffffff, 0x00030002,
397 	0x91b8, 0xffffffff, 0x00050004,
398 	0x91c4, 0xffffffff, 0x00010006,
399 	0x91c8, 0xffffffff, 0x00090008,
400 	0x91cc, 0xffffffff, 0x00070000,
401 	0x91d0, 0xffffffff, 0x00030002,
402 	0x91d4, 0xffffffff, 0x00050004,
403 	0x91e0, 0xffffffff, 0x00010006,
404 	0x91e4, 0xffffffff, 0x00090008,
405 	0x91e8, 0xffffffff, 0x00000000,
406 	0x91ec, 0xffffffff, 0x00070000,
407 	0x91f0, 0xffffffff, 0x00030002,
408 	0x91f4, 0xffffffff, 0x00050004,
409 	0x9200, 0xffffffff, 0x00010006,
410 	0x9204, 0xffffffff, 0x00090008,
411 	0x9208, 0xffffffff, 0x00070000,
412 	0x920c, 0xffffffff, 0x00030002,
413 	0x9210, 0xffffffff, 0x00050004,
414 	0x921c, 0xffffffff, 0x00010006,
415 	0x9220, 0xffffffff, 0x00090008,
416 	0x9224, 0xffffffff, 0x00070000,
417 	0x9228, 0xffffffff, 0x00030002,
418 	0x922c, 0xffffffff, 0x00050004,
419 	0x9238, 0xffffffff, 0x00010006,
420 	0x923c, 0xffffffff, 0x00090008,
421 	0x9240, 0xffffffff, 0x00070000,
422 	0x9244, 0xffffffff, 0x00030002,
423 	0x9248, 0xffffffff, 0x00050004,
424 	0x9254, 0xffffffff, 0x00010006,
425 	0x9258, 0xffffffff, 0x00090008,
426 	0x925c, 0xffffffff, 0x00070000,
427 	0x9260, 0xffffffff, 0x00030002,
428 	0x9264, 0xffffffff, 0x00050004,
429 	0x9270, 0xffffffff, 0x00010006,
430 	0x9274, 0xffffffff, 0x00090008,
431 	0x9278, 0xffffffff, 0x00070000,
432 	0x927c, 0xffffffff, 0x00030002,
433 	0x9280, 0xffffffff, 0x00050004,
434 	0x928c, 0xffffffff, 0x00010006,
435 	0x9290, 0xffffffff, 0x00090008,
436 	0x9294, 0xffffffff, 0x00000000,
437 	0x929c, 0xffffffff, 0x00000001,
438 	0x802c, 0xffffffff, 0xc0000000
443 	0x802c, 0xffffffff, 0xc0000000,
444 	0x5448, 0xffffffff, 0x00000100,
445 	0x55e4, 0xffffffff, 0x00000100,
446 	0x160c, 0xffffffff, 0x00000100,
447 	0x5644, 0xffffffff, 0x00000100,
448 	0xc164, 0xffffffff, 0x00000100,
449 	0x8a18, 0xffffffff, 0x00000100,
450 	0x897c, 0xffffffff, 0x06000100,
451 	0x8b28, 0xffffffff, 0x00000100,
452 	0x9144, 0xffffffff, 0x00000100,
453 	0x9a60, 0xffffffff, 0x00000100,
454 	0x9868, 0xffffffff, 0x00000100,
455 	0x8d58, 0xffffffff, 0x00000100,
456 	0x9510, 0xffffffff, 0x00000100,
457 	0x949c, 0xffffffff, 0x00000100,
458 	0x9654, 0xffffffff, 0x00000100,
459 	0x9030, 0xffffffff, 0x00000100,
460 	0x9034, 0xffffffff, 0x00000100,
461 	0x9038, 0xffffffff, 0x00000100,
462 	0x903c, 0xffffffff, 0x00000100,
463 	0x9040, 0xffffffff, 0x00000100,
464 	0xa200, 0xffffffff, 0x00000100,
465 	0xa204, 0xffffffff, 0x00000100,
466 	0xa208, 0xffffffff, 0x00000100,
467 	0xa20c, 0xffffffff, 0x00000100,
468 	0x971c, 0xffffffff, 0x00000100,
469 	0x977c, 0xffffffff, 0x00000100,
470 	0x3f80, 0xffffffff, 0x00000100,
471 	0xa210, 0xffffffff, 0x00000100,
472 	0xa214, 0xffffffff, 0x00000100,
473 	0x4d8, 0xffffffff, 0x00000100,
474 	0x9784, 0xffffffff, 0x00000100,
475 	0x9698, 0xffffffff, 0x00000100,
476 	0x4d4, 0xffffffff, 0x00000200,
477 	0x30cc, 0xffffffff, 0x00000100,
478 	0xd0c0, 0xffffffff, 0xff000100,
479 	0x802c, 0xffffffff, 0x40000000,
480 	0x915c, 0xffffffff, 0x00010000,
481 	0x9160, 0xffffffff, 0x00030002,
482 	0x9178, 0xffffffff, 0x00070000,
483 	0x917c, 0xffffffff, 0x00030002,
484 	0x9180, 0xffffffff, 0x00050004,
485 	0x918c, 0xffffffff, 0x00010006,
486 	0x9190, 0xffffffff, 0x00090008,
487 	0x9194, 0xffffffff, 0x00070000,
488 	0x9198, 0xffffffff, 0x00030002,
489 	0x919c, 0xffffffff, 0x00050004,
490 	0x91a8, 0xffffffff, 0x00010006,
491 	0x91ac, 0xffffffff, 0x00090008,
492 	0x91b0, 0xffffffff, 0x00070000,
493 	0x91b4, 0xffffffff, 0x00030002,
494 	0x91b8, 0xffffffff, 0x00050004,
495 	0x91c4, 0xffffffff, 0x00010006,
496 	0x91c8, 0xffffffff, 0x00090008,
497 	0x91cc, 0xffffffff, 0x00070000,
498 	0x91d0, 0xffffffff, 0x00030002,
499 	0x91d4, 0xffffffff, 0x00050004,
500 	0x91e0, 0xffffffff, 0x00010006,
501 	0x91e4, 0xffffffff, 0x00090008,
502 	0x91e8, 0xffffffff, 0x00000000,
503 	0x91ec, 0xffffffff, 0x00070000,
504 	0x91f0, 0xffffffff, 0x00030002,
505 	0x91f4, 0xffffffff, 0x00050004,
506 	0x9200, 0xffffffff, 0x00010006,
507 	0x9204, 0xffffffff, 0x00090008,
508 	0x9294, 0xffffffff, 0x00000000,
509 	0x929c, 0xffffffff, 0x00000001,
510 	0x802c, 0xffffffff, 0xc0000000
515 	0x3f90, 0xffff0000, 0xff000000,
516 	0x9148, 0xffff0000, 0xff000000,
517 	0x3f94, 0xffff0000, 0xff000000,
518 	0x914c, 0xffff0000, 0xff000000,
519 	0x9b7c, 0xffffffff, 0x00000000,
520 	0x8a14, 0xffffffff, 0x00000007,
521 	0x8b10, 0xffffffff, 0x00000000,
522 	0x960c, 0xffffffff, 0x54763210,
523 	0x88c4, 0xffffffff, 0x000000c2,
524 	0x88d4, 0xffffffff, 0x00000000,
525 	0x8974, 0xffffffff, 0x00000000,
526 	0xc78, 0x00000080, 0x00000080,
527 	0x5eb4, 0xffffffff, 0x00000002,
528 	0x5e78, 0xffffffff, 0x001000f0,
529 	0x6104, 0x01000300, 0x00000000,
530 	0x5bc0, 0x00300000, 0x00000000,
531 	0x7030, 0xffffffff, 0x00000011,
532 	0x7c30, 0xffffffff, 0x00000011,
533 	0x10830, 0xffffffff, 0x00000011,
534 	0x11430, 0xffffffff, 0x00000011,
535 	0xd02c, 0xffffffff, 0x08421000,
536 	0x240c, 0xffffffff, 0x00000380,
537 	0x8b24, 0xffffffff, 0x00ff0fff,
538 	0x28a4c, 0x06000000, 0x06000000,
539 	0x10c, 0x00000001, 0x00000001,
540 	0x8d00, 0xffffffff, 0x100e4848,
541 	0x8d04, 0xffffffff, 0x00164745,
542 	0x8c00, 0xffffffff, 0xe4000003,
543 	0x8c04, 0xffffffff, 0x40600060,
544 	0x8c08, 0xffffffff, 0x001c001c,
545 	0x8cf0, 0xffffffff, 0x08e00410,
546 	0x8c20, 0xffffffff, 0x00800080,
547 	0x8c24, 0xffffffff, 0x00800080,
548 	0x8c18, 0xffffffff, 0x20202078,
549 	0x8c1c, 0xffffffff, 0x00001010,
550 	0x28350, 0xffffffff, 0x00000000,
551 	0xa008, 0xffffffff, 0x00010000,
552 	0x5c4, 0xffffffff, 0x00000001,
553 	0x9508, 0xffffffff, 0x00000002
558 	0x802c, 0xffffffff, 0xc0000000,
559 	0x5448, 0xffffffff, 0x00000100,
560 	0x55e4, 0xffffffff, 0x00000100,
561 	0x160c, 0xffffffff, 0x00000100,
562 	0x5644, 0xffffffff, 0x00000100,
563 	0xc164, 0xffffffff, 0x00000100,
564 	0x8a18, 0xffffffff, 0x00000100,
565 	0x897c, 0xffffffff, 0x06000100,
566 	0x8b28, 0xffffffff, 0x00000100,
567 	0x9144, 0xffffffff, 0x00000100,
568 	0x9a60, 0xffffffff, 0x00000100,
569 	0x9868, 0xffffffff, 0x00000100,
570 	0x8d58, 0xffffffff, 0x00000100,
571 	0x9510, 0xffffffff, 0x00000100,
572 	0x949c, 0xffffffff, 0x00000100,
573 	0x9654, 0xffffffff, 0x00000100,
574 	0x9030, 0xffffffff, 0x00000100,
575 	0x9034, 0xffffffff, 0x00000100,
576 	0x9038, 0xffffffff, 0x00000100,
577 	0x903c, 0xffffffff, 0x00000100,
578 	0x9040, 0xffffffff, 0x00000100,
579 	0xa200, 0xffffffff, 0x00000100,
580 	0xa204, 0xffffffff, 0x00000100,
581 	0xa208, 0xffffffff, 0x00000100,
582 	0xa20c, 0xffffffff, 0x00000100,
583 	0x971c, 0xffffffff, 0x00000100,
584 	0x977c, 0xffffffff, 0x00000100,
585 	0x3f80, 0xffffffff, 0x00000100,
586 	0xa210, 0xffffffff, 0x00000100,
587 	0xa214, 0xffffffff, 0x00000100,
588 	0x4d8, 0xffffffff, 0x00000100,
589 	0x9784, 0xffffffff, 0x00000100,
590 	0x9698, 0xffffffff, 0x00000100,
591 	0x4d4, 0xffffffff, 0x00000200,
592 	0x30cc, 0xffffffff, 0x00000100,
593 	0xd0c0, 0xffffffff, 0xff000100,
594 	0x802c, 0xffffffff, 0x40000000,
595 	0x915c, 0xffffffff, 0x00010000,
596 	0x9178, 0xffffffff, 0x00050000,
597 	0x917c, 0xffffffff, 0x00030002,
598 	0x918c, 0xffffffff, 0x00010004,
599 	0x9190, 0xffffffff, 0x00070006,
600 	0x9194, 0xffffffff, 0x00050000,
601 	0x9198, 0xffffffff, 0x00030002,
602 	0x91a8, 0xffffffff, 0x00010004,
603 	0x91ac, 0xffffffff, 0x00070006,
604 	0x91e8, 0xffffffff, 0x00000000,
605 	0x9294, 0xffffffff, 0x00000000,
606 	0x929c, 0xffffffff, 0x00000001,
607 	0x802c, 0xffffffff, 0xc0000000
612 	0x802c, 0xffffffff, 0xc0000000,
613 	0x5448, 0xffffffff, 0x00000100,
614 	0x55e4, 0xffffffff, 0x00000100,
615 	0x160c, 0xffffffff, 0x00000100,
616 	0x5644, 0xffffffff, 0x00000100,
617 	0xc164, 0xffffffff, 0x00000100,
618 	0x8a18, 0xffffffff, 0x00000100,
619 	0x897c, 0xffffffff, 0x06000100,
620 	0x8b28, 0xffffffff, 0x00000100,
621 	0x9144, 0xffffffff, 0x00000100,
622 	0x9a60, 0xffffffff, 0x00000100,
623 	0x9868, 0xffffffff, 0x00000100,
624 	0x8d58, 0xffffffff, 0x00000100,
625 	0x9510, 0xffffffff, 0x00000100,
626 	0x949c, 0xffffffff, 0x00000100,
627 	0x9654, 0xffffffff, 0x00000100,
628 	0x9030, 0xffffffff, 0x00000100,
629 	0x9034, 0xffffffff, 0x00000100,
630 	0x9038, 0xffffffff, 0x00000100,
631 	0x903c, 0xffffffff, 0x00000100,
632 	0x9040, 0xffffffff, 0x00000100,
633 	0xa200, 0xffffffff, 0x00000100,
634 	0xa204, 0xffffffff, 0x00000100,
635 	0xa208, 0xffffffff, 0x00000100,
636 	0xa20c, 0xffffffff, 0x00000100,
637 	0x971c, 0xffffffff, 0x00000100,
638 	0xd0c0, 0xffffffff, 0xff000100,
639 	0x802c, 0xffffffff, 0x40000000,
640 	0x915c, 0xffffffff, 0x00010000,
641 	0x9160, 0xffffffff, 0x00030002,
642 	0x9178, 0xffffffff, 0x00070000,
643 	0x917c, 0xffffffff, 0x00030002,
644 	0x9180, 0xffffffff, 0x00050004,
645 	0x918c, 0xffffffff, 0x00010006,
646 	0x9190, 0xffffffff, 0x00090008,
647 	0x9194, 0xffffffff, 0x00070000,
648 	0x9198, 0xffffffff, 0x00030002,
649 	0x919c, 0xffffffff, 0x00050004,
650 	0x91a8, 0xffffffff, 0x00010006,
651 	0x91ac, 0xffffffff, 0x00090008,
652 	0x91b0, 0xffffffff, 0x00070000,
653 	0x91b4, 0xffffffff, 0x00030002,
654 	0x91b8, 0xffffffff, 0x00050004,
655 	0x91c4, 0xffffffff, 0x00010006,
656 	0x91c8, 0xffffffff, 0x00090008,
657 	0x91cc, 0xffffffff, 0x00070000,
658 	0x91d0, 0xffffffff, 0x00030002,
659 	0x91d4, 0xffffffff, 0x00050004,
660 	0x91e0, 0xffffffff, 0x00010006,
661 	0x91e4, 0xffffffff, 0x00090008,
662 	0x91e8, 0xffffffff, 0x00000000,
663 	0x91ec, 0xffffffff, 0x00070000,
664 	0x91f0, 0xffffffff, 0x00030002,
665 	0x91f4, 0xffffffff, 0x00050004,
666 	0x9200, 0xffffffff, 0x00010006,
667 	0x9204, 0xffffffff, 0x00090008,
668 	0x9208, 0xffffffff, 0x00070000,
669 	0x920c, 0xffffffff, 0x00030002,
670 	0x9210, 0xffffffff, 0x00050004,
671 	0x921c, 0xffffffff, 0x00010006,
672 	0x9220, 0xffffffff, 0x00090008,
673 	0x9224, 0xffffffff, 0x00070000,
674 	0x9228, 0xffffffff, 0x00030002,
675 	0x922c, 0xffffffff, 0x00050004,
676 	0x9238, 0xffffffff, 0x00010006,
677 	0x923c, 0xffffffff, 0x00090008,
678 	0x9240, 0xffffffff, 0x00070000,
679 	0x9244, 0xffffffff, 0x00030002,
680 	0x9248, 0xffffffff, 0x00050004,
681 	0x9254, 0xffffffff, 0x00010006,
682 	0x9258, 0xffffffff, 0x00090008,
683 	0x925c, 0xffffffff, 0x00070000,
684 	0x9260, 0xffffffff, 0x00030002,
685 	0x9264, 0xffffffff, 0x00050004,
686 	0x9270, 0xffffffff, 0x00010006,
687 	0x9274, 0xffffffff, 0x00090008,
688 	0x9278, 0xffffffff, 0x00070000,
689 	0x927c, 0xffffffff, 0x00030002,
690 	0x9280, 0xffffffff, 0x00050004,
691 	0x928c, 0xffffffff, 0x00010006,
692 	0x9290, 0xffffffff, 0x00090008,
693 	0x9294, 0xffffffff, 0x00000000,
694 	0x929c, 0xffffffff, 0x00000001,
695 	0x802c, 0xffffffff, 0xc0000000,
696 	0x977c, 0xffffffff, 0x00000100,
697 	0x3f80, 0xffffffff, 0x00000100,
698 	0xa210, 0xffffffff, 0x00000100,
699 	0xa214, 0xffffffff, 0x00000100,
700 	0x4d8, 0xffffffff, 0x00000100,
701 	0x9784, 0xffffffff, 0x00000100,
702 	0x9698, 0xffffffff, 0x00000100,
703 	0x4d4, 0xffffffff, 0x00000200,
704 	0x30cc, 0xffffffff, 0x00000100,
705 	0x802c, 0xffffffff, 0xc0000000
710 	0x5eb4, 0xffffffff, 0x00000002,
711 	0x5c4, 0xffffffff, 0x00000001,
712 	0x7030, 0xffffffff, 0x00000011,
713 	0x7c30, 0xffffffff, 0x00000011,
714 	0x6104, 0x01000300, 0x00000000,
715 	0x5bc0, 0x00300000, 0x00000000,
716 	0x8c04, 0xffffffff, 0x40600060,
717 	0x8c08, 0xffffffff, 0x001c001c,
718 	0x8c20, 0xffffffff, 0x00800080,
719 	0x8c24, 0xffffffff, 0x00800080,
720 	0x8c18, 0xffffffff, 0x20202078,
721 	0x8c1c, 0xffffffff, 0x00001010,
722 	0x918c, 0xffffffff, 0x00010006,
723 	0x91a8, 0xffffffff, 0x00010006,
724 	0x91c4, 0xffffffff, 0x00010006,
725 	0x91e0, 0xffffffff, 0x00010006,
726 	0x9200, 0xffffffff, 0x00010006,
727 	0x9150, 0xffffffff, 0x6e944040,
728 	0x917c, 0xffffffff, 0x00030002,
729 	0x9180, 0xffffffff, 0x00050004,
730 	0x9198, 0xffffffff, 0x00030002,
731 	0x919c, 0xffffffff, 0x00050004,
732 	0x91b4, 0xffffffff, 0x00030002,
733 	0x91b8, 0xffffffff, 0x00050004,
734 	0x91d0, 0xffffffff, 0x00030002,
735 	0x91d4, 0xffffffff, 0x00050004,
736 	0x91f0, 0xffffffff, 0x00030002,
737 	0x91f4, 0xffffffff, 0x00050004,
738 	0x915c, 0xffffffff, 0x00010000,
739 	0x9160, 0xffffffff, 0x00030002,
740 	0x3f90, 0xffff0000, 0xff000000,
741 	0x9178, 0xffffffff, 0x00070000,
742 	0x9194, 0xffffffff, 0x00070000,
743 	0x91b0, 0xffffffff, 0x00070000,
744 	0x91cc, 0xffffffff, 0x00070000,
745 	0x91ec, 0xffffffff, 0x00070000,
746 	0x9148, 0xffff0000, 0xff000000,
747 	0x9190, 0xffffffff, 0x00090008,
748 	0x91ac, 0xffffffff, 0x00090008,
749 	0x91c8, 0xffffffff, 0x00090008,
750 	0x91e4, 0xffffffff, 0x00090008,
751 	0x9204, 0xffffffff, 0x00090008,
752 	0x3f94, 0xffff0000, 0xff000000,
753 	0x914c, 0xffff0000, 0xff000000,
754 	0x929c, 0xffffffff, 0x00000001,
755 	0x8a18, 0xffffffff, 0x00000100,
756 	0x8b28, 0xffffffff, 0x00000100,
757 	0x9144, 0xffffffff, 0x00000100,
758 	0x5644, 0xffffffff, 0x00000100,
759 	0x9b7c, 0xffffffff, 0x00000000,
760 	0x8030, 0xffffffff, 0x0000100a,
761 	0x8a14, 0xffffffff, 0x00000007,
762 	0x8b24, 0xffffffff, 0x00ff0fff,
763 	0x8b10, 0xffffffff, 0x00000000,
764 	0x28a4c, 0x06000000, 0x06000000,
765 	0x4d8, 0xffffffff, 0x00000100,
766 	0x913c, 0xffff000f, 0x0100000a,
767 	0x960c, 0xffffffff, 0x54763210,
768 	0x88c4, 0xffffffff, 0x000000c2,
769 	0x88d4, 0xffffffff, 0x00000010,
770 	0x8974, 0xffffffff, 0x00000000,
771 	0xc78, 0x00000080, 0x00000080,
772 	0x5e78, 0xffffffff, 0x001000f0,
773 	0xd02c, 0xffffffff, 0x08421000,
774 	0xa008, 0xffffffff, 0x00010000,
775 	0x8d00, 0xffffffff, 0x100e4848,
776 	0x8d04, 0xffffffff, 0x00164745,
777 	0x8c00, 0xffffffff, 0xe4000003,
778 	0x8cf0, 0x1fffffff, 0x08e00620,
779 	0x28350, 0xffffffff, 0x00000000,
780 	0x9508, 0xffffffff, 0x00000002
785 	0x900c, 0x00ffffff, 0x0017071f,
786 	0x8c18, 0xffffffff, 0x10101060,
787 	0x8c1c, 0xffffffff, 0x00001010,
788 	0x8c30, 0x0000000f, 0x00000005,
789 	0x9688, 0x0000000f, 0x00000007
794 	0x5eb4, 0xffffffff, 0x00000002,
795 	0x5c4, 0xffffffff, 0x00000001,
796 	0x7030, 0xffffffff, 0x00000011,
797 	0x7c30, 0xffffffff, 0x00000011,
798 	0x6104, 0x01000300, 0x00000000,
799 	0x5bc0, 0x00300000, 0x00000000,
800 	0x918c, 0xffffffff, 0x00010006,
801 	0x91a8, 0xffffffff, 0x00010006,
802 	0x9150, 0xffffffff, 0x6e944040,
803 	0x917c, 0xffffffff, 0x00030002,
804 	0x9198, 0xffffffff, 0x00030002,
805 	0x915c, 0xffffffff, 0x00010000,
806 	0x3f90, 0xffff0000, 0xff000000,
807 	0x9178, 0xffffffff, 0x00070000,
808 	0x9194, 0xffffffff, 0x00070000,
809 	0x9148, 0xffff0000, 0xff000000,
810 	0x9190, 0xffffffff, 0x00090008,
811 	0x91ac, 0xffffffff, 0x00090008,
812 	0x3f94, 0xffff0000, 0xff000000,
813 	0x914c, 0xffff0000, 0xff000000,
814 	0x929c, 0xffffffff, 0x00000001,
815 	0x8a18, 0xffffffff, 0x00000100,
816 	0x8b28, 0xffffffff, 0x00000100,
817 	0x9144, 0xffffffff, 0x00000100,
818 	0x9b7c, 0xffffffff, 0x00000000,
819 	0x8030, 0xffffffff, 0x0000100a,
820 	0x8a14, 0xffffffff, 0x00000001,
821 	0x8b24, 0xffffffff, 0x00ff0fff,
822 	0x8b10, 0xffffffff, 0x00000000,
823 	0x28a4c, 0x06000000, 0x06000000,
824 	0x4d8, 0xffffffff, 0x00000100,
825 	0x913c, 0xffff000f, 0x0100000a,
826 	0x960c, 0xffffffff, 0x54763210,
827 	0x88c4, 0xffffffff, 0x000000c2,
828 	0x88d4, 0xffffffff, 0x00000010,
829 	0x8974, 0xffffffff, 0x00000000,
830 	0xc78, 0x00000080, 0x00000080,
831 	0x5e78, 0xffffffff, 0x001000f0,
832 	0xd02c, 0xffffffff, 0x08421000,
833 	0xa008, 0xffffffff, 0x00010000,
834 	0x8d00, 0xffffffff, 0x100e4848,
835 	0x8d04, 0xffffffff, 0x00164745,
836 	0x8c00, 0xffffffff, 0xe4000003,
837 	0x8cf0, 0x1fffffff, 0x08e00410,
838 	0x28350, 0xffffffff, 0x00000000,
839 	0x9508, 0xffffffff, 0x00000002,
840 	0x900c, 0xffffffff, 0x0017071f,
841 	0x8c18, 0xffffffff, 0x10101060,
842 	0x8c1c, 0xffffffff, 0x00001010
847 	0x5eb4, 0xffffffff, 0x00000002,
848 	0x5e78, 0x8f311ff1, 0x001000f0,
849 	0x3f90, 0xffff0000, 0xff000000,
850 	0x9148, 0xffff0000, 0xff000000,
851 	0x3f94, 0xffff0000, 0xff000000,
852 	0x914c, 0xffff0000, 0xff000000,
853 	0xc78, 0x00000080, 0x00000080,
854 	0xbd4, 0x70073777, 0x00010001,
855 	0xd02c, 0xbfffff1f, 0x08421000,
856 	0xd0b8, 0x03773777, 0x02011003,
857 	0x5bc0, 0x00200000, 0x50100000,
858 	0x98f8, 0x33773777, 0x02011003,
859 	0x98fc, 0xffffffff, 0x76543210,
860 	0x7030, 0x31000311, 0x00000011,
861 	0x2f48, 0x00000007, 0x02011003,
862 	0x6b28, 0x00000010, 0x00000012,
863 	0x7728, 0x00000010, 0x00000012,
864 	0x10328, 0x00000010, 0x00000012,
865 	0x10f28, 0x00000010, 0x00000012,
866 	0x11b28, 0x00000010, 0x00000012,
867 	0x12728, 0x00000010, 0x00000012,
868 	0x240c, 0x000007ff, 0x00000380,
869 	0x8a14, 0xf000001f, 0x00000007,
870 	0x8b24, 0x3fff3fff, 0x00ff0fff,
871 	0x8b10, 0x0000ff0f, 0x00000000,
872 	0x28a4c, 0x07ffffff, 0x06000000,
873 	0x10c, 0x00000001, 0x00010003,
874 	0xa02c, 0xffffffff, 0x0000009b,
875 	0x913c, 0x0000000f, 0x0100000a,
876 	0x8d00, 0xffff7f7f, 0x100e4848,
877 	0x8d04, 0x00ffffff, 0x00164745,
878 	0x8c00, 0xfffc0003, 0xe4000003,
879 	0x8c04, 0xf8ff00ff, 0x40600060,
880 	0x8c08, 0x00ff00ff, 0x001c001c,
881 	0x8cf0, 0x1fff1fff, 0x08e00620,
882 	0x8c20, 0x0fff0fff, 0x00800080,
883 	0x8c24, 0x0fff0fff, 0x00800080,
884 	0x8c18, 0xffffffff, 0x20202078,
885 	0x8c1c, 0x0000ffff, 0x00001010,
886 	0x28350, 0x00000f01, 0x00000000,
887 	0x9508, 0x3700001f, 0x00000002,
888 	0x960c, 0xffffffff, 0x54763210,
889 	0x88c4, 0x001f3ae3, 0x000000c2,
890 	0x88d4, 0x0000001f, 0x00000010,
891 	0x8974, 0xffffffff, 0x00000000
896 	0x5eb4, 0xffffffff, 0x00000002,
897 	0x5e78, 0x8f311ff1, 0x001000f0,
898 	0x8c8, 0x00003000, 0x00001070,
899 	0x8cc, 0x000fffff, 0x00040035,
900 	0x3f90, 0xffff0000, 0xfff00000,
901 	0x9148, 0xffff0000, 0xfff00000,
902 	0x3f94, 0xffff0000, 0xfff00000,
903 	0x914c, 0xffff0000, 0xfff00000,
904 	0xc78, 0x00000080, 0x00000080,
905 	0xbd4, 0x00073007, 0x00010002,
906 	0xd02c, 0xbfffff1f, 0x08421000,
907 	0xd0b8, 0x03773777, 0x02010002,
908 	0x5bc0, 0x00200000, 0x50100000,
909 	0x98f8, 0x33773777, 0x00010002,
910 	0x98fc, 0xffffffff, 0x33221100,
911 	0x7030, 0x31000311, 0x00000011,
912 	0x2f48, 0x33773777, 0x00010002,
913 	0x6b28, 0x00000010, 0x00000012,
914 	0x7728, 0x00000010, 0x00000012,
915 	0x10328, 0x00000010, 0x00000012,
916 	0x10f28, 0x00000010, 0x00000012,
917 	0x11b28, 0x00000010, 0x00000012,
918 	0x12728, 0x00000010, 0x00000012,
919 	0x240c, 0x000007ff, 0x00000380,
920 	0x8a14, 0xf000001f, 0x00000007,
921 	0x8b24, 0x3fff3fff, 0x00ff0fff,
922 	0x8b10, 0x0000ff0f, 0x00000000,
923 	0x28a4c, 0x07ffffff, 0x06000000,
924 	0x10c, 0x00000001, 0x00010003,
925 	0xa02c, 0xffffffff, 0x0000009b,
926 	0x913c, 0x0000000f, 0x0100000a,
927 	0x8d00, 0xffff7f7f, 0x100e4848,
928 	0x8d04, 0x00ffffff, 0x00164745,
929 	0x8c00, 0xfffc0003, 0xe4000003,
930 	0x8c04, 0xf8ff00ff, 0x40600060,
931 	0x8c08, 0x00ff00ff, 0x001c001c,
932 	0x8cf0, 0x1fff1fff, 0x08e00410,
933 	0x8c20, 0x0fff0fff, 0x00800080,
934 	0x8c24, 0x0fff0fff, 0x00800080,
935 	0x8c18, 0xffffffff, 0x20202078,
936 	0x8c1c, 0x0000ffff, 0x00001010,
937 	0x28350, 0x00000f01, 0x00000000,
938 	0x9508, 0x3700001f, 0x00000002,
939 	0x960c, 0xffffffff, 0x54763210,
940 	0x88c4, 0x001f3ae3, 0x000000c2,
941 	0x88d4, 0x0000001f, 0x00000010,
942 	0x8974, 0xffffffff, 0x00000000
947 	0x5eb4, 0xffffffff, 0x00000002,
948 	0x5e78, 0x8f311ff1, 0x001000f0,
949 	0x8c8, 0x00003420, 0x00001450,
950 	0x8cc, 0x000fffff, 0x00040035,
951 	0x3f90, 0xffff0000, 0xfffc0000,
952 	0x9148, 0xffff0000, 0xfffc0000,
953 	0x3f94, 0xffff0000, 0xfffc0000,
954 	0x914c, 0xffff0000, 0xfffc0000,
955 	0xc78, 0x00000080, 0x00000080,
956 	0xbd4, 0x00073007, 0x00010001,
957 	0xd02c, 0xbfffff1f, 0x08421000,
958 	0xd0b8, 0x03773777, 0x02010001,
959 	0x5bc0, 0x00200000, 0x50100000,
960 	0x98f8, 0x33773777, 0x02010001,
961 	0x98fc, 0xffffffff, 0x33221100,
962 	0x7030, 0x31000311, 0x00000011,
963 	0x2f48, 0x33773777, 0x02010001,
964 	0x6b28, 0x00000010, 0x00000012,
965 	0x7728, 0x00000010, 0x00000012,
966 	0x10328, 0x00000010, 0x00000012,
967 	0x10f28, 0x00000010, 0x00000012,
968 	0x11b28, 0x00000010, 0x00000012,
969 	0x12728, 0x00000010, 0x00000012,
970 	0x240c, 0x000007ff, 0x00000380,
971 	0x8a14, 0xf000001f, 0x00000001,
972 	0x8b24, 0x3fff3fff, 0x00ff0fff,
973 	0x8b10, 0x0000ff0f, 0x00000000,
974 	0x28a4c, 0x07ffffff, 0x06000000,
975 	0x10c, 0x00000001, 0x00010003,
976 	0xa02c, 0xffffffff, 0x0000009b,
977 	0x913c, 0x0000000f, 0x0100000a,
978 	0x8d00, 0xffff7f7f, 0x100e4848,
979 	0x8d04, 0x00ffffff, 0x00164745,
980 	0x8c00, 0xfffc0003, 0xe4000003,
981 	0x8c04, 0xf8ff00ff, 0x40600060,
982 	0x8c08, 0x00ff00ff, 0x001c001c,
983 	0x8cf0, 0x1fff1fff, 0x08e00410,
984 	0x8c20, 0x0fff0fff, 0x00800080,
985 	0x8c24, 0x0fff0fff, 0x00800080,
986 	0x8c18, 0xffffffff, 0x20202078,
987 	0x8c1c, 0x0000ffff, 0x00001010,
988 	0x28350, 0x00000f01, 0x00000000,
989 	0x9508, 0x3700001f, 0x00000002,
990 	0x960c, 0xffffffff, 0x54763210,
991 	0x88c4, 0x001f3ae3, 0x000000c2,
992 	0x88d4, 0x0000001f, 0x00000010,
993 	0x8974, 0xffffffff, 0x00000000
998 	switch (rdev->family) {  in evergreen_init_golden_registers()
1083  * evergreen_get_allowed_info_register - fetch the register for the info ioctl
1089  * Returns 0 for success or -EINVAL for an invalid register
1104 		return 0;  in evergreen_get_allowed_info_register()
1106 		return -EINVAL;  in evergreen_get_allowed_info_register()
1154 	for (i = 0; i < 100; i++) {  in sumo_set_uvd_clock()
1160 		return -ETIMEDOUT;  in sumo_set_uvd_clock()
1162 	return 0;  in sumo_set_uvd_clock()
1167 	int r = 0;  in sumo_set_uvd_clocks()
1173 	cg_scratch &= 0xffff0000;  in sumo_set_uvd_clocks()
1179 	cg_scratch &= 0x0000ffff;  in sumo_set_uvd_clocks()
1191 	unsigned fb_div = 0, vclk_div = 0, dclk_div = 0;  in evergreen_set_uvd_clocks()
1205 		return 0;  in evergreen_set_uvd_clocks()
1209 					  16384, 0x03FFFFFF, 0, 128, 5,  in evergreen_set_uvd_clocks()
1217 	/* toggle UPLL_SLEEP to 1 then back to 0 */  in evergreen_set_uvd_clocks()
1219 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);  in evergreen_set_uvd_clocks()
1222 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);  in evergreen_set_uvd_clocks()
1234 	WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);  in evergreen_set_uvd_clocks()
1239 	/* set ref divider to 0 */  in evergreen_set_uvd_clocks()
1240 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);  in evergreen_set_uvd_clocks()
1243 		WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9);  in evergreen_set_uvd_clocks()
1256 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);  in evergreen_set_uvd_clocks()
1261 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);  in evergreen_set_uvd_clocks()
1274 	return 0;  in evergreen_set_uvd_clocks()
1282 	readrq = pcie_get_readrq(rdev->pdev);  in evergreen_fix_pci_max_read_req_size()
1283 	v = ffs(readrq) - 8;  in evergreen_fix_pci_max_read_req_size()
1287 	if ((v == 0) || (v == 6) || (v == 7))  in evergreen_fix_pci_max_read_req_size()
1288 		pcie_set_readrq(rdev->pdev, 512);  in evergreen_fix_pci_max_read_req_size()
1293 	struct drm_device *dev = encoder->dev;  in dce4_program_fmt()
1294 	struct radeon_device *rdev = dev->dev_private;  in dce4_program_fmt()
1296 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);  in dce4_program_fmt()
1298 	int bpc = 0;  in dce4_program_fmt()
1299 	u32 tmp = 0;  in dce4_program_fmt()
1305 		dither = radeon_connector->dither;  in dce4_program_fmt()
1309 	if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)  in dce4_program_fmt()
1313 	if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||  in dce4_program_fmt()
1314 	    (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))  in dce4_program_fmt()
1317 	if (bpc == 0)  in dce4_program_fmt()
1344 	WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);  in dce4_program_fmt()
1369  * dce4_wait_for_vblank - vblank wait asic callback.
1378 	unsigned i = 0;  in dce4_wait_for_vblank()
1380 	if (crtc >= rdev->num_crtc)  in dce4_wait_for_vblank()
1390 		if (i++ % 100 == 0) {  in dce4_wait_for_vblank()
1397 		if (i++ % 100 == 0) {  in dce4_wait_for_vblank()
1405  * evergreen_page_flip - pageflip callback.
1418 	struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];  in evergreen_page_flip()
1419 	struct drm_framebuffer *fb = radeon_crtc->base.primary->fb;  in evergreen_page_flip()
1422 	WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset,  in evergreen_page_flip()
1423 	       async ? EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN : 0);  in evergreen_page_flip()
1425 	WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset,  in evergreen_page_flip()
1426 	       fb->pitches[0] / fb->format->cpp[0]);  in evergreen_page_flip()
1428 	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,  in evergreen_page_flip()
1430 	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,  in evergreen_page_flip()
1433 	RREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset);  in evergreen_page_flip()
1437  * evergreen_page_flip_pending - check if page flip is still pending
1446 	struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];  in evergreen_page_flip_pending()
1449 	return !!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) &  in evergreen_page_flip_pending()
1457 	int actual_temp = 0;  in evergreen_get_temp()
1459 	if (rdev->family == CHIP_JUNIPER) {  in evergreen_get_temp()
1465 		if (toffset & 0x100)  in evergreen_get_temp()
1466 			actual_temp = temp / 2 - (0x200 - toffset);  in evergreen_get_temp()
1476 		if (temp & 0x400)  in evergreen_get_temp()
1477 			actual_temp = -256;  in evergreen_get_temp()
1478 		else if (temp & 0x200)  in evergreen_get_temp()
1480 		else if (temp & 0x100) {  in evergreen_get_temp()
1481 			actual_temp = temp & 0x1ff;  in evergreen_get_temp()
1482 			actual_temp |= ~0x1ff;  in evergreen_get_temp()
1484 			actual_temp = temp & 0xff;  in evergreen_get_temp()
1494 	u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;  in sumo_get_temp()
1495 	int actual_temp = temp - 49;  in sumo_get_temp()
1501  * sumo_pm_init_profile - Initialize power profiles callback.
1514 	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;  in sumo_pm_init_profile()
1515 	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;  in sumo_pm_init_profile()
1516 	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;  in sumo_pm_init_profile()
1517 	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;  in sumo_pm_init_profile()
1520 	if (rdev->flags & RADEON_IS_MOBILITY)  in sumo_pm_init_profile()
1521 		idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);  in sumo_pm_init_profile()
1523 		idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);  in sumo_pm_init_profile()
1525 	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;  in sumo_pm_init_profile()
1526 	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;  in sumo_pm_init_profile()
1527 	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;  in sumo_pm_init_profile()
1528 	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;  in sumo_pm_init_profile()
1530 	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;  in sumo_pm_init_profile()
1531 	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;  in sumo_pm_init_profile()
1532 	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;  in sumo_pm_init_profile()
1533 	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;  in sumo_pm_init_profile()
1535 	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;  in sumo_pm_init_profile()
1536 	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;  in sumo_pm_init_profile()
1537 	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;  in sumo_pm_init_profile()
1538 	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;  in sumo_pm_init_profile()
1540 	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;  in sumo_pm_init_profile()
1541 	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;  in sumo_pm_init_profile()
1542 	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;  in sumo_pm_init_profile()
1543 	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;  in sumo_pm_init_profile()
1546 	idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);  in sumo_pm_init_profile()
1547 	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;  in sumo_pm_init_profile()
1548 	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;  in sumo_pm_init_profile()
1549 	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;  in sumo_pm_init_profile()
1550 	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx =  in sumo_pm_init_profile()
1551 		rdev->pm.power_state[idx].num_clock_modes - 1;  in sumo_pm_init_profile()
1553 	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;  in sumo_pm_init_profile()
1554 	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;  in sumo_pm_init_profile()
1555 	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;  in sumo_pm_init_profile()
1556 	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx =  in sumo_pm_init_profile()
1557 		rdev->pm.power_state[idx].num_clock_modes - 1;  in sumo_pm_init_profile()
1561  * btc_pm_init_profile - Initialize power profiles callback.
1574 	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;  in btc_pm_init_profile()
1575 	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;  in btc_pm_init_profile()
1576 	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;  in btc_pm_init_profile()
1577 	rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;  in btc_pm_init_profile()
1582 	if (rdev->flags & RADEON_IS_MOBILITY)  in btc_pm_init_profile()
1583 		idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);  in btc_pm_init_profile()
1585 		idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);  in btc_pm_init_profile()
1587 	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;  in btc_pm_init_profile()
1588 	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;  in btc_pm_init_profile()
1589 	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;  in btc_pm_init_profile()
1590 	rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;  in btc_pm_init_profile()
1592 	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;  in btc_pm_init_profile()
1593 	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;  in btc_pm_init_profile()
1594 	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;  in btc_pm_init_profile()
1595 	rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;  in btc_pm_init_profile()
1597 	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;  in btc_pm_init_profile()
1598 	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;  in btc_pm_init_profile()
1599 	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;  in btc_pm_init_profile()
1600 	rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;  in btc_pm_init_profile()
1602 	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;  in btc_pm_init_profile()
1603 	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;  in btc_pm_init_profile()
1604 	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;  in btc_pm_init_profile()
1605 	rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;  in btc_pm_init_profile()
1607 	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;  in btc_pm_init_profile()
1608 	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;  in btc_pm_init_profile()
1609 	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;  in btc_pm_init_profile()
1610 	rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;  in btc_pm_init_profile()
1612 	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;  in btc_pm_init_profile()
1613 	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;  in btc_pm_init_profile()
1614 	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;  in btc_pm_init_profile()
1615 	rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;  in btc_pm_init_profile()
1619  * evergreen_pm_misc - set additional pm hw parameters callback.
1623  * Set non-clock parameters associated with a power state
1628 	int req_ps_idx = rdev->pm.requested_power_state_index;  in evergreen_pm_misc()
1629 	int req_cm_idx = rdev->pm.requested_clock_mode_index;  in evergreen_pm_misc()
1630 	struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];  in evergreen_pm_misc()
1631 	struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;  in evergreen_pm_misc()
1633 	if (voltage->type == VOLTAGE_SW) {  in evergreen_pm_misc()
1634 		/* 0xff0x are flags rather then an actual voltage */  in evergreen_pm_misc()
1635 		if ((voltage->voltage & 0xff00) == 0xff00)  in evergreen_pm_misc()
1637 		if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {  in evergreen_pm_misc()
1638 			radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);  in evergreen_pm_misc()
1639 			rdev->pm.current_vddc = voltage->voltage;  in evergreen_pm_misc()
1640 			DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);  in evergreen_pm_misc()
1647 		if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&  in evergreen_pm_misc()
1648 		    (rdev->family >= CHIP_BARTS) &&  in evergreen_pm_misc()
1649 		    rdev->pm.active_crtc_count &&  in evergreen_pm_misc()
1650 		    ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||  in evergreen_pm_misc()
1651 		     (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))  in evergreen_pm_misc()
1652 			voltage = &rdev->pm.power_state[req_ps_idx].  in evergreen_pm_misc()
1653 				clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].voltage;  in evergreen_pm_misc()
1655 		/* 0xff0x are flags rather then an actual voltage */  in evergreen_pm_misc()
1656 		if ((voltage->vddci & 0xff00) == 0xff00)  in evergreen_pm_misc()
1658 		if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {  in evergreen_pm_misc()
1659 			radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);  in evergreen_pm_misc()
1660 			rdev->pm.current_vddci = voltage->vddci;  in evergreen_pm_misc()
1661 			DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci);  in evergreen_pm_misc()
1667  * evergreen_pm_prepare - pre-power state change callback.
1675 	struct drm_device *ddev = rdev->ddev;  in evergreen_pm_prepare()
1681 	list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {  in evergreen_pm_prepare()
1683 		if (radeon_crtc->enabled) {  in evergreen_pm_prepare()
1684 			tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);  in evergreen_pm_prepare()
1686 			WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);  in evergreen_pm_prepare()
1692  * evergreen_pm_finish - post-power state change callback.
1700 	struct drm_device *ddev = rdev->ddev;  in evergreen_pm_finish()
1706 	list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {  in evergreen_pm_finish()
1708 		if (radeon_crtc->enabled) {  in evergreen_pm_finish()
1709 			tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);  in evergreen_pm_finish()
1711 			WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);  in evergreen_pm_finish()
1717  * evergreen_hpd_sense - hpd sense callback.
1734  * evergreen_hpd_set_polarity - hpd set polarity callback.
1756  * evergreen_hpd_init - hpd setup callback.
1765 	struct drm_device *dev = rdev->ddev;  in evergreen_hpd_init()
1767 	unsigned enabled = 0;  in evergreen_hpd_init()
1768 	u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |  in evergreen_hpd_init()
1769 		DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;  in evergreen_hpd_init()
1771 	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {  in evergreen_hpd_init()
1773 			to_radeon_connector(connector)->hpd.hpd;  in evergreen_hpd_init()
1775 		if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||  in evergreen_hpd_init()
1776 		    connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {  in evergreen_hpd_init()
1797  * evergreen_hpd_fini - hpd tear down callback.
1806 	struct drm_device *dev = rdev->ddev;  in evergreen_hpd_fini()
1808 	unsigned disabled = 0;  in evergreen_hpd_fini()
1810 	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {  in evergreen_hpd_fini()
1812 			to_radeon_connector(connector)->hpd.hpd;  in evergreen_hpd_fini()
1817 		WREG32(DC_HPDx_CONTROL(hpd), 0);  in evergreen_hpd_fini()
1831 	u32 pipe_offset = radeon_crtc->crtc_id * 0x20;  in evergreen_line_buffer_adjust()
1837 	 * preset allocations specified in bits 2:0:  in evergreen_line_buffer_adjust()
1839 	 *  0 - first half of lb (3840 * 2)  in evergreen_line_buffer_adjust()
1840 	 *  1 - first 3/4 of lb (5760 * 2)  in evergreen_line_buffer_adjust()
1841 	 *  2 - whole lb (7680 * 2), other crtc must be disabled  in evergreen_line_buffer_adjust()
1842 	 *  3 - first 1/4 of lb (1920 * 2)  in evergreen_line_buffer_adjust()
1844 	 *  4 - second half of lb (3840 * 2)  in evergreen_line_buffer_adjust()
1845 	 *  5 - second 3/4 of lb (5760 * 2)  in evergreen_line_buffer_adjust()
1846 	 *  6 - whole lb (7680 * 2), other crtc must be disabled  in evergreen_line_buffer_adjust()
1847 	 *  7 - last 1/4 of lb (1920 * 2)  in evergreen_line_buffer_adjust()
1851 	 * non-linked crtcs for maximum line buffer allocation.  in evergreen_line_buffer_adjust()
1853 	if (radeon_crtc->base.enabled && mode) {  in evergreen_line_buffer_adjust()
1855 			tmp = 0; /* 1/2 */  in evergreen_line_buffer_adjust()
1862 		tmp = 0;  in evergreen_line_buffer_adjust()
1863 		buffer_alloc = 0;  in evergreen_line_buffer_adjust()
1867 	if (radeon_crtc->crtc_id % 2)  in evergreen_line_buffer_adjust()
1869 	WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);  in evergreen_line_buffer_adjust()
1874 		for (i = 0; i < rdev->usec_timeout; i++) {  in evergreen_line_buffer_adjust()
1882 	if (radeon_crtc->base.enabled && mode) {  in evergreen_line_buffer_adjust()
1884 		case 0:  in evergreen_line_buffer_adjust()
1913 	return 0;  in evergreen_line_buffer_adjust()
1921 	case 0:  in evergreen_get_number_of_dram_channels()
1957 	yclk.full = dfixed_const(wm->yclk);  in evergreen_dram_bandwidth()
1959 	dram_channels.full = dfixed_const(wm->dram_channels * 4);  in evergreen_dram_bandwidth()
1977 	yclk.full = dfixed_const(wm->yclk);  in evergreen_dram_bandwidth_for_display()
1979 	dram_channels.full = dfixed_const(wm->dram_channels * 4);  in evergreen_dram_bandwidth_for_display()
1997 	sclk.full = dfixed_const(wm->sclk);  in evergreen_data_return_bandwidth()
2017 	disp_clk.full = dfixed_const(wm->disp_clk);  in evergreen_dmif_request_bandwidth()
2052 	line_time.full = dfixed_const(wm->active_time + wm->blank_time);  in evergreen_average_bandwidth()
2054 	bpp.full = dfixed_const(wm->bytes_per_pixel);  in evergreen_average_bandwidth()
2055 	src_width.full = dfixed_const(wm->src_width);  in evergreen_average_bandwidth()
2057 	bandwidth.full = dfixed_mul(bandwidth, wm->vsc);  in evergreen_average_bandwidth()
2070 	u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */  in evergreen_latency_watermark()
2071 	u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +  in evergreen_latency_watermark()
2072 		(wm->num_heads * cursor_line_pair_return_time);  in evergreen_latency_watermark()
2077 	if (wm->num_heads == 0)  in evergreen_latency_watermark()
2078 		return 0;  in evergreen_latency_watermark()
2082 	if ((wm->vsc.full > a.full) ||  in evergreen_latency_watermark()
2083 	    ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||  in evergreen_latency_watermark()
2084 	    (wm->vtaps >= 5) ||  in evergreen_latency_watermark()
2085 	    ((wm->vsc.full >= a.full) && wm->interlaced))  in evergreen_latency_watermark()
2091 	b.full = dfixed_const(wm->num_heads);  in evergreen_latency_watermark()
2094 	lb_fill_bw = min(dfixed_trunc(a), wm->disp_clk * wm->bytes_per_pixel / 1000);  in evergreen_latency_watermark()
2096 	a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);  in evergreen_latency_watermark()
2103 	if (line_fill_time < wm->active_time)  in evergreen_latency_watermark()
2106 		return latency + (line_fill_time - wm->active_time);  in evergreen_latency_watermark()
2113 	    (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))  in evergreen_average_bandwidth_vs_dram_bandwidth_for_display()
2122 	    (evergreen_available_bandwidth(wm) / wm->num_heads))  in evergreen_average_bandwidth_vs_available_bandwidth()
2130 	u32 lb_partitions = wm->lb_size / wm->src_width;  in evergreen_check_latency_hiding()
2131 	u32 line_time = wm->active_time + wm->blank_time;  in evergreen_check_latency_hiding()
2137 	if (wm->vsc.full > a.full)  in evergreen_check_latency_hiding()
2140 		if (lb_partitions <= (wm->vtaps + 1))  in evergreen_check_latency_hiding()
2146 	latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);  in evergreen_check_latency_hiding()
2158 	struct drm_display_mode *mode = &radeon_crtc->base.mode;  in evergreen_program_watermarks()
2162 	u32 line_time = 0;  in evergreen_program_watermarks()
2163 	u32 latency_watermark_a = 0, latency_watermark_b = 0;  in evergreen_program_watermarks()
2164 	u32 priority_a_mark = 0, priority_b_mark = 0;  in evergreen_program_watermarks()
2167 	u32 pipe_offset = radeon_crtc->crtc_id * 16;  in evergreen_program_watermarks()
2171 	if (radeon_crtc->base.enabled && num_heads && mode) {  in evergreen_program_watermarks()
2172 		active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,  in evergreen_program_watermarks()
2173 					    (u32)mode->clock);  in evergreen_program_watermarks()
2174 		line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,  in evergreen_program_watermarks()
2175 					  (u32)mode->clock);  in evergreen_program_watermarks()
2177 		priority_a_cnt = 0;  in evergreen_program_watermarks()
2178 		priority_b_cnt = 0;  in evergreen_program_watermarks()
2182 		if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {  in evergreen_program_watermarks()
2188 			wm_high.yclk = rdev->pm.current_mclk * 10;  in evergreen_program_watermarks()
2189 			wm_high.sclk = rdev->pm.current_sclk * 10;  in evergreen_program_watermarks()
2192 		wm_high.disp_clk = mode->clock;  in evergreen_program_watermarks()
2193 		wm_high.src_width = mode->crtc_hdisplay;  in evergreen_program_watermarks()
2195 		wm_high.blank_time = line_time - wm_high.active_time;  in evergreen_program_watermarks()
2197 		if (mode->flags & DRM_MODE_FLAG_INTERLACE)  in evergreen_program_watermarks()
2199 		wm_high.vsc = radeon_crtc->vsc;  in evergreen_program_watermarks()
2201 		if (radeon_crtc->rmx_type != RMX_OFF)  in evergreen_program_watermarks()
2209 		if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {  in evergreen_program_watermarks()
2215 			wm_low.yclk = rdev->pm.current_mclk * 10;  in evergreen_program_watermarks()
2216 			wm_low.sclk = rdev->pm.current_sclk * 10;  in evergreen_program_watermarks()
2219 		wm_low.disp_clk = mode->clock;  in evergreen_program_watermarks()
2220 		wm_low.src_width = mode->crtc_hdisplay;  in evergreen_program_watermarks()
2222 		wm_low.blank_time = line_time - wm_low.active_time;  in evergreen_program_watermarks()
2224 		if (mode->flags & DRM_MODE_FLAG_INTERLACE)  in evergreen_program_watermarks()
2226 		wm_low.vsc = radeon_crtc->vsc;  in evergreen_program_watermarks()
2228 		if (radeon_crtc->rmx_type != RMX_OFF)  in evergreen_program_watermarks()
2245 		    (rdev->disp_priority == 2)) {  in evergreen_program_watermarks()
2252 		    (rdev->disp_priority == 2)) {  in evergreen_program_watermarks()
2258 		b.full = dfixed_const(mode->clock);  in evergreen_program_watermarks()
2262 		c.full = dfixed_mul(c, radeon_crtc->hsc);  in evergreen_program_watermarks()
2270 		b.full = dfixed_const(mode->clock);  in evergreen_program_watermarks()
2274 		c.full = dfixed_mul(c, radeon_crtc->hsc);  in evergreen_program_watermarks()
2282 		radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);  in evergreen_program_watermarks()
2306 	WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);  in evergreen_program_watermarks()
2307 	WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);  in evergreen_program_watermarks()
2310 	radeon_crtc->line_time = line_time;  in evergreen_program_watermarks()
2311 	radeon_crtc->wm_high = latency_watermark_a;  in evergreen_program_watermarks()
2312 	radeon_crtc->wm_low = latency_watermark_b;  in evergreen_program_watermarks()
2316  * evergreen_bandwidth_update - update display watermarks callback.
2327 	u32 num_heads = 0, lb_size;  in evergreen_bandwidth_update()
2330 	if (!rdev->mode_info.mode_config_initialized)  in evergreen_bandwidth_update()
2335 	for (i = 0; i < rdev->num_crtc; i++) {  in evergreen_bandwidth_update()
2336 		if (rdev->mode_info.crtcs[i]->base.enabled)  in evergreen_bandwidth_update()
2339 	for (i = 0; i < rdev->num_crtc; i += 2) {  in evergreen_bandwidth_update()
2340 		mode0 = &rdev->mode_info.crtcs[i]->base.mode;  in evergreen_bandwidth_update()
2341 		mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;  in evergreen_bandwidth_update()
2342 		lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);  in evergreen_bandwidth_update()
2343 		evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);  in evergreen_bandwidth_update()
2344 		lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);  in evergreen_bandwidth_update()
2345 		evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);  in evergreen_bandwidth_update()
2350  * evergreen_mc_wait_for_idle - wait for MC idle callback.
2356  * Returns 0 if the MC is idle, -1 if not.
2363 	for (i = 0; i < rdev->usec_timeout; i++) {  in evergreen_mc_wait_for_idle()
2365 		tmp = RREG32(SRBM_STATUS) & 0x1F00;  in evergreen_mc_wait_for_idle()
2367 			return 0;  in evergreen_mc_wait_for_idle()
2370 	return -1;  in evergreen_mc_wait_for_idle()
2381 	WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);  in evergreen_pcie_gart_tlb_flush()
2384 	for (i = 0; i < rdev->usec_timeout; i++) {  in evergreen_pcie_gart_tlb_flush()
2404 	if (rdev->gart.robj == NULL) {  in evergreen_pcie_gart_enable()
2405 		dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");  in evergreen_pcie_gart_enable()
2406 		return -EINVAL;  in evergreen_pcie_gart_enable()
2415 	WREG32(VM_L2_CNTL2, 0);  in evergreen_pcie_gart_enable()
2416 	WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));  in evergreen_pcie_gart_enable()
2422 	if (rdev->flags & RADEON_IS_IGP) {  in evergreen_pcie_gart_enable()
2430 		if ((rdev->family == CHIP_JUNIPER) ||  in evergreen_pcie_gart_enable()
2431 		    (rdev->family == CHIP_CYPRESS) ||  in evergreen_pcie_gart_enable()
2432 		    (rdev->family == CHIP_HEMLOCK) ||  in evergreen_pcie_gart_enable()
2433 		    (rdev->family == CHIP_BARTS))  in evergreen_pcie_gart_enable()
2440 	WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);  in evergreen_pcie_gart_enable()
2441 	WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);  in evergreen_pcie_gart_enable()
2442 	WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);  in evergreen_pcie_gart_enable()
2443 	WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |  in evergreen_pcie_gart_enable()
2446 			(u32)(rdev->dummy_page.addr >> 12));  in evergreen_pcie_gart_enable()
2447 	WREG32(VM_CONTEXT1_CNTL, 0);  in evergreen_pcie_gart_enable()
2450 	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",  in evergreen_pcie_gart_enable()
2451 		 (unsigned)(rdev->mc.gtt_size >> 20),  in evergreen_pcie_gart_enable()
2452 		 (unsigned long long)rdev->gart.table_addr);  in evergreen_pcie_gart_enable()
2453 	rdev->gart.ready = true;  in evergreen_pcie_gart_enable()
2454 	return 0;  in evergreen_pcie_gart_enable()
2462 	WREG32(VM_CONTEXT0_CNTL, 0);  in evergreen_pcie_gart_disable()
2463 	WREG32(VM_CONTEXT1_CNTL, 0);  in evergreen_pcie_gart_disable()
2468 	WREG32(VM_L2_CNTL2, 0);  in evergreen_pcie_gart_disable()
2469 	WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));  in evergreen_pcie_gart_disable()
2498 	WREG32(VM_L2_CNTL2, 0);  in evergreen_agp_enable()
2499 	WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));  in evergreen_agp_enable()
2512 	WREG32(VM_CONTEXT0_CNTL, 0);  in evergreen_agp_enable()
2513 	WREG32(VM_CONTEXT1_CNTL, 0);  in evergreen_agp_enable()
2581 	for (i = 0; i < ARRAY_SIZE(ni_dig_offsets); i++) {  in evergreen_is_dp_sst_stream_enabled()
2595 		for (i = 0; i < ARRAY_SIZE(ni_dig_offsets); i++) {  in evergreen_is_dp_sst_stream_enabled()
2631 	unsigned counter = 0;  in evergreen_blank_dp_output()
2673 		save->vga_render_control = RREG32(VGA_RENDER_CONTROL);  in evergreen_mc_stop()
2674 		save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);  in evergreen_mc_stop()
2677 		WREG32(VGA_RENDER_CONTROL, 0);  in evergreen_mc_stop()
2680 	for (i = 0; i < rdev->num_crtc; i++) {  in evergreen_mc_stop()
2683 			save->crtc_enabled[i] = true;  in evergreen_mc_stop()
2691 					WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);  in evergreen_mc_stop()
2700 					WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);  in evergreen_mc_stop()
2705 			for (j = 0; j < rdev->usec_timeout; j++) {  in evergreen_mc_stop()
2726 			WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);  in evergreen_mc_stop()
2727 			save->crtc_enabled[i] = false;  in evergreen_mc_stop()
2730 			save->crtc_enabled[i] = false;  in evergreen_mc_stop()
2739 		WREG32(BIF_FB_EN, 0);  in evergreen_mc_stop()
2748 	for (i = 0; i < rdev->num_crtc; i++) {  in evergreen_mc_stop()
2749 		if (save->crtc_enabled[i]) {  in evergreen_mc_stop()
2770 	for (i = 0; i < rdev->num_crtc; i++) {  in evergreen_mc_resume()
2772 		       upper_32_bits(rdev->mc.vram_start));  in evergreen_mc_resume()
2774 		       upper_32_bits(rdev->mc.vram_start));  in evergreen_mc_resume()
2776 		       (u32)rdev->mc.vram_start);  in evergreen_mc_resume()
2778 		       (u32)rdev->mc.vram_start);  in evergreen_mc_resume()
2782 		WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));  in evergreen_mc_resume()
2783 		WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);  in evergreen_mc_resume()
2787 	for (i = 0; i < rdev->num_crtc; i++) {  in evergreen_mc_resume()
2788 		if (save->crtc_enabled[i]) {  in evergreen_mc_resume()
2790 			if ((tmp & 0x7) != 0) {  in evergreen_mc_resume()
2791 				tmp &= ~0x7;  in evergreen_mc_resume()
2804 			for (j = 0; j < rdev->usec_timeout; j++) {  in evergreen_mc_resume()
2806 				if ((tmp & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING) == 0)  in evergreen_mc_resume()
2820 	for (i = 0; i < rdev->num_crtc; i++) {  in evergreen_mc_resume()
2821 		if (save->crtc_enabled[i]) {  in evergreen_mc_resume()
2827 				WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);  in evergreen_mc_resume()
2833 				WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);  in evergreen_mc_resume()
2837 			for (j = 0; j < rdev->usec_timeout; j++) {  in evergreen_mc_resume()
2846 		WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);  in evergreen_mc_resume()
2848 		WREG32(VGA_RENDER_CONTROL, save->vga_render_control);  in evergreen_mc_resume()
2859 	for (i = 0, j = 0; i < 32; i++, j += 0x18) {  in evergreen_mc_program()
2860 		WREG32((0x2c14 + j), 0x00000000);  in evergreen_mc_program()
2861 		WREG32((0x2c18 + j), 0x00000000);  in evergreen_mc_program()
2862 		WREG32((0x2c1c + j), 0x00000000);  in evergreen_mc_program()
2863 		WREG32((0x2c20 + j), 0x00000000);  in evergreen_mc_program()
2864 		WREG32((0x2c24 + j), 0x00000000);  in evergreen_mc_program()
2866 	WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);  in evergreen_mc_program()
2870 		dev_warn(rdev->dev, "Wait for MC idle timedout !\n");  in evergreen_mc_program()
2875 	if (rdev->flags & RADEON_IS_AGP) {  in evergreen_mc_program()
2876 		if (rdev->mc.vram_start < rdev->mc.gtt_start) {  in evergreen_mc_program()
2879 				rdev->mc.vram_start >> 12);  in evergreen_mc_program()
2881 				rdev->mc.gtt_end >> 12);  in evergreen_mc_program()
2885 				rdev->mc.gtt_start >> 12);  in evergreen_mc_program()
2887 				rdev->mc.vram_end >> 12);  in evergreen_mc_program()
2891 			rdev->mc.vram_start >> 12);  in evergreen_mc_program()
2893 			rdev->mc.vram_end >> 12);  in evergreen_mc_program()
2895 	WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);  in evergreen_mc_program()
2897 	if ((rdev->family == CHIP_PALM) ||  in evergreen_mc_program()
2898 	    (rdev->family == CHIP_SUMO) ||  in evergreen_mc_program()
2899 	    (rdev->family == CHIP_SUMO2)) {  in evergreen_mc_program()
2900 		tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;  in evergreen_mc_program()
2901 		tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;  in evergreen_mc_program()
2902 		tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;  in evergreen_mc_program()
2905 	tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;  in evergreen_mc_program()
2906 	tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);  in evergreen_mc_program()
2908 	WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));  in evergreen_mc_program()
2910 	WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);  in evergreen_mc_program()
2911 	if (rdev->flags & RADEON_IS_AGP) {  in evergreen_mc_program()
2912 		WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);  in evergreen_mc_program()
2913 		WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);  in evergreen_mc_program()
2914 		WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);  in evergreen_mc_program()
2916 		WREG32(MC_VM_AGP_BASE, 0);  in evergreen_mc_program()
2917 		WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);  in evergreen_mc_program()
2918 		WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);  in evergreen_mc_program()
2921 		dev_warn(rdev->dev, "Wait for MC idle timedout !\n");  in evergreen_mc_program()
2934 	struct radeon_ring *ring = &rdev->ring[ib->ring];  in evergreen_ring_ib_execute()
2938 	radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));  in evergreen_ring_ib_execute()
2941 	if (ring->rptr_save_reg) {  in evergreen_ring_ib_execute()
2942 		next_rptr = ring->wptr + 3 + 4;  in evergreen_ring_ib_execute()
2944 		radeon_ring_write(ring, ((ring->rptr_save_reg -   in evergreen_ring_ib_execute()
2947 	} else if (rdev->wb.enabled) {  in evergreen_ring_ib_execute()
2948 		next_rptr = ring->wptr + 5 + 4;  in evergreen_ring_ib_execute()
2950 		radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);  in evergreen_ring_ib_execute()
2951 		radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));  in evergreen_ring_ib_execute()
2953 		radeon_ring_write(ring, 0);  in evergreen_ring_ib_execute()
2959 			  (2 << 0) |  in evergreen_ring_ib_execute()
2961 			  (ib->gpu_addr & 0xFFFFFFFC));  in evergreen_ring_ib_execute()
2962 	radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);  in evergreen_ring_ib_execute()
2963 	radeon_ring_write(ring, ib->length_dw);  in evergreen_ring_ib_execute()
2972 	if (!rdev->me_fw || !rdev->pfp_fw)  in evergreen_cp_load_microcode()
2973 		return -EINVAL;  in evergreen_cp_load_microcode()
2982 	fw_data = (const __be32 *)rdev->pfp_fw->data;  in evergreen_cp_load_microcode()
2983 	WREG32(CP_PFP_UCODE_ADDR, 0);  in evergreen_cp_load_microcode()
2984 	for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)  in evergreen_cp_load_microcode()
2986 	WREG32(CP_PFP_UCODE_ADDR, 0);  in evergreen_cp_load_microcode()
2988 	fw_data = (const __be32 *)rdev->me_fw->data;  in evergreen_cp_load_microcode()
2989 	WREG32(CP_ME_RAM_WADDR, 0);  in evergreen_cp_load_microcode()
2990 	for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)  in evergreen_cp_load_microcode()
2993 	WREG32(CP_PFP_UCODE_ADDR, 0);  in evergreen_cp_load_microcode()
2994 	WREG32(CP_ME_RAM_WADDR, 0);  in evergreen_cp_load_microcode()
2995 	WREG32(CP_ME_RAM_RADDR, 0);  in evergreen_cp_load_microcode()
2996 	return 0;  in evergreen_cp_load_microcode()
3001 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];  in evergreen_cp_start()
3011 	radeon_ring_write(ring, 0x1);  in evergreen_cp_start()
3012 	radeon_ring_write(ring, 0x0);  in evergreen_cp_start()
3013 	radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1);  in evergreen_cp_start()
3015 	radeon_ring_write(ring, 0);  in evergreen_cp_start()
3016 	radeon_ring_write(ring, 0);  in evergreen_cp_start()
3019 	cp_me = 0xff;  in evergreen_cp_start()
3029 	radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in evergreen_cp_start()
3032 	for (i = 0; i < evergreen_default_size; i++)  in evergreen_cp_start()
3035 	radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in evergreen_cp_start()
3039 	radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));  in evergreen_cp_start()
3040 	radeon_ring_write(ring, 0);  in evergreen_cp_start()
3043 	radeon_ring_write(ring, 0xc0026f00);  in evergreen_cp_start()
3044 	radeon_ring_write(ring, 0x00000000);  in evergreen_cp_start()
3045 	radeon_ring_write(ring, 0x00000000);  in evergreen_cp_start()
3046 	radeon_ring_write(ring, 0x00000000);  in evergreen_cp_start()
3049 	radeon_ring_write(ring, 0xc0036f00);  in evergreen_cp_start()
3050 	radeon_ring_write(ring, 0x00000bc4);  in evergreen_cp_start()
3051 	radeon_ring_write(ring, 0xffffffff);  in evergreen_cp_start()
3052 	radeon_ring_write(ring, 0xffffffff);  in evergreen_cp_start()
3053 	radeon_ring_write(ring, 0xffffffff);  in evergreen_cp_start()
3055 	radeon_ring_write(ring, 0xc0026900);  in evergreen_cp_start()
3056 	radeon_ring_write(ring, 0x00000316);  in evergreen_cp_start()
3057 	radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */  in evergreen_cp_start()
3058 	radeon_ring_write(ring, 0x00000010); /*  */  in evergreen_cp_start()
3062 	return 0;  in evergreen_cp_start()
3067 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];  in evergreen_cp_resume()
3081 	WREG32(GRBM_SOFT_RESET, 0);  in evergreen_cp_resume()
3085 	rb_bufsz = order_base_2(ring->ring_size / 8);  in evergreen_cp_resume()
3091 	WREG32(CP_SEM_WAIT_TIMER, 0x0);  in evergreen_cp_resume()
3092 	WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);  in evergreen_cp_resume()
3095 	WREG32(CP_RB_WPTR_DELAY, 0);  in evergreen_cp_resume()
3099 	WREG32(CP_RB_RPTR_WR, 0);  in evergreen_cp_resume()
3100 	ring->wptr = 0;  in evergreen_cp_resume()
3101 	WREG32(CP_RB_WPTR, ring->wptr);  in evergreen_cp_resume()
3105 	       ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));  in evergreen_cp_resume()
3106 	WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);  in evergreen_cp_resume()
3107 	WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);  in evergreen_cp_resume()
3109 	if (rdev->wb.enabled)  in evergreen_cp_resume()
3110 		WREG32(SCRATCH_UMSK, 0xff);  in evergreen_cp_resume()
3113 		WREG32(SCRATCH_UMSK, 0);  in evergreen_cp_resume()
3119 	WREG32(CP_RB_BASE, ring->gpu_addr >> 8);  in evergreen_cp_resume()
3123 	ring->ready = true;  in evergreen_cp_resume()
3126 		ring->ready = false;  in evergreen_cp_resume()
3129 	return 0;  in evergreen_cp_resume()
3156 	switch (rdev->family) {  in evergreen_gpu_init()
3159 		rdev->config.evergreen.num_ses = 2;  in evergreen_gpu_init()
3160 		rdev->config.evergreen.max_pipes = 4;  in evergreen_gpu_init()
3161 		rdev->config.evergreen.max_tile_pipes = 8;  in evergreen_gpu_init()
3162 		rdev->config.evergreen.max_simds = 10;  in evergreen_gpu_init()
3163 		rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;  in evergreen_gpu_init()
3164 		rdev->config.evergreen.max_gprs = 256;  in evergreen_gpu_init()
3165 		rdev->config.evergreen.max_threads = 248;  in evergreen_gpu_init()
3166 		rdev->config.evergreen.max_gs_threads = 32;  in evergreen_gpu_init()
3167 		rdev->config.evergreen.max_stack_entries = 512;  in evergreen_gpu_init()
3168 		rdev->config.evergreen.sx_num_of_sets = 4;  in evergreen_gpu_init()
3169 		rdev->config.evergreen.sx_max_export_size = 256;  in evergreen_gpu_init()
3170 		rdev->config.evergreen.sx_max_export_pos_size = 64;  in evergreen_gpu_init()
3171 		rdev->config.evergreen.sx_max_export_smx_size = 192;  in evergreen_gpu_init()
3172 		rdev->config.evergreen.max_hw_contexts = 8;  in evergreen_gpu_init()
3173 		rdev->config.evergreen.sq_num_cf_insts = 2;  in evergreen_gpu_init()
3175 		rdev->config.evergreen.sc_prim_fifo_size = 0x100;  in evergreen_gpu_init()
3176 		rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;  in evergreen_gpu_init()
3177 		rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;  in evergreen_gpu_init()
3181 		rdev->config.evergreen.num_ses = 1;  in evergreen_gpu_init()
3182 		rdev->config.evergreen.max_pipes = 4;  in evergreen_gpu_init()
3183 		rdev->config.evergreen.max_tile_pipes = 4;  in evergreen_gpu_init()
3184 		rdev->config.evergreen.max_simds = 10;  in evergreen_gpu_init()
3185 		rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;  in evergreen_gpu_init()
3186 		rdev->config.evergreen.max_gprs = 256;  in evergreen_gpu_init()
3187 		rdev->config.evergreen.max_threads = 248;  in evergreen_gpu_init()
3188 		rdev->config.evergreen.max_gs_threads = 32;  in evergreen_gpu_init()
3189 		rdev->config.evergreen.max_stack_entries = 512;  in evergreen_gpu_init()
3190 		rdev->config.evergreen.sx_num_of_sets = 4;  in evergreen_gpu_init()
3191 		rdev->config.evergreen.sx_max_export_size = 256;  in evergreen_gpu_init()
3192 		rdev->config.evergreen.sx_max_export_pos_size = 64;  in evergreen_gpu_init()
3193 		rdev->config.evergreen.sx_max_export_smx_size = 192;  in evergreen_gpu_init()
3194 		rdev->config.evergreen.max_hw_contexts = 8;  in evergreen_gpu_init()
3195 		rdev->config.evergreen.sq_num_cf_insts = 2;  in evergreen_gpu_init()
3197 		rdev->config.evergreen.sc_prim_fifo_size = 0x100;  in evergreen_gpu_init()
3198 		rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;  in evergreen_gpu_init()
3199 		rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;  in evergreen_gpu_init()
3203 		rdev->config.evergreen.num_ses = 1;  in evergreen_gpu_init()
3204 		rdev->config.evergreen.max_pipes = 4;  in evergreen_gpu_init()
3205 		rdev->config.evergreen.max_tile_pipes = 4;  in evergreen_gpu_init()
3206 		rdev->config.evergreen.max_simds = 5;  in evergreen_gpu_init()
3207 		rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;  in evergreen_gpu_init()
3208 		rdev->config.evergreen.max_gprs = 256;  in evergreen_gpu_init()
3209 		rdev->config.evergreen.max_threads = 248;  in evergreen_gpu_init()
3210 		rdev->config.evergreen.max_gs_threads = 32;  in evergreen_gpu_init()
3211 		rdev->config.evergreen.max_stack_entries = 256;  in evergreen_gpu_init()
3212 		rdev->config.evergreen.sx_num_of_sets = 4;  in evergreen_gpu_init()
3213 		rdev->config.evergreen.sx_max_export_size = 256;  in evergreen_gpu_init()
3214 		rdev->config.evergreen.sx_max_export_pos_size = 64;  in evergreen_gpu_init()
3215 		rdev->config.evergreen.sx_max_export_smx_size = 192;  in evergreen_gpu_init()
3216 		rdev->config.evergreen.max_hw_contexts = 8;  in evergreen_gpu_init()
3217 		rdev->config.evergreen.sq_num_cf_insts = 2;  in evergreen_gpu_init()
3219 		rdev->config.evergreen.sc_prim_fifo_size = 0x100;  in evergreen_gpu_init()
3220 		rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;  in evergreen_gpu_init()
3221 		rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;  in evergreen_gpu_init()
3226 		rdev->config.evergreen.num_ses = 1;  in evergreen_gpu_init()
3227 		rdev->config.evergreen.max_pipes = 2;  in evergreen_gpu_init()
3228 		rdev->config.evergreen.max_tile_pipes = 2;  in evergreen_gpu_init()
3229 		rdev->config.evergreen.max_simds = 2;  in evergreen_gpu_init()
3230 		rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;  in evergreen_gpu_init()
3231 		rdev->config.evergreen.max_gprs = 256;  in evergreen_gpu_init()
3232 		rdev->config.evergreen.max_threads = 192;  in evergreen_gpu_init()
3233 		rdev->config.evergreen.max_gs_threads = 16;  in evergreen_gpu_init()
3234 		rdev->config.evergreen.max_stack_entries = 256;  in evergreen_gpu_init()
3235 		rdev->config.evergreen.sx_num_of_sets = 4;  in evergreen_gpu_init()
3236 		rdev->config.evergreen.sx_max_export_size = 128;  in evergreen_gpu_init()
3237 		rdev->config.evergreen.sx_max_export_pos_size = 32;  in evergreen_gpu_init()
3238 		rdev->config.evergreen.sx_max_export_smx_size = 96;  in evergreen_gpu_init()
3239 		rdev->config.evergreen.max_hw_contexts = 4;  in evergreen_gpu_init()
3240 		rdev->config.evergreen.sq_num_cf_insts = 1;  in evergreen_gpu_init()
3242 		rdev->config.evergreen.sc_prim_fifo_size = 0x40;  in evergreen_gpu_init()
3243 		rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;  in evergreen_gpu_init()
3244 		rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;  in evergreen_gpu_init()
3248 		rdev->config.evergreen.num_ses = 1;  in evergreen_gpu_init()
3249 		rdev->config.evergreen.max_pipes = 2;  in evergreen_gpu_init()
3250 		rdev->config.evergreen.max_tile_pipes = 2;  in evergreen_gpu_init()
3251 		rdev->config.evergreen.max_simds = 2;  in evergreen_gpu_init()
3252 		rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;  in evergreen_gpu_init()
3253 		rdev->config.evergreen.max_gprs = 256;  in evergreen_gpu_init()
3254 		rdev->config.evergreen.max_threads = 192;  in evergreen_gpu_init()
3255 		rdev->config.evergreen.max_gs_threads = 16;  in evergreen_gpu_init()
3256 		rdev->config.evergreen.max_stack_entries = 256;  in evergreen_gpu_init()
3257 		rdev->config.evergreen.sx_num_of_sets = 4;  in evergreen_gpu_init()
3258 		rdev->config.evergreen.sx_max_export_size = 128;  in evergreen_gpu_init()
3259 		rdev->config.evergreen.sx_max_export_pos_size = 32;  in evergreen_gpu_init()
3260 		rdev->config.evergreen.sx_max_export_smx_size = 96;  in evergreen_gpu_init()
3261 		rdev->config.evergreen.max_hw_contexts = 4;  in evergreen_gpu_init()
3262 		rdev->config.evergreen.sq_num_cf_insts = 1;  in evergreen_gpu_init()
3264 		rdev->config.evergreen.sc_prim_fifo_size = 0x40;  in evergreen_gpu_init()
3265 		rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;  in evergreen_gpu_init()
3266 		rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;  in evergreen_gpu_init()
3270 		rdev->config.evergreen.num_ses = 1;  in evergreen_gpu_init()
3271 		rdev->config.evergreen.max_pipes = 4;  in evergreen_gpu_init()
3272 		rdev->config.evergreen.max_tile_pipes = 4;  in evergreen_gpu_init()
3273 		if (rdev->pdev->device == 0x9648)  in evergreen_gpu_init()
3274 			rdev->config.evergreen.max_simds = 3;  in evergreen_gpu_init()
3275 		else if ((rdev->pdev->device == 0x9647) ||  in evergreen_gpu_init()
3276 			 (rdev->pdev->device == 0x964a))  in evergreen_gpu_init()
3277 			rdev->config.evergreen.max_simds = 4;  in evergreen_gpu_init()
3279 			rdev->config.evergreen.max_simds = 5;  in evergreen_gpu_init()
3280 		rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;  in evergreen_gpu_init()
3281 		rdev->config.evergreen.max_gprs = 256;  in evergreen_gpu_init()
3282 		rdev->config.evergreen.max_threads = 248;  in evergreen_gpu_init()
3283 		rdev->config.evergreen.max_gs_threads = 32;  in evergreen_gpu_init()
3284 		rdev->config.evergreen.max_stack_entries = 256;  in evergreen_gpu_init()
3285 		rdev->config.evergreen.sx_num_of_sets = 4;  in evergreen_gpu_init()
3286 		rdev->config.evergreen.sx_max_export_size = 256;  in evergreen_gpu_init()
3287 		rdev->config.evergreen.sx_max_export_pos_size = 64;  in evergreen_gpu_init()
3288 		rdev->config.evergreen.sx_max_export_smx_size = 192;  in evergreen_gpu_init()
3289 		rdev->config.evergreen.max_hw_contexts = 8;  in evergreen_gpu_init()
3290 		rdev->config.evergreen.sq_num_cf_insts = 2;  in evergreen_gpu_init()
3292 		rdev->config.evergreen.sc_prim_fifo_size = 0x40;  in evergreen_gpu_init()
3293 		rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;  in evergreen_gpu_init()
3294 		rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;  in evergreen_gpu_init()
3298 		rdev->config.evergreen.num_ses = 1;  in evergreen_gpu_init()
3299 		rdev->config.evergreen.max_pipes = 4;  in evergreen_gpu_init()
3300 		rdev->config.evergreen.max_tile_pipes = 4;  in evergreen_gpu_init()
3301 		rdev->config.evergreen.max_simds = 2;  in evergreen_gpu_init()
3302 		rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;  in evergreen_gpu_init()
3303 		rdev->config.evergreen.max_gprs = 256;  in evergreen_gpu_init()
3304 		rdev->config.evergreen.max_threads = 248;  in evergreen_gpu_init()
3305 		rdev->config.evergreen.max_gs_threads = 32;  in evergreen_gpu_init()
3306 		rdev->config.evergreen.max_stack_entries = 512;  in evergreen_gpu_init()
3307 		rdev->config.evergreen.sx_num_of_sets = 4;  in evergreen_gpu_init()
3308 		rdev->config.evergreen.sx_max_export_size = 256;  in evergreen_gpu_init()
3309 		rdev->config.evergreen.sx_max_export_pos_size = 64;  in evergreen_gpu_init()
3310 		rdev->config.evergreen.sx_max_export_smx_size = 192;  in evergreen_gpu_init()
3311 		rdev->config.evergreen.max_hw_contexts = 4;  in evergreen_gpu_init()
3312 		rdev->config.evergreen.sq_num_cf_insts = 2;  in evergreen_gpu_init()
3314 		rdev->config.evergreen.sc_prim_fifo_size = 0x40;  in evergreen_gpu_init()
3315 		rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;  in evergreen_gpu_init()
3316 		rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;  in evergreen_gpu_init()
3320 		rdev->config.evergreen.num_ses = 2;  in evergreen_gpu_init()
3321 		rdev->config.evergreen.max_pipes = 4;  in evergreen_gpu_init()
3322 		rdev->config.evergreen.max_tile_pipes = 8;  in evergreen_gpu_init()
3323 		rdev->config.evergreen.max_simds = 7;  in evergreen_gpu_init()
3324 		rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;  in evergreen_gpu_init()
3325 		rdev->config.evergreen.max_gprs = 256;  in evergreen_gpu_init()
3326 		rdev->config.evergreen.max_threads = 248;  in evergreen_gpu_init()
3327 		rdev->config.evergreen.max_gs_threads = 32;  in evergreen_gpu_init()
3328 		rdev->config.evergreen.max_stack_entries = 512;  in evergreen_gpu_init()
3329 		rdev->config.evergreen.sx_num_of_sets = 4;  in evergreen_gpu_init()
3330 		rdev->config.evergreen.sx_max_export_size = 256;  in evergreen_gpu_init()
3331 		rdev->config.evergreen.sx_max_export_pos_size = 64;  in evergreen_gpu_init()
3332 		rdev->config.evergreen.sx_max_export_smx_size = 192;  in evergreen_gpu_init()
3333 		rdev->config.evergreen.max_hw_contexts = 8;  in evergreen_gpu_init()
3334 		rdev->config.evergreen.sq_num_cf_insts = 2;  in evergreen_gpu_init()
3336 		rdev->config.evergreen.sc_prim_fifo_size = 0x100;  in evergreen_gpu_init()
3337 		rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;  in evergreen_gpu_init()
3338 		rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;  in evergreen_gpu_init()
3342 		rdev->config.evergreen.num_ses = 1;  in evergreen_gpu_init()
3343 		rdev->config.evergreen.max_pipes = 4;  in evergreen_gpu_init()
3344 		rdev->config.evergreen.max_tile_pipes = 4;  in evergreen_gpu_init()
3345 		rdev->config.evergreen.max_simds = 6;  in evergreen_gpu_init()
3346 		rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;  in evergreen_gpu_init()
3347 		rdev->config.evergreen.max_gprs = 256;  in evergreen_gpu_init()
3348 		rdev->config.evergreen.max_threads = 248;  in evergreen_gpu_init()
3349 		rdev->config.evergreen.max_gs_threads = 32;  in evergreen_gpu_init()
3350 		rdev->config.evergreen.max_stack_entries = 256;  in evergreen_gpu_init()
3351 		rdev->config.evergreen.sx_num_of_sets = 4;  in evergreen_gpu_init()
3352 		rdev->config.evergreen.sx_max_export_size = 256;  in evergreen_gpu_init()
3353 		rdev->config.evergreen.sx_max_export_pos_size = 64;  in evergreen_gpu_init()
3354 		rdev->config.evergreen.sx_max_export_smx_size = 192;  in evergreen_gpu_init()
3355 		rdev->config.evergreen.max_hw_contexts = 8;  in evergreen_gpu_init()
3356 		rdev->config.evergreen.sq_num_cf_insts = 2;  in evergreen_gpu_init()
3358 		rdev->config.evergreen.sc_prim_fifo_size = 0x100;  in evergreen_gpu_init()
3359 		rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;  in evergreen_gpu_init()
3360 		rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;  in evergreen_gpu_init()
3364 		rdev->config.evergreen.num_ses = 1;  in evergreen_gpu_init()
3365 		rdev->config.evergreen.max_pipes = 2;  in evergreen_gpu_init()
3366 		rdev->config.evergreen.max_tile_pipes = 2;  in evergreen_gpu_init()
3367 		rdev->config.evergreen.max_simds = 2;  in evergreen_gpu_init()
3368 		rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;  in evergreen_gpu_init()
3369 		rdev->config.evergreen.max_gprs = 256;  in evergreen_gpu_init()
3370 		rdev->config.evergreen.max_threads = 192;  in evergreen_gpu_init()
3371 		rdev->config.evergreen.max_gs_threads = 16;  in evergreen_gpu_init()
3372 		rdev->config.evergreen.max_stack_entries = 256;  in evergreen_gpu_init()
3373 		rdev->config.evergreen.sx_num_of_sets = 4;  in evergreen_gpu_init()
3374 		rdev->config.evergreen.sx_max_export_size = 128;  in evergreen_gpu_init()
3375 		rdev->config.evergreen.sx_max_export_pos_size = 32;  in evergreen_gpu_init()
3376 		rdev->config.evergreen.sx_max_export_smx_size = 96;  in evergreen_gpu_init()
3377 		rdev->config.evergreen.max_hw_contexts = 4;  in evergreen_gpu_init()
3378 		rdev->config.evergreen.sq_num_cf_insts = 1;  in evergreen_gpu_init()
3380 		rdev->config.evergreen.sc_prim_fifo_size = 0x40;  in evergreen_gpu_init()
3381 		rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;  in evergreen_gpu_init()
3382 		rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;  in evergreen_gpu_init()
3388 	for (i = 0, j = 0; i < 32; i++, j += 0x18) {  in evergreen_gpu_init()
3389 		WREG32((0x2c14 + j), 0x00000000);  in evergreen_gpu_init()
3390 		WREG32((0x2c18 + j), 0x00000000);  in evergreen_gpu_init()
3391 		WREG32((0x2c1c + j), 0x00000000);  in evergreen_gpu_init()
3392 		WREG32((0x2c20 + j), 0x00000000);  in evergreen_gpu_init()
3393 		WREG32((0x2c24 + j), 0x00000000);  in evergreen_gpu_init()
3396 	WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));  in evergreen_gpu_init()
3397 	WREG32(SRBM_INT_CNTL, 0x1);  in evergreen_gpu_init()
3398 	WREG32(SRBM_INT_ACK, 0x1);  in evergreen_gpu_init()
3403 	if ((rdev->family == CHIP_PALM) ||  in evergreen_gpu_init()
3404 	    (rdev->family == CHIP_SUMO) ||  in evergreen_gpu_init()
3405 	    (rdev->family == CHIP_SUMO2))  in evergreen_gpu_init()
3412 	 * bits 3:0   num_pipes  in evergreen_gpu_init()
3417 	rdev->config.evergreen.tile_config = 0;  in evergreen_gpu_init()
3418 	switch (rdev->config.evergreen.max_tile_pipes) {  in evergreen_gpu_init()
3421 		rdev->config.evergreen.tile_config |= (0 << 0);  in evergreen_gpu_init()
3424 		rdev->config.evergreen.tile_config |= (1 << 0);  in evergreen_gpu_init()
3427 		rdev->config.evergreen.tile_config |= (2 << 0);  in evergreen_gpu_init()
3430 		rdev->config.evergreen.tile_config |= (3 << 0);  in evergreen_gpu_init()
3433 	/* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */  in evergreen_gpu_init()
3434 	if (rdev->flags & RADEON_IS_IGP)  in evergreen_gpu_init()
3435 		rdev->config.evergreen.tile_config |= 1 << 4;  in evergreen_gpu_init()
3438 		case 0: /* four banks */  in evergreen_gpu_init()
3439 			rdev->config.evergreen.tile_config |= 0 << 4;  in evergreen_gpu_init()
3442 			rdev->config.evergreen.tile_config |= 1 << 4;  in evergreen_gpu_init()
3446 			rdev->config.evergreen.tile_config |= 2 << 4;  in evergreen_gpu_init()
3450 	rdev->config.evergreen.tile_config |= 0 << 8;  in evergreen_gpu_init()
3451 	rdev->config.evergreen.tile_config |=  in evergreen_gpu_init()
3452 		((gb_addr_config & 0x30000000) >> 28) << 12;  in evergreen_gpu_init()
3454 	if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) {  in evergreen_gpu_init()
3458 		efuse_straps_4 = RREG32_RCU(0x204);  in evergreen_gpu_init()
3459 		efuse_straps_3 = RREG32_RCU(0x203);  in evergreen_gpu_init()
3460 		tmp = (((efuse_straps_4 & 0xf) << 4) |  in evergreen_gpu_init()
3461 		      ((efuse_straps_3 & 0xf0000000) >> 28));  in evergreen_gpu_init()
3463 		tmp = 0;  in evergreen_gpu_init()
3464 		for (i = (rdev->config.evergreen.num_ses - 1); i >= 0; i--) {  in evergreen_gpu_init()
3469 			rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;  in evergreen_gpu_init()
3476 	tmp = 0;  in evergreen_gpu_init()
3477 	for (i = 0; i < rdev->config.evergreen.max_backends; i++)  in evergreen_gpu_init()
3481 		for (i = 0; i < rdev->config.evergreen.max_backends; i++)  in evergreen_gpu_init()
3485 	for (i = 0; i < rdev->config.evergreen.num_ses; i++) {  in evergreen_gpu_init()
3490 		simd_disable_bitmap = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16;  in evergreen_gpu_init()
3491 		simd_disable_bitmap |= 0xffffffff << rdev->config.evergreen.max_simds;  in evergreen_gpu_init()
3495 	rdev->config.evergreen.active_simds = hweight32(~tmp);  in evergreen_gpu_init()
3508 	if ((rdev->config.evergreen.max_backends == 1) &&  in evergreen_gpu_init()
3509 	    (rdev->flags & RADEON_IS_IGP)) {  in evergreen_gpu_init()
3512 			tmp = 0x11111111;  in evergreen_gpu_init()
3515 			tmp = 0x00000000;  in evergreen_gpu_init()
3519 		tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends,  in evergreen_gpu_init()
3522 	rdev->config.evergreen.backend_map = tmp;  in evergreen_gpu_init()
3525 	WREG32(CGTS_SYS_TCC_DISABLE, 0);  in evergreen_gpu_init()
3526 	WREG32(CGTS_TCC_DISABLE, 0);  in evergreen_gpu_init()
3527 	WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);  in evergreen_gpu_init()
3528 	WREG32(CGTS_USER_TCC_DISABLE, 0);  in evergreen_gpu_init()
3531 	WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |  in evergreen_gpu_init()
3532 				     ROQ_IB2_START(0x2b)));  in evergreen_gpu_init()
3534 	WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));  in evergreen_gpu_init()
3547 	smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);  in evergreen_gpu_init()
3548 	smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);  in evergreen_gpu_init()
3551 	if (rdev->family <= CHIP_SUMO2)  in evergreen_gpu_init()
3552 		WREG32(SMX_SAR_CTL0, 0x00010000);  in evergreen_gpu_init()
3554 …REG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) -…  in evergreen_gpu_init()
3555 					POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |  in evergreen_gpu_init()
3556 					SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));  in evergreen_gpu_init()
3558 	WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |  in evergreen_gpu_init()
3559 				 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |  in evergreen_gpu_init()
3560 				 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));  in evergreen_gpu_init()
3563 	WREG32(SPI_CONFIG_CNTL, 0);  in evergreen_gpu_init()
3565 	WREG32(CP_PERFMON_CNTL, 0);  in evergreen_gpu_init()
3567 	WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |  in evergreen_gpu_init()
3568 				  FETCH_FIFO_HIWATER(0x4) |  in evergreen_gpu_init()
3569 				  DONE_FIFO_HIWATER(0xe0) |  in evergreen_gpu_init()
3570 				  ALU_UPDATE_FIFO_HIWATER(0x8)));  in evergreen_gpu_init()
3579 		      PS_PRIO(0) |  in evergreen_gpu_init()
3584 	switch (rdev->family) {  in evergreen_gpu_init()
3599 	sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);  in evergreen_gpu_init()
3600 	sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);  in evergreen_gpu_init()
3602 	sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);  in evergreen_gpu_init()
3603 	sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);  in evergreen_gpu_init()
3604 	sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);  in evergreen_gpu_init()
3605 	sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);  in evergreen_gpu_init()
3607 	switch (rdev->family) {  in evergreen_gpu_init()
3620 …sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count)…  in evergreen_gpu_init()
3621 …sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count)…  in evergreen_gpu_init()
3622 …sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count)…  in evergreen_gpu_init()
3623 …sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count…  in evergreen_gpu_init()
3624 …sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_coun…  in evergreen_gpu_init()
3626 …sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6…  in evergreen_gpu_init()
3627 …sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / …  in evergreen_gpu_init()
3628 …sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6…  in evergreen_gpu_init()
3629 …sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / …  in evergreen_gpu_init()
3630 …sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6…  in evergreen_gpu_init()
3631 …sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / …  in evergreen_gpu_init()
3642 	WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);  in evergreen_gpu_init()
3648 	switch (rdev->family) {  in evergreen_gpu_init()
3664 	WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);  in evergreen_gpu_init()
3665 	WREG32(PA_SC_LINE_STIPPLE_STATE, 0);  in evergreen_gpu_init()
3670 	WREG32(CB_PERF_CTR0_SEL_0, 0);  in evergreen_gpu_init()
3671 	WREG32(CB_PERF_CTR0_SEL_1, 0);  in evergreen_gpu_init()
3672 	WREG32(CB_PERF_CTR1_SEL_0, 0);  in evergreen_gpu_init()
3673 	WREG32(CB_PERF_CTR1_SEL_1, 0);  in evergreen_gpu_init()
3674 	WREG32(CB_PERF_CTR2_SEL_0, 0);  in evergreen_gpu_init()
3675 	WREG32(CB_PERF_CTR2_SEL_1, 0);  in evergreen_gpu_init()
3676 	WREG32(CB_PERF_CTR3_SEL_0, 0);  in evergreen_gpu_init()
3677 	WREG32(CB_PERF_CTR3_SEL_1, 0);  in evergreen_gpu_init()
3680 	WREG32(CB_COLOR0_BASE, 0);  in evergreen_gpu_init()
3681 	WREG32(CB_COLOR1_BASE, 0);  in evergreen_gpu_init()
3682 	WREG32(CB_COLOR2_BASE, 0);  in evergreen_gpu_init()
3683 	WREG32(CB_COLOR3_BASE, 0);  in evergreen_gpu_init()
3684 	WREG32(CB_COLOR4_BASE, 0);  in evergreen_gpu_init()
3685 	WREG32(CB_COLOR5_BASE, 0);  in evergreen_gpu_init()
3686 	WREG32(CB_COLOR6_BASE, 0);  in evergreen_gpu_init()
3687 	WREG32(CB_COLOR7_BASE, 0);  in evergreen_gpu_init()
3688 	WREG32(CB_COLOR8_BASE, 0);  in evergreen_gpu_init()
3689 	WREG32(CB_COLOR9_BASE, 0);  in evergreen_gpu_init()
3690 	WREG32(CB_COLOR10_BASE, 0);  in evergreen_gpu_init()
3691 	WREG32(CB_COLOR11_BASE, 0);  in evergreen_gpu_init()
3693 	/* set the shader const cache sizes to 0 */  in evergreen_gpu_init()
3694 	for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)  in evergreen_gpu_init()
3695 		WREG32(i, 0);  in evergreen_gpu_init()
3696 	for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)  in evergreen_gpu_init()
3697 		WREG32(i, 0);  in evergreen_gpu_init()
3718 	rdev->mc.vram_is_ddr = true;  in evergreen_mc_init()
3719 	if ((rdev->family == CHIP_PALM) ||  in evergreen_mc_init()
3720 	    (rdev->family == CHIP_SUMO) ||  in evergreen_mc_init()
3721 	    (rdev->family == CHIP_SUMO2))  in evergreen_mc_init()
3734 	case 0:  in evergreen_mc_init()
3748 	rdev->mc.vram_width = numchan * chansize;  in evergreen_mc_init()
3749 	/* Could aper size report 0 ? */  in evergreen_mc_init()
3750 	rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);  in evergreen_mc_init()
3751 	rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);  in evergreen_mc_init()
3753 	if ((rdev->family == CHIP_PALM) ||  in evergreen_mc_init()
3754 	    (rdev->family == CHIP_SUMO) ||  in evergreen_mc_init()
3755 	    (rdev->family == CHIP_SUMO2)) {  in evergreen_mc_init()
3757 		rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);  in evergreen_mc_init()
3758 		rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);  in evergreen_mc_init()
3761 		rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;  in evergreen_mc_init()
3762 		rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;  in evergreen_mc_init()
3764 	rdev->mc.visible_vram_size = rdev->mc.aper_size;  in evergreen_mc_init()
3765 	r700_vram_gtt_location(rdev, &rdev->mc);  in evergreen_mc_init()
3768 	return 0;  in evergreen_mc_init()
3773 	dev_info(rdev->dev, "  GRBM_STATUS               = 0x%08X\n",  in evergreen_print_gpu_status_regs()
3775 	dev_info(rdev->dev, "  GRBM_STATUS_SE0           = 0x%08X\n",  in evergreen_print_gpu_status_regs()
3777 	dev_info(rdev->dev, "  GRBM_STATUS_SE1           = 0x%08X\n",  in evergreen_print_gpu_status_regs()
3779 	dev_info(rdev->dev, "  SRBM_STATUS               = 0x%08X\n",  in evergreen_print_gpu_status_regs()
3781 	dev_info(rdev->dev, "  SRBM_STATUS2              = 0x%08X\n",  in evergreen_print_gpu_status_regs()
3783 	dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",  in evergreen_print_gpu_status_regs()
3785 	dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",  in evergreen_print_gpu_status_regs()
3787 	dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",  in evergreen_print_gpu_status_regs()
3789 	dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",  in evergreen_print_gpu_status_regs()
3791 	dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",  in evergreen_print_gpu_status_regs()
3793 	if (rdev->family >= CHIP_CAYMAN) {  in evergreen_print_gpu_status_regs()
3794 		dev_info(rdev->dev, "  R_00D834_DMA_STATUS_REG   = 0x%08X\n",  in evergreen_print_gpu_status_regs()
3795 			 RREG32(DMA_STATUS_REG + 0x800));  in evergreen_print_gpu_status_regs()
3801 	u32 crtc_hung = 0;  in evergreen_is_display_hung()
3805 	for (i = 0; i < rdev->num_crtc; i++) {  in evergreen_is_display_hung()
3812 	for (j = 0; j < 10; j++) {  in evergreen_is_display_hung()
3813 		for (i = 0; i < rdev->num_crtc; i++) {  in evergreen_is_display_hung()
3820 		if (crtc_hung == 0)  in evergreen_is_display_hung()
3830 	u32 reset_mask = 0;  in evergreen_gpu_check_soft_reset()
3890 		DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);  in evergreen_gpu_check_soft_reset()
3900 	u32 grbm_soft_reset = 0, srbm_soft_reset = 0;  in evergreen_gpu_soft_reset()
3903 	if (reset_mask == 0)  in evergreen_gpu_soft_reset()
3906 	dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);  in evergreen_gpu_soft_reset()
3924 		dev_warn(rdev->dev, "Wait for MC idle timedout !\n");  in evergreen_gpu_soft_reset()
3969 	if (!(rdev->flags & RADEON_IS_IGP)) {  in evergreen_gpu_soft_reset()
3977 		dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);  in evergreen_gpu_soft_reset()
3991 		dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);  in evergreen_gpu_soft_reset()
4016 	dev_info(rdev->dev, "GPU pci config reset\n");  in evergreen_gpu_pci_config_reset()
4037 	pci_clear_master(rdev->pdev);  in evergreen_gpu_pci_config_reset()
4041 		dev_warn(rdev->dev, "Wait for MC idle timed out !\n");  in evergreen_gpu_pci_config_reset()
4046 	for (i = 0; i < rdev->usec_timeout; i++) {  in evergreen_gpu_pci_config_reset()
4047 		if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)  in evergreen_gpu_pci_config_reset()
4059 		return 0;  in evergreen_asic_reset()
4081 	return 0;  in evergreen_asic_reset()
4085  * evergreen_gfx_is_lockup - Check if the GFX engine is locked up
4109 #define RLC_SAVE_RESTORE_LIST_END_MARKER    0x00000000
4110 #define RLC_CLEAR_STATE_END_MARKER          0x00000001
4117 	if (rdev->rlc.save_restore_obj) {  in sumo_rlc_fini()
4118 		r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);  in sumo_rlc_fini()
4119 		if (unlikely(r != 0))  in sumo_rlc_fini()
4120 			dev_warn(rdev->dev, "(%d) reserve RLC sr bo failed\n", r);  in sumo_rlc_fini()
4121 		radeon_bo_unpin(rdev->rlc.save_restore_obj);  in sumo_rlc_fini()
4122 		radeon_bo_unreserve(rdev->rlc.save_restore_obj);  in sumo_rlc_fini()
4124 		radeon_bo_unref(&rdev->rlc.save_restore_obj);  in sumo_rlc_fini()
4125 		rdev->rlc.save_restore_obj = NULL;  in sumo_rlc_fini()
4129 	if (rdev->rlc.clear_state_obj) {  in sumo_rlc_fini()
4130 		r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);  in sumo_rlc_fini()
4131 		if (unlikely(r != 0))  in sumo_rlc_fini()
4132 			dev_warn(rdev->dev, "(%d) reserve RLC c bo failed\n", r);  in sumo_rlc_fini()
4133 		radeon_bo_unpin(rdev->rlc.clear_state_obj);  in sumo_rlc_fini()
4134 		radeon_bo_unreserve(rdev->rlc.clear_state_obj);  in sumo_rlc_fini()
4136 		radeon_bo_unref(&rdev->rlc.clear_state_obj);  in sumo_rlc_fini()
4137 		rdev->rlc.clear_state_obj = NULL;  in sumo_rlc_fini()
4141 	if (rdev->rlc.cp_table_obj) {  in sumo_rlc_fini()
4142 		r = radeon_bo_reserve(rdev->rlc.cp_table_obj, false);  in sumo_rlc_fini()
4143 		if (unlikely(r != 0))  in sumo_rlc_fini()
4144 			dev_warn(rdev->dev, "(%d) reserve RLC cp table bo failed\n", r);  in sumo_rlc_fini()
4145 		radeon_bo_unpin(rdev->rlc.cp_table_obj);  in sumo_rlc_fini()
4146 		radeon_bo_unreserve(rdev->rlc.cp_table_obj);  in sumo_rlc_fini()
4148 		radeon_bo_unref(&rdev->rlc.cp_table_obj);  in sumo_rlc_fini()
4149 		rdev->rlc.cp_table_obj = NULL;  in sumo_rlc_fini()
4160 	u32 reg_list_num, reg_list_hdr_blk_index, reg_list_blk_index = 0;  in sumo_rlc_init()
4165 	src_ptr = rdev->rlc.reg_list;  in sumo_rlc_init()
4166 	dws = rdev->rlc.reg_list_size;  in sumo_rlc_init()
4167 	if (rdev->family >= CHIP_BONAIRE) {  in sumo_rlc_init()
4170 	cs_data = rdev->rlc.cs_data;  in sumo_rlc_init()
4174 		if (rdev->rlc.save_restore_obj == NULL) {  in sumo_rlc_init()
4176 					     RADEON_GEM_DOMAIN_VRAM, 0, NULL,  in sumo_rlc_init()
4177 					     NULL, &rdev->rlc.save_restore_obj);  in sumo_rlc_init()
4179 				dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n", r);  in sumo_rlc_init()
4184 		r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);  in sumo_rlc_init()
4185 		if (unlikely(r != 0)) {  in sumo_rlc_init()
4189 		r = radeon_bo_pin(rdev->rlc.save_restore_obj, RADEON_GEM_DOMAIN_VRAM,  in sumo_rlc_init()
4190 				  &rdev->rlc.save_restore_gpu_addr);  in sumo_rlc_init()
4192 			radeon_bo_unreserve(rdev->rlc.save_restore_obj);  in sumo_rlc_init()
4193 			dev_warn(rdev->dev, "(%d) pin RLC sr bo failed\n", r);  in sumo_rlc_init()
4198 		r = radeon_bo_kmap(rdev->rlc.save_restore_obj, (void **)&rdev->rlc.sr_ptr);  in sumo_rlc_init()
4200 			dev_warn(rdev->dev, "(%d) map RLC sr bo failed\n", r);  in sumo_rlc_init()
4205 		dst_ptr = rdev->rlc.sr_ptr;  in sumo_rlc_init()
4206 		if (rdev->family >= CHIP_TAHITI) {  in sumo_rlc_init()
4208 			for (i = 0; i < rdev->rlc.reg_list_size; i++)  in sumo_rlc_init()
4217 			for (i = 0; i < dws; i++) {  in sumo_rlc_init()
4222 				j = (((i - 1) * 3) / 2);  in sumo_rlc_init()
4228 		radeon_bo_kunmap(rdev->rlc.save_restore_obj);  in sumo_rlc_init()
4229 		radeon_bo_unreserve(rdev->rlc.save_restore_obj);  in sumo_rlc_init()
4234 		if (rdev->family >= CHIP_BONAIRE) {  in sumo_rlc_init()
4235 			rdev->rlc.clear_state_size = dws = cik_get_csb_size(rdev);  in sumo_rlc_init()
4236 		} else if (rdev->family >= CHIP_TAHITI) {  in sumo_rlc_init()
4237 			rdev->rlc.clear_state_size = si_get_csb_size(rdev);  in sumo_rlc_init()
4238 			dws = rdev->rlc.clear_state_size + (256 / 4);  in sumo_rlc_init()
4240 			reg_list_num = 0;  in sumo_rlc_init()
4241 			dws = 0;  in sumo_rlc_init()
4242 			for (i = 0; cs_data[i].section != NULL; i++) {  in sumo_rlc_init()
4243 				for (j = 0; cs_data[i].section[j].extent != NULL; j++) {  in sumo_rlc_init()
4250 			rdev->rlc.clear_state_size = dws;  in sumo_rlc_init()
4253 		if (rdev->rlc.clear_state_obj == NULL) {  in sumo_rlc_init()
4255 					     RADEON_GEM_DOMAIN_VRAM, 0, NULL,  in sumo_rlc_init()
4256 					     NULL, &rdev->rlc.clear_state_obj);  in sumo_rlc_init()
4258 				dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r);  in sumo_rlc_init()
4263 		r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);  in sumo_rlc_init()
4264 		if (unlikely(r != 0)) {  in sumo_rlc_init()
4268 		r = radeon_bo_pin(rdev->rlc.clear_state_obj, RADEON_GEM_DOMAIN_VRAM,  in sumo_rlc_init()
4269 				  &rdev->rlc.clear_state_gpu_addr);  in sumo_rlc_init()
4271 			radeon_bo_unreserve(rdev->rlc.clear_state_obj);  in sumo_rlc_init()
4272 			dev_warn(rdev->dev, "(%d) pin RLC c bo failed\n", r);  in sumo_rlc_init()
4277 		r = radeon_bo_kmap(rdev->rlc.clear_state_obj, (void **)&rdev->rlc.cs_ptr);  in sumo_rlc_init()
4279 			dev_warn(rdev->dev, "(%d) map RLC c bo failed\n", r);  in sumo_rlc_init()
4284 		dst_ptr = rdev->rlc.cs_ptr;  in sumo_rlc_init()
4285 		if (rdev->family >= CHIP_BONAIRE) {  in sumo_rlc_init()
4287 		} else if (rdev->family >= CHIP_TAHITI) {  in sumo_rlc_init()
4288 			reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + 256;  in sumo_rlc_init()
4289 			dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr));  in sumo_rlc_init()
4291 			dst_ptr[2] = cpu_to_le32(rdev->rlc.clear_state_size);  in sumo_rlc_init()
4294 			reg_list_hdr_blk_index = 0;  in sumo_rlc_init()
4295 			reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + (reg_list_blk_index * 4);  in sumo_rlc_init()
4299 			for (i = 0; cs_data[i].section != NULL; i++) {  in sumo_rlc_init()
4300 				for (j = 0; cs_data[i].section[j].extent != NULL; j++) {  in sumo_rlc_init()
4302 					data = reg_list_mc_addr & 0xffffffff;  in sumo_rlc_init()
4306 					data = (cs_data[i].section[j].reg_index * 4) & 0xffffffff;  in sumo_rlc_init()
4310 					data = 0x08000000 | (reg_num * 4);  in sumo_rlc_init()
4314 					for (k = 0; k < reg_num; k++) {  in sumo_rlc_init()
4324 		radeon_bo_kunmap(rdev->rlc.clear_state_obj);  in sumo_rlc_init()
4325 		radeon_bo_unreserve(rdev->rlc.clear_state_obj);  in sumo_rlc_init()
4328 	if (rdev->rlc.cp_table_size) {  in sumo_rlc_init()
4329 		if (rdev->rlc.cp_table_obj == NULL) {  in sumo_rlc_init()
4330 			r = radeon_bo_create(rdev, rdev->rlc.cp_table_size,  in sumo_rlc_init()
4332 					     RADEON_GEM_DOMAIN_VRAM, 0, NULL,  in sumo_rlc_init()
4333 					     NULL, &rdev->rlc.cp_table_obj);  in sumo_rlc_init()
4335 				dev_warn(rdev->dev, "(%d) create RLC cp table bo failed\n", r);  in sumo_rlc_init()
4341 		r = radeon_bo_reserve(rdev->rlc.cp_table_obj, false);  in sumo_rlc_init()
4342 		if (unlikely(r != 0)) {  in sumo_rlc_init()
4343 			dev_warn(rdev->dev, "(%d) reserve RLC cp table bo failed\n", r);  in sumo_rlc_init()
4347 		r = radeon_bo_pin(rdev->rlc.cp_table_obj, RADEON_GEM_DOMAIN_VRAM,  in sumo_rlc_init()
4348 				  &rdev->rlc.cp_table_gpu_addr);  in sumo_rlc_init()
4350 			radeon_bo_unreserve(rdev->rlc.cp_table_obj);  in sumo_rlc_init()
4351 			dev_warn(rdev->dev, "(%d) pin RLC cp_table bo failed\n", r);  in sumo_rlc_init()
4355 		r = radeon_bo_kmap(rdev->rlc.cp_table_obj, (void **)&rdev->rlc.cp_table_ptr);  in sumo_rlc_init()
4357 			dev_warn(rdev->dev, "(%d) map RLC cp table bo failed\n", r);  in sumo_rlc_init()
4364 		radeon_bo_kunmap(rdev->rlc.cp_table_obj);  in sumo_rlc_init()
4365 		radeon_bo_unreserve(rdev->rlc.cp_table_obj);  in sumo_rlc_init()
4369 	return 0;  in sumo_rlc_init()
4376 	if (rdev->flags & RADEON_IS_IGP) {  in evergreen_rlc_start()
4388 	if (!rdev->rlc_fw)  in evergreen_rlc_resume()
4389 		return -EINVAL;  in evergreen_rlc_resume()
4393 	WREG32(RLC_HB_CNTL, 0);  in evergreen_rlc_resume()
4395 	if (rdev->flags & RADEON_IS_IGP) {  in evergreen_rlc_resume()
4396 		if (rdev->family == CHIP_ARUBA) {  in evergreen_rlc_resume()
4398 				3 | (3 << (16 * rdev->config.cayman.max_shader_engines));  in evergreen_rlc_resume()
4400 			u32 tmp = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16;  in evergreen_rlc_resume()
4401 			tmp |= 0xffffffff << rdev->config.cayman.max_simds_per_se;  in evergreen_rlc_resume()
4403 			if (tmp == rdev->config.cayman.max_simds_per_se) {  in evergreen_rlc_resume()
4405 				WREG32(TN_RLC_LB_PARAMS, 0x00601004);  in evergreen_rlc_resume()
4406 				WREG32(TN_RLC_LB_INIT_SIMD_MASK, 0xffffffff);  in evergreen_rlc_resume()
4407 				WREG32(TN_RLC_LB_CNTR_INIT, 0x00000000);  in evergreen_rlc_resume()
4408 				WREG32(TN_RLC_LB_CNTR_MAX, 0x00002000);  in evergreen_rlc_resume()
4411 			WREG32(RLC_HB_WPTR_LSB_ADDR, 0);  in evergreen_rlc_resume()
4412 			WREG32(RLC_HB_WPTR_MSB_ADDR, 0);  in evergreen_rlc_resume()
4414 		WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);  in evergreen_rlc_resume()
4415 		WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);  in evergreen_rlc_resume()
4417 		WREG32(RLC_HB_BASE, 0);  in evergreen_rlc_resume()
4418 		WREG32(RLC_HB_RPTR, 0);  in evergreen_rlc_resume()
4419 		WREG32(RLC_HB_WPTR, 0);  in evergreen_rlc_resume()
4420 		WREG32(RLC_HB_WPTR_LSB_ADDR, 0);  in evergreen_rlc_resume()
4421 		WREG32(RLC_HB_WPTR_MSB_ADDR, 0);  in evergreen_rlc_resume()
4423 	WREG32(RLC_MC_CNTL, 0);  in evergreen_rlc_resume()
4424 	WREG32(RLC_UCODE_CNTL, 0);  in evergreen_rlc_resume()
4426 	fw_data = (const __be32 *)rdev->rlc_fw->data;  in evergreen_rlc_resume()
4427 	if (rdev->family >= CHIP_ARUBA) {  in evergreen_rlc_resume()
4428 		for (i = 0; i < ARUBA_RLC_UCODE_SIZE; i++) {  in evergreen_rlc_resume()
4432 	} else if (rdev->family >= CHIP_CAYMAN) {  in evergreen_rlc_resume()
4433 		for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) {  in evergreen_rlc_resume()
4438 		for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {  in evergreen_rlc_resume()
4443 	WREG32(RLC_UCODE_ADDR, 0);  in evergreen_rlc_resume()
4447 	return 0;  in evergreen_rlc_resume()
4454 	if (crtc >= rdev->num_crtc)  in evergreen_get_vblank_counter()
4455 		return 0;  in evergreen_get_vblank_counter()
4465 	if (rdev->family >= CHIP_CAYMAN) {  in evergreen_disable_interrupt_state()
4466 		cayman_cp_int_cntl_setup(rdev, 0,  in evergreen_disable_interrupt_state()
4468 		cayman_cp_int_cntl_setup(rdev, 1, 0);  in evergreen_disable_interrupt_state()
4469 		cayman_cp_int_cntl_setup(rdev, 2, 0);  in evergreen_disable_interrupt_state()
4476 	WREG32(GRBM_INT_CNTL, 0);  in evergreen_disable_interrupt_state()
4477 	WREG32(SRBM_INT_CNTL, 0);  in evergreen_disable_interrupt_state()
4478 	for (i = 0; i < rdev->num_crtc; i++)  in evergreen_disable_interrupt_state()
4479 		WREG32(INT_MASK + crtc_offsets[i], 0);  in evergreen_disable_interrupt_state()
4480 	for (i = 0; i < rdev->num_crtc; i++)  in evergreen_disable_interrupt_state()
4481 		WREG32(GRPH_INT_CONTROL + crtc_offsets[i], 0);  in evergreen_disable_interrupt_state()
4485 		WREG32(DACA_AUTODETECT_INT_CONTROL, 0);  in evergreen_disable_interrupt_state()
4486 	WREG32(DACB_AUTODETECT_INT_CONTROL, 0);  in evergreen_disable_interrupt_state()
4488 	for (i = 0; i < 6; i++)  in evergreen_disable_interrupt_state()
4497 	u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;  in evergreen_irq_set()
4498 	u32 grbm_int_cntl = 0;  in evergreen_irq_set()
4499 	u32 dma_cntl, dma_cntl1 = 0;  in evergreen_irq_set()
4500 	u32 thermal_int = 0;  in evergreen_irq_set()
4502 	if (!rdev->irq.installed) {  in evergreen_irq_set()
4504 		return -EINVAL;  in evergreen_irq_set()
4507 	if (!rdev->ih.enabled) {  in evergreen_irq_set()
4511 		return 0;  in evergreen_irq_set()
4514 	if (rdev->family == CHIP_ARUBA)  in evergreen_irq_set()
4523 	if (rdev->family >= CHIP_CAYMAN) {  in evergreen_irq_set()
4525 		if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {  in evergreen_irq_set()
4529 		if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {  in evergreen_irq_set()
4533 		if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {  in evergreen_irq_set()
4538 		if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {  in evergreen_irq_set()
4545 	if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {  in evergreen_irq_set()
4550 	if (rdev->family >= CHIP_CAYMAN) {  in evergreen_irq_set()
4552 		if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) {  in evergreen_irq_set()
4558 	if (rdev->irq.dpm_thermal) {  in evergreen_irq_set()
4563 	if (rdev->family >= CHIP_CAYMAN) {  in evergreen_irq_set()
4564 		cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl);  in evergreen_irq_set()
4572 	if (rdev->family >= CHIP_CAYMAN)  in evergreen_irq_set()
4577 	for (i = 0; i < rdev->num_crtc; i++) {  in evergreen_irq_set()
4581 		    rdev->irq.crtc_vblank_int[i] ||  in evergreen_irq_set()
4582 		    atomic_read(&rdev->irq.pflip[i]), "vblank", i);  in evergreen_irq_set()
4585 	for (i = 0; i < rdev->num_crtc; i++)  in evergreen_irq_set()
4588 	for (i = 0; i < 6; i++) {  in evergreen_irq_set()
4592 		    rdev->irq.hpd[i], "HPD", i);  in evergreen_irq_set()
4595 	if (rdev->family == CHIP_ARUBA)  in evergreen_irq_set()
4600 	for (i = 0; i < 6; i++) {  in evergreen_irq_set()
4604 		    rdev->irq.afmt[i], "HDMI", i);  in evergreen_irq_set()
4610 	return 0;  in evergreen_irq_set()
4617 	u32 *grph_int = rdev->irq.stat_regs.evergreen.grph_int;  in evergreen_irq_ack()
4618 	u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int;  in evergreen_irq_ack()
4619 	u32 *afmt_status = rdev->irq.stat_regs.evergreen.afmt_status;  in evergreen_irq_ack()
4621 	for (i = 0; i < 6; i++) {  in evergreen_irq_ack()
4624 		if (i < rdev->num_crtc)  in evergreen_irq_ack()
4629 	for (i = 0; i < rdev->num_crtc; i += 2) {  in evergreen_irq_ack()
4646 	for (i = 0; i < 6; i++) {  in evergreen_irq_ack()
4651 	for (i = 0; i < 6; i++) {  in evergreen_irq_ack()
4656 	for (i = 0; i < 6; i++) {  in evergreen_irq_ack()
4682 	if (rdev->wb.enabled)  in evergreen_get_ih_wptr()
4683 		wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);  in evergreen_get_ih_wptr()
4693 		dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",  in evergreen_get_ih_wptr()
4694 			 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask);  in evergreen_get_ih_wptr()
4695 		rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;  in evergreen_get_ih_wptr()
4700 	return (wptr & rdev->ih.ptr_mask);  in evergreen_get_ih_wptr()
4705 	u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int;  in evergreen_irq_process()
4706 	u32 *afmt_status = rdev->irq.stat_regs.evergreen.afmt_status;  in evergreen_irq_process()
4720 	if (!rdev->ih.enabled || rdev->shutdown)  in evergreen_irq_process()
4727 	if (atomic_xchg(&rdev->ih.lock, 1))  in evergreen_irq_process()
4730 	rptr = rdev->ih.rptr;  in evergreen_irq_process()
4742 		src_id =  le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;  in evergreen_irq_process()
4743 		src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;  in evergreen_irq_process()
4752 			crtc_idx = src_id - 1;  in evergreen_irq_process()
4754 			if (src_data == 0) { /* vblank */  in evergreen_irq_process()
4758 				if (rdev->irq.crtc_vblank_int[crtc_idx]) {  in evergreen_irq_process()
4759 					drm_handle_vblank(rdev->ddev, crtc_idx);  in evergreen_irq_process()
4760 					rdev->pm.vblank_sync = true;  in evergreen_irq_process()
4761 					wake_up(&rdev->irq.vblank_queue);  in evergreen_irq_process()
4763 				if (atomic_read(&rdev->irq.pflip[crtc_idx])) {  in evergreen_irq_process()
4778 				DRM_DEBUG("IH: D%d %s - IH event w/o asserted irq bit?\n",  in evergreen_irq_process()
4792 			DRM_DEBUG("IH: D%d flip\n", ((src_id - 8) >> 1) + 1);  in evergreen_irq_process()
4793 			if (radeon_use_pflipirq > 0)  in evergreen_irq_process()
4794 				radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1);  in evergreen_irq_process()
4804 				hpd_idx = src_data - 6;  in evergreen_irq_process()
4837 			DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR));  in evergreen_irq_process()
4838 			WREG32(SRBM_INT_ACK, 0x1);  in evergreen_irq_process()
4841 			DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);  in evergreen_irq_process()
4850 			if (addr == 0x0 && status == 0x0)  in evergreen_irq_process()
4852 			dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);  in evergreen_irq_process()
4853 			dev_err(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",  in evergreen_irq_process()
4855 			dev_err(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",  in evergreen_irq_process()
4862 			DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);  in evergreen_irq_process()
4867 			if (rdev->family >= CHIP_CAYMAN) {  in evergreen_irq_process()
4869 				case 0:  in evergreen_irq_process()
4888 			rdev->pm.dpm.thermal.high_to_low = false;  in evergreen_irq_process()
4893 			rdev->pm.dpm.thermal.high_to_low = true;  in evergreen_irq_process()
4900 			if (rdev->family >= CHIP_CAYMAN) {  in evergreen_irq_process()
4912 		rptr &= rdev->ih.ptr_mask;  in evergreen_irq_process()
4916 		schedule_work(&rdev->dp_work);  in evergreen_irq_process()
4918 		schedule_delayed_work(&rdev->hotplug_work, 0);  in evergreen_irq_process()
4920 		schedule_work(&rdev->audio_work);  in evergreen_irq_process()
4921 	if (queue_thermal && rdev->pm.dpm_enabled)  in evergreen_irq_process()
4922 		schedule_work(&rdev->pm.dpm.thermal.work);  in evergreen_irq_process()
4923 	rdev->ih.rptr = rptr;  in evergreen_irq_process()
4924 	atomic_set(&rdev->ih.lock, 0);  in evergreen_irq_process()
4938 	if (!rdev->has_uvd)  in evergreen_uvd_init()
4943 		dev_err(rdev->dev, "failed UVD (%d) init.\n", r);  in evergreen_uvd_init()
4945 		 * At this point rdev->uvd.vcpu_bo is NULL which trickles down  in evergreen_uvd_init()
4950 		rdev->has_uvd = false;  in evergreen_uvd_init()
4953 	rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;  in evergreen_uvd_init()
4954 	r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096);  in evergreen_uvd_init()
4961 	if (!rdev->has_uvd)  in evergreen_uvd_start()
4966 		dev_err(rdev->dev, "failed UVD resume (%d).\n", r);  in evergreen_uvd_start()
4971 		dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r);  in evergreen_uvd_start()
4977 	rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;  in evergreen_uvd_start()
4985 	if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size)  in evergreen_uvd_resume()
4988 	ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];  in evergreen_uvd_resume()
4989 	r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0));  in evergreen_uvd_resume()
4991 		dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r);  in evergreen_uvd_resume()
4996 		dev_err(rdev->dev, "failed initializing UVD (%d).\n", r);  in evergreen_uvd_resume()
5018 	if (ASIC_IS_DCE5(rdev) && !rdev->pm.dpm_enabled) {  in evergreen_startup()
5026 	if (rdev->flags & RADEON_IS_AGP) {  in evergreen_startup()
5036 	if (rdev->flags & RADEON_IS_IGP) {  in evergreen_startup()
5037 		rdev->rlc.reg_list = sumo_rlc_save_restore_register_list;  in evergreen_startup()
5038 		rdev->rlc.reg_list_size =  in evergreen_startup()
5040 		rdev->rlc.cs_data = evergreen_cs_data;  in evergreen_startup()
5055 		dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);  in evergreen_startup()
5061 		dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);  in evergreen_startup()
5068 	if (!rdev->irq.installed) {  in evergreen_startup()
5082 	ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];  in evergreen_startup()
5083 	r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,  in evergreen_startup()
5088 	ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];  in evergreen_startup()
5089 	r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,  in evergreen_startup()
5090 			     DMA_PACKET(DMA_PACKET_NOP, 0, 0));  in evergreen_startup()
5108 		dev_err(rdev->dev, "IB initialization failed (%d).\n", r);  in evergreen_startup()
5118 	return 0;  in evergreen_startup()
5129 		dev_warn(rdev->dev, "GPU reset failed !\n");  in evergreen_resume()
5135 	atom_asic_init(rdev->mode_info.atom_context);  in evergreen_resume()
5140 	if (rdev->pm.pm_method == PM_METHOD_DPM)  in evergreen_resume()
5143 	rdev->accel_working = true;  in evergreen_resume()
5147 		rdev->accel_working = false;  in evergreen_resume()
5159 	if (rdev->has_uvd) {  in evergreen_suspend()
5169 	return 0;  in evergreen_suspend()
5185 			return -EINVAL;  in evergreen_init()
5188 	if (!rdev->is_atom_bios) {  in evergreen_init()
5189 		dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n");  in evergreen_init()
5190 		return -EINVAL;  in evergreen_init()
5199 		dev_warn(rdev->dev, "GPU reset failed !\n");  in evergreen_init()
5202 		if (!rdev->bios) {  in evergreen_init()
5203 			dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");  in evergreen_init()
5204 			return -EINVAL;  in evergreen_init()
5207 		atom_asic_init(rdev->mode_info.atom_context);  in evergreen_init()
5216 	radeon_get_clock_info(rdev->ddev);  in evergreen_init()
5220 	if (rdev->flags & RADEON_IS_AGP) {  in evergreen_init()
5235 		if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {  in evergreen_init()
5243 		if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {  in evergreen_init()
5255 	rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;  in evergreen_init()
5256 	r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);  in evergreen_init()
5258 	rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;  in evergreen_init()
5259 	r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);  in evergreen_init()
5263 	rdev->ih.ring_obj = NULL;  in evergreen_init()
5270 	rdev->accel_working = true;  in evergreen_init()
5273 		dev_err(rdev->dev, "disabling GPU acceleration\n");  in evergreen_init()
5277 		if (rdev->flags & RADEON_IS_IGP)  in evergreen_init()
5283 		rdev->accel_working = false;  in evergreen_init()
5291 		if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {  in evergreen_init()
5293 			return -EINVAL;  in evergreen_init()
5297 	return 0;  in evergreen_init()
5307 	if (rdev->flags & RADEON_IS_IGP)  in evergreen_fini()
5321 	kfree(rdev->bios);  in evergreen_fini()
5322 	rdev->bios = NULL;  in evergreen_fini()
5329 	if (radeon_pcie_gen2 == 0)  in evergreen_pcie_gen2_enable()
5332 	if (rdev->flags & RADEON_IS_IGP)  in evergreen_pcie_gen2_enable()
5335 	if (!(rdev->flags & RADEON_IS_PCIE))  in evergreen_pcie_gen2_enable()
5342 	if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&  in evergreen_pcie_gen2_enable()
5343 		(rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))  in evergreen_pcie_gen2_enable()
5352 	DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");  in evergreen_pcie_gen2_enable()
5379 		/* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */  in evergreen_pcie_gen2_enable()
5400 	if (radeon_aspm == 0)  in evergreen_program_aspm()
5403 	if (!(rdev->flags & RADEON_IS_PCIE))  in evergreen_program_aspm()
5406 	switch (rdev->family) {  in evergreen_program_aspm()
5423 	if (rdev->flags & RADEON_IS_IGP)  in evergreen_program_aspm()
5445 		if (rdev->family >= CHIP_BARTS)  in evergreen_program_aspm()
5452 		if (rdev->family >= CHIP_BARTS)  in evergreen_program_aspm()
5482 			if (rdev->family >= CHIP_BARTS) {  in evergreen_program_aspm()
5514 			if (rdev->family >= CHIP_BARTS) {  in evergreen_program_aspm()
5531 	if (rdev->family < CHIP_BARTS)  in evergreen_program_aspm()