Lines Matching +full:0 +full:x8c8
29 #define GENERAL_PWRMGT 0x63c
30 # define GLOBAL_PWRMGT_EN (1 << 0)
47 #define TARGET_AND_CURRENT_PROFILE_INDEX 0x66c
48 # define CURRENT_PROFILE_INDEX_MASK (0xf << 4)
51 #define CG_BIF_REQ_AND_RSP 0x7f4
52 #define CG_CLIENT_REQ(x) ((x) << 0)
53 #define CG_CLIENT_REQ_MASK (0xff << 0)
54 #define CG_CLIENT_REQ_SHIFT 0
56 #define CG_CLIENT_RESP_MASK (0xff << 8)
59 #define CLIENT_CG_REQ_MASK (0xff << 16)
62 #define CLIENT_CG_RESP_MASK (0xff << 24)
65 #define SCLK_PSKIP_CNTL 0x8c0
67 #define PSKIP_ON_ALLOW_STOP_HI_MASK (0xff << 16)
70 #define CG_ULV_CONTROL 0x8c8
71 #define CG_ULV_PARAMETER 0x8cc
73 #define MC_ARB_DRAM_TIMING 0x2774
74 #define MC_ARB_DRAM_TIMING2 0x2778
76 #define MC_ARB_RFSH_RATE 0x27b0
77 #define POWERMODE0(x) ((x) << 0)
78 #define POWERMODE0_MASK (0xff << 0)
79 #define POWERMODE0_SHIFT 0
81 #define POWERMODE1_MASK (0xff << 8)
84 #define POWERMODE2_MASK (0xff << 16)
87 #define POWERMODE3_MASK (0xff << 24)
90 #define MC_ARB_BURST_TIME 0x2808
91 #define STATE0(x) ((x) << 0)
92 #define STATE0_MASK (0x1f << 0)
93 #define STATE0_SHIFT 0
95 #define STATE1_MASK (0x1f << 5)
98 #define STATE2_MASK (0x1f << 10)
101 #define STATE3_MASK (0x1f << 15)
104 #define MC_SEQ_RAS_TIMING 0x28a0
105 #define MC_SEQ_CAS_TIMING 0x28a4
106 #define MC_SEQ_MISC_TIMING 0x28a8
107 #define MC_SEQ_MISC_TIMING2 0x28ac
109 #define MC_SEQ_RD_CTL_D0 0x28b4
110 #define MC_SEQ_RD_CTL_D1 0x28b8
111 #define MC_SEQ_WR_CTL_D0 0x28bc
112 #define MC_SEQ_WR_CTL_D1 0x28c0
114 #define MC_PMG_AUTO_CFG 0x28d4
116 #define MC_SEQ_STATUS_M 0x29f4
119 #define MC_SEQ_MISC0 0x2a00
121 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
123 #define MC_SEQ_MISC1 0x2a04
124 #define MC_SEQ_RESERVE_M 0x2a08
125 #define MC_PMG_CMD_EMRS 0x2a0c
127 #define MC_SEQ_MISC3 0x2a2c
129 #define MC_SEQ_MISC5 0x2a54
130 #define MC_SEQ_MISC6 0x2a58
132 #define MC_SEQ_MISC7 0x2a64
134 #define MC_SEQ_CG 0x2a68
135 #define CG_SEQ_REQ(x) ((x) << 0)
136 #define CG_SEQ_REQ_MASK (0xff << 0)
137 #define CG_SEQ_REQ_SHIFT 0
139 #define CG_SEQ_RESP_MASK (0xff << 8)
142 #define SEQ_CG_REQ_MASK (0xff << 16)
145 #define SEQ_CG_RESP_MASK (0xff << 24)
147 #define MC_SEQ_RAS_TIMING_LP 0x2a6c
148 #define MC_SEQ_CAS_TIMING_LP 0x2a70
149 #define MC_SEQ_MISC_TIMING_LP 0x2a74
150 #define MC_SEQ_MISC_TIMING2_LP 0x2a78
151 #define MC_SEQ_WR_CTL_D0_LP 0x2a7c
152 #define MC_SEQ_WR_CTL_D1_LP 0x2a80
153 #define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84
154 #define MC_SEQ_PMG_CMD_MRS_LP 0x2a88
156 #define MC_PMG_CMD_MRS 0x2aac
158 #define MC_SEQ_RD_CTL_D0_LP 0x2b1c
159 #define MC_SEQ_RD_CTL_D1_LP 0x2b20
161 #define MC_PMG_CMD_MRS1 0x2b44
162 #define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48
164 #define LB_SYNC_RESET_SEL 0x6b28
165 #define LB_SYNC_RESET_SEL_MASK (3 << 0)
166 #define LB_SYNC_RESET_SEL_SHIFT 0
169 #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */
170 # define LC_GEN2_EN_STRAP (1 << 0)
174 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8)
180 # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14)