Lines Matching +full:- +full:dig +full:- +full:div
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
37 #include "atom-bits.h"
43 struct drm_device *dev = crtc->dev; in atombios_overscan_setup()
44 struct radeon_device *rdev = dev->dev_private; in atombios_overscan_setup()
52 args.ucCRTC = radeon_crtc->crtc_id; in atombios_overscan_setup()
54 switch (radeon_crtc->rmx_type) { in atombios_overscan_setup()
56 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); in atombios_overscan_setup()
57 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); in atombios_overscan_setup()
58 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); in atombios_overscan_setup()
59 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); in atombios_overscan_setup()
62 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; in atombios_overscan_setup()
63 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; in atombios_overscan_setup()
66 …args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); in atombios_overscan_setup()
67 …args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2… in atombios_overscan_setup()
69 … args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); in atombios_overscan_setup()
70 …args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / … in atombios_overscan_setup()
75 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border); in atombios_overscan_setup()
76 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border); in atombios_overscan_setup()
77 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border); in atombios_overscan_setup()
78 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border); in atombios_overscan_setup()
81 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); in atombios_overscan_setup()
86 struct drm_device *dev = crtc->dev; in atombios_scaler_setup()
87 struct radeon_device *rdev = dev->dev_private; in atombios_scaler_setup()
92 to_radeon_encoder(radeon_crtc->encoder); in atombios_scaler_setup()
93 /* fixme - fill in enc_priv for atom dac */ in atombios_scaler_setup()
97 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) in atombios_scaler_setup()
100 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { in atombios_scaler_setup()
101 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; in atombios_scaler_setup()
102 tv_std = tv_dac->tv_std; in atombios_scaler_setup()
108 args.ucScaler = radeon_crtc->crtc_id; in atombios_scaler_setup()
143 switch (radeon_crtc->rmx_type) { in atombios_scaler_setup()
161 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); in atombios_scaler_setup()
163 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) { in atombios_scaler_setup()
171 struct drm_device *dev = crtc->dev; in atombios_lock_crtc()
172 struct radeon_device *rdev = dev->dev_private; in atombios_lock_crtc()
179 args.ucCRTC = radeon_crtc->crtc_id; in atombios_lock_crtc()
182 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); in atombios_lock_crtc()
188 struct drm_device *dev = crtc->dev; in atombios_enable_crtc()
189 struct radeon_device *rdev = dev->dev_private; in atombios_enable_crtc()
195 args.ucCRTC = radeon_crtc->crtc_id; in atombios_enable_crtc()
198 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); in atombios_enable_crtc()
204 struct drm_device *dev = crtc->dev; in atombios_enable_crtc_memreq()
205 struct radeon_device *rdev = dev->dev_private; in atombios_enable_crtc_memreq()
211 args.ucCRTC = radeon_crtc->crtc_id; in atombios_enable_crtc_memreq()
214 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); in atombios_enable_crtc_memreq()
230 struct drm_device *dev = crtc->dev; in atombios_blank_crtc()
231 struct radeon_device *rdev = dev->dev_private; in atombios_blank_crtc()
239 vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]); in atombios_blank_crtc()
240 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1); in atombios_blank_crtc()
243 args.ucCRTC = radeon_crtc->crtc_id; in atombios_blank_crtc()
246 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); in atombios_blank_crtc()
249 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control); in atombios_blank_crtc()
255 struct drm_device *dev = crtc->dev; in atombios_powergate_crtc()
256 struct radeon_device *rdev = dev->dev_private; in atombios_powergate_crtc()
262 args.ucDispPipeId = radeon_crtc->crtc_id; in atombios_powergate_crtc()
265 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); in atombios_powergate_crtc()
270 struct drm_device *dev = crtc->dev; in atombios_crtc_dpms()
271 struct radeon_device *rdev = dev->dev_private; in atombios_crtc_dpms()
276 radeon_crtc->enabled = true; in atombios_crtc_dpms()
281 if (dev->num_crtcs > radeon_crtc->crtc_id) in atombios_crtc_dpms()
288 if (dev->num_crtcs > radeon_crtc->crtc_id) in atombios_crtc_dpms()
290 if (radeon_crtc->enabled) in atombios_crtc_dpms()
295 radeon_crtc->enabled = false; in atombios_crtc_dpms()
307 struct drm_device *dev = crtc->dev; in atombios_set_crtc_dtd_timing()
308 struct radeon_device *rdev = dev->dev_private; in atombios_set_crtc_dtd_timing()
314 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2)); in atombios_set_crtc_dtd_timing()
316 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2)); in atombios_set_crtc_dtd_timing()
317 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2)); in atombios_set_crtc_dtd_timing()
319 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2)); in atombios_set_crtc_dtd_timing()
321 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border); in atombios_set_crtc_dtd_timing()
323 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); in atombios_set_crtc_dtd_timing()
325 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border); in atombios_set_crtc_dtd_timing()
327 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); in atombios_set_crtc_dtd_timing()
328 args.ucH_Border = radeon_crtc->h_border; in atombios_set_crtc_dtd_timing()
329 args.ucV_Border = radeon_crtc->v_border; in atombios_set_crtc_dtd_timing()
331 if (mode->flags & DRM_MODE_FLAG_NVSYNC) in atombios_set_crtc_dtd_timing()
333 if (mode->flags & DRM_MODE_FLAG_NHSYNC) in atombios_set_crtc_dtd_timing()
335 if (mode->flags & DRM_MODE_FLAG_CSYNC) in atombios_set_crtc_dtd_timing()
337 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in atombios_set_crtc_dtd_timing()
339 if (mode->flags & DRM_MODE_FLAG_DBLCLK) in atombios_set_crtc_dtd_timing()
341 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) in atombios_set_crtc_dtd_timing()
345 args.ucCRTC = radeon_crtc->crtc_id; in atombios_set_crtc_dtd_timing()
347 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); in atombios_set_crtc_dtd_timing()
354 struct drm_device *dev = crtc->dev; in atombios_crtc_set_timing()
355 struct radeon_device *rdev = dev->dev_private; in atombios_crtc_set_timing()
361 args.usH_Total = cpu_to_le16(mode->crtc_htotal); in atombios_crtc_set_timing()
362 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay); in atombios_crtc_set_timing()
363 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start); in atombios_crtc_set_timing()
365 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); in atombios_crtc_set_timing()
366 args.usV_Total = cpu_to_le16(mode->crtc_vtotal); in atombios_crtc_set_timing()
367 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay); in atombios_crtc_set_timing()
368 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start); in atombios_crtc_set_timing()
370 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); in atombios_crtc_set_timing()
372 args.ucOverscanRight = radeon_crtc->h_border; in atombios_crtc_set_timing()
373 args.ucOverscanLeft = radeon_crtc->h_border; in atombios_crtc_set_timing()
374 args.ucOverscanBottom = radeon_crtc->v_border; in atombios_crtc_set_timing()
375 args.ucOverscanTop = radeon_crtc->v_border; in atombios_crtc_set_timing()
377 if (mode->flags & DRM_MODE_FLAG_NVSYNC) in atombios_crtc_set_timing()
379 if (mode->flags & DRM_MODE_FLAG_NHSYNC) in atombios_crtc_set_timing()
381 if (mode->flags & DRM_MODE_FLAG_CSYNC) in atombios_crtc_set_timing()
383 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in atombios_crtc_set_timing()
385 if (mode->flags & DRM_MODE_FLAG_DBLCLK) in atombios_crtc_set_timing()
387 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) in atombios_crtc_set_timing()
391 args.ucCRTC = radeon_crtc->crtc_id; in atombios_crtc_set_timing()
393 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); in atombios_crtc_set_timing()
460 if (ss->percentage == 0) in atombios_crtc_program_ss()
462 if (ss->type & ATOM_EXTERNAL_SS_MASK) in atombios_crtc_program_ss()
465 for (i = 0; i < rdev->num_crtc; i++) { in atombios_crtc_program_ss()
466 if (rdev->mode_info.crtcs[i] && in atombios_crtc_program_ss()
467 rdev->mode_info.crtcs[i]->enabled && in atombios_crtc_program_ss()
469 pll_id == rdev->mode_info.crtcs[i]->pll_id) { in atombios_crtc_program_ss()
483 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; in atombios_crtc_program_ss()
497 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); in atombios_crtc_program_ss()
498 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); in atombios_crtc_program_ss()
501 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); in atombios_crtc_program_ss()
502 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; in atombios_crtc_program_ss()
516 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); in atombios_crtc_program_ss()
517 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step); in atombios_crtc_program_ss()
520 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); in atombios_crtc_program_ss()
521 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; in atombios_crtc_program_ss()
522 args.v1.ucSpreadSpectrumStep = ss->step; in atombios_crtc_program_ss()
523 args.v1.ucSpreadSpectrumDelay = ss->delay; in atombios_crtc_program_ss()
524 args.v1.ucSpreadSpectrumRange = ss->range; in atombios_crtc_program_ss()
528 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || in atombios_crtc_program_ss()
529 (ss->type & ATOM_EXTERNAL_SS_MASK)) { in atombios_crtc_program_ss()
533 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); in atombios_crtc_program_ss()
534 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; in atombios_crtc_program_ss()
535 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step; in atombios_crtc_program_ss()
536 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay; in atombios_crtc_program_ss()
537 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range; in atombios_crtc_program_ss()
544 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); in atombios_crtc_program_ss()
545 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; in atombios_crtc_program_ss()
546 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2; in atombios_crtc_program_ss()
547 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4; in atombios_crtc_program_ss()
550 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); in atombios_crtc_program_ss()
562 struct drm_device *dev = crtc->dev; in atombios_adjust_pll()
563 struct radeon_device *rdev = dev->dev_private; in atombios_adjust_pll()
564 struct drm_encoder *encoder = radeon_crtc->encoder; in atombios_adjust_pll()
567 u32 adjusted_clock = mode->clock; in atombios_adjust_pll()
569 u32 dp_clock = mode->clock; in atombios_adjust_pll()
570 u32 clock = mode->clock; in atombios_adjust_pll()
571 int bpc = radeon_crtc->bpc; in atombios_adjust_pll()
572 bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock); in atombios_adjust_pll()
575 radeon_crtc->pll_flags = 0; in atombios_adjust_pll()
578 if ((rdev->family == CHIP_RS600) || in atombios_adjust_pll()
579 (rdev->family == CHIP_RS690) || in atombios_adjust_pll()
580 (rdev->family == CHIP_RS740)) in atombios_adjust_pll()
581 radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/ in atombios_adjust_pll()
584 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */ in atombios_adjust_pll()
585 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; in atombios_adjust_pll()
587 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; in atombios_adjust_pll()
589 if (rdev->family < CHIP_RV770) in atombios_adjust_pll()
590 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP; in atombios_adjust_pll()
591 /* use frac fb div on APUs */ in atombios_adjust_pll()
593 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; in atombios_adjust_pll()
594 /* use frac fb div on RS780/RS880 */ in atombios_adjust_pll()
595 if (((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) in atombios_adjust_pll()
596 && !radeon_crtc->ss_enabled) in atombios_adjust_pll()
597 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; in atombios_adjust_pll()
598 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000) in atombios_adjust_pll()
599 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; in atombios_adjust_pll()
601 radeon_crtc->pll_flags |= RADEON_PLL_LEGACY; in atombios_adjust_pll()
603 if (mode->clock > 200000) /* range limits??? */ in atombios_adjust_pll()
604 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; in atombios_adjust_pll()
606 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; in atombios_adjust_pll()
609 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || in atombios_adjust_pll()
614 radeon_connector->con_priv; in atombios_adjust_pll()
616 dp_clock = dig_connector->dp_clock; in atombios_adjust_pll()
621 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { in atombios_adjust_pll()
622 if (radeon_crtc->ss_enabled) { in atombios_adjust_pll()
623 if (radeon_crtc->ss.refdiv) { in atombios_adjust_pll()
624 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; in atombios_adjust_pll()
625 radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv; in atombios_adjust_pll()
627 rdev->family != CHIP_RS780 && in atombios_adjust_pll()
628 rdev->family != CHIP_RS880) in atombios_adjust_pll()
629 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; in atombios_adjust_pll()
636 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) in atombios_adjust_pll()
637 adjusted_clock = mode->clock * 2; in atombios_adjust_pll()
638 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) in atombios_adjust_pll()
639 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; in atombios_adjust_pll()
640 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) in atombios_adjust_pll()
641 radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD; in atombios_adjust_pll()
643 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) in atombios_adjust_pll()
644 radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; in atombios_adjust_pll()
645 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) in atombios_adjust_pll()
646 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; in atombios_adjust_pll()
677 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, in atombios_adjust_pll()
689 args.v1.ucTransmitterID = radeon_encoder->encoder_id; in atombios_adjust_pll()
691 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) in atombios_adjust_pll()
695 atom_execute_table(rdev->mode_info.atom_context, in atombios_adjust_pll()
701 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id; in atombios_adjust_pll()
704 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) in atombios_adjust_pll()
712 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { in atombios_adjust_pll()
713 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; in atombios_adjust_pll() local
714 if (dig->coherent_mode) in atombios_adjust_pll()
728 atom_execute_table(rdev->mode_info.atom_context, in atombios_adjust_pll()
732 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; in atombios_adjust_pll()
733 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; in atombios_adjust_pll()
734 radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv; in atombios_adjust_pll()
737 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; in atombios_adjust_pll()
738 radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV; in atombios_adjust_pll()
739 radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv; in atombios_adjust_pll()
777 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, in atombios_crtc_set_disp_eng_pll()
813 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); in atombios_crtc_set_disp_eng_pll()
830 struct drm_device *dev = crtc->dev; in atombios_crtc_program_pll()
831 struct radeon_device *rdev = dev->dev_private; in atombios_crtc_program_pll()
838 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, in atombios_crtc_program_pll()
878 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) in atombios_crtc_program_pll()
891 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) in atombios_crtc_program_pll()
920 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) in atombios_crtc_program_pll()
953 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); in atombios_crtc_program_pll()
959 struct drm_device *dev = crtc->dev; in atombios_crtc_prepare_pll()
960 struct radeon_device *rdev = dev->dev_private; in atombios_crtc_prepare_pll()
962 to_radeon_encoder(radeon_crtc->encoder); in atombios_crtc_prepare_pll()
963 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); in atombios_crtc_prepare_pll()
965 radeon_crtc->bpc = 8; in atombios_crtc_prepare_pll()
966 radeon_crtc->ss_enabled = false; in atombios_crtc_prepare_pll()
968 if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || in atombios_crtc_prepare_pll()
969 (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) { in atombios_crtc_prepare_pll()
970 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; in atombios_crtc_prepare_pll() local
972 radeon_get_connector_for_encoder(radeon_crtc->encoder); in atombios_crtc_prepare_pll()
976 radeon_connector->con_priv; in atombios_crtc_prepare_pll()
980 radeon_connector->pixelclock_for_modeset = mode->clock; in atombios_crtc_prepare_pll()
981 radeon_crtc->bpc = radeon_get_monitor_bpc(connector); in atombios_crtc_prepare_pll()
987 dp_clock = dig_connector->dp_clock / 10; in atombios_crtc_prepare_pll()
989 radeon_crtc->ss_enabled = in atombios_crtc_prepare_pll()
990 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss, in atombios_crtc_prepare_pll()
995 radeon_crtc->ss_enabled = in atombios_crtc_prepare_pll()
997 &radeon_crtc->ss, in atombios_crtc_prepare_pll()
999 if (!radeon_crtc->ss_enabled) in atombios_crtc_prepare_pll()
1000 radeon_crtc->ss_enabled = in atombios_crtc_prepare_pll()
1002 &radeon_crtc->ss, in atombios_crtc_prepare_pll()
1005 radeon_crtc->ss_enabled = in atombios_crtc_prepare_pll()
1007 &radeon_crtc->ss, in atombios_crtc_prepare_pll()
1011 radeon_crtc->ss_enabled = false; in atombios_crtc_prepare_pll()
1016 radeon_crtc->ss_enabled = in atombios_crtc_prepare_pll()
1018 &radeon_crtc->ss, in atombios_crtc_prepare_pll()
1019 dig->lcd_ss_id, in atombios_crtc_prepare_pll()
1020 mode->clock / 10); in atombios_crtc_prepare_pll()
1022 radeon_crtc->ss_enabled = in atombios_crtc_prepare_pll()
1024 &radeon_crtc->ss, in atombios_crtc_prepare_pll()
1025 dig->lcd_ss_id); in atombios_crtc_prepare_pll()
1029 radeon_crtc->ss_enabled = in atombios_crtc_prepare_pll()
1031 &radeon_crtc->ss, in atombios_crtc_prepare_pll()
1033 mode->clock / 10); in atombios_crtc_prepare_pll()
1037 radeon_crtc->ss_enabled = in atombios_crtc_prepare_pll()
1039 &radeon_crtc->ss, in atombios_crtc_prepare_pll()
1041 mode->clock / 10); in atombios_crtc_prepare_pll()
1049 radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode); in atombios_crtc_prepare_pll()
1057 struct drm_device *dev = crtc->dev; in atombios_crtc_set_pll()
1058 struct radeon_device *rdev = dev->dev_private; in atombios_crtc_set_pll()
1060 to_radeon_encoder(radeon_crtc->encoder); in atombios_crtc_set_pll()
1061 u32 pll_clock = mode->clock; in atombios_crtc_set_pll()
1062 u32 clock = mode->clock; in atombios_crtc_set_pll()
1065 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); in atombios_crtc_set_pll()
1070 (radeon_crtc->bpc > 8)) in atombios_crtc_set_pll()
1071 clock = radeon_crtc->adjusted_clock; in atombios_crtc_set_pll()
1073 switch (radeon_crtc->pll_id) { in atombios_crtc_set_pll()
1075 pll = &rdev->clock.p1pll; in atombios_crtc_set_pll()
1078 pll = &rdev->clock.p2pll; in atombios_crtc_set_pll()
1083 pll = &rdev->clock.dcpll; in atombios_crtc_set_pll()
1088 pll->flags = radeon_crtc->pll_flags; in atombios_crtc_set_pll()
1089 pll->reference_div = radeon_crtc->pll_reference_div; in atombios_crtc_set_pll()
1090 pll->post_div = radeon_crtc->pll_post_div; in atombios_crtc_set_pll()
1092 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) in atombios_crtc_set_pll()
1094 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, in atombios_crtc_set_pll()
1097 radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock, in atombios_crtc_set_pll()
1100 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, in atombios_crtc_set_pll()
1103 atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id, in atombios_crtc_set_pll()
1104 radeon_crtc->crtc_id, &radeon_crtc->ss); in atombios_crtc_set_pll()
1106 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, in atombios_crtc_set_pll()
1107 encoder_mode, radeon_encoder->encoder_id, clock, in atombios_crtc_set_pll()
1109 radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss); in atombios_crtc_set_pll()
1111 if (radeon_crtc->ss_enabled) { in atombios_crtc_set_pll()
1116 (u32)radeon_crtc->ss.percentage) / in atombios_crtc_set_pll()
1117 (100 * (u32)radeon_crtc->ss.percentage_divider); in atombios_crtc_set_pll()
1118 radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK; in atombios_crtc_set_pll()
1119 radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) & in atombios_crtc_set_pll()
1121 if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD) in atombios_crtc_set_pll()
1122 step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) / in atombios_crtc_set_pll()
1123 (125 * 25 * pll->reference_freq / 100); in atombios_crtc_set_pll()
1125 step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) / in atombios_crtc_set_pll()
1126 (125 * 25 * pll->reference_freq / 100); in atombios_crtc_set_pll()
1127 radeon_crtc->ss.step = step_size; in atombios_crtc_set_pll()
1130 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id, in atombios_crtc_set_pll()
1131 radeon_crtc->crtc_id, &radeon_crtc->ss); in atombios_crtc_set_pll()
1140 struct drm_device *dev = crtc->dev; in dce4_crtc_do_set_base()
1141 struct radeon_device *rdev = dev->dev_private; in dce4_crtc_do_set_base()
1154 if (!atomic && !crtc->primary->fb) { in dce4_crtc_do_set_base()
1162 target_fb = crtc->primary->fb; in dce4_crtc_do_set_base()
1167 obj = target_fb->obj[0]; in dce4_crtc_do_set_base()
1179 return -EINVAL; in dce4_crtc_do_set_base()
1186 switch (target_fb->format->format) { in dce4_crtc_do_set_base()
1237 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ in dce4_crtc_do_set_base()
1247 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ in dce4_crtc_do_set_base()
1262 &target_fb->format->format); in dce4_crtc_do_set_base()
1263 return -EINVAL; in dce4_crtc_do_set_base()
1270 if (rdev->family >= CHIP_TAHITI) { in dce4_crtc_do_set_base()
1273 if (rdev->family >= CHIP_BONAIRE) { in dce4_crtc_do_set_base()
1278 tileb = 8 * 8 * target_fb->format->cpp[0]; in dce4_crtc_do_set_base()
1286 target_fb->format->cpp[0] * 8, in dce4_crtc_do_set_base()
1288 return -EINVAL; in dce4_crtc_do_set_base()
1291 num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3; in dce4_crtc_do_set_base()
1293 switch (target_fb->format->cpp[0] * 8) { in dce4_crtc_do_set_base()
1306 num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3; in dce4_crtc_do_set_base()
1312 if (rdev->family >= CHIP_CAYMAN) in dce4_crtc_do_set_base()
1313 tmp = rdev->config.cayman.tile_config; in dce4_crtc_do_set_base()
1315 tmp = rdev->config.evergreen.tile_config; in dce4_crtc_do_set_base()
1336 if (rdev->family >= CHIP_BONAIRE) { in dce4_crtc_do_set_base()
1343 if (rdev->family >= CHIP_BONAIRE) { in dce4_crtc_do_set_base()
1347 u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f; in dce4_crtc_do_set_base()
1350 } else if ((rdev->family == CHIP_TAHITI) || in dce4_crtc_do_set_base()
1351 (rdev->family == CHIP_PITCAIRN)) in dce4_crtc_do_set_base()
1353 else if ((rdev->family == CHIP_VERDE) || in dce4_crtc_do_set_base()
1354 (rdev->family == CHIP_OLAND) || in dce4_crtc_do_set_base()
1355 (rdev->family == CHIP_HAINAN)) /* for completeness. HAINAN has no display hw */ in dce4_crtc_do_set_base()
1358 switch (radeon_crtc->crtc_id) { in dce4_crtc_do_set_base()
1384 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0); in dce4_crtc_do_set_base()
1386 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1388 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1390 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1392 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1394 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); in dce4_crtc_do_set_base()
1395 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); in dce4_crtc_do_set_base()
1402 WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1409 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); in dce4_crtc_do_set_base()
1410 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); in dce4_crtc_do_set_base()
1411 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); in dce4_crtc_do_set_base()
1412 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0); in dce4_crtc_do_set_base()
1413 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); in dce4_crtc_do_set_base()
1414 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); in dce4_crtc_do_set_base()
1416 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; in dce4_crtc_do_set_base()
1417 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); in dce4_crtc_do_set_base()
1418 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); in dce4_crtc_do_set_base()
1420 if (rdev->family >= CHIP_BONAIRE) in dce4_crtc_do_set_base()
1421 WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1422 target_fb->height); in dce4_crtc_do_set_base()
1424 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1425 target_fb->height); in dce4_crtc_do_set_base()
1428 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1430 viewport_w = crtc->mode.hdisplay; in dce4_crtc_do_set_base()
1431 viewport_h = (crtc->mode.vdisplay + 1) & ~1; in dce4_crtc_do_set_base()
1432 if ((rdev->family >= CHIP_BONAIRE) && in dce4_crtc_do_set_base()
1433 (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)) in dce4_crtc_do_set_base()
1435 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1439 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); in dce4_crtc_do_set_base()
1441 if (!atomic && fb && fb != crtc->primary->fb) { in dce4_crtc_do_set_base()
1442 rbo = gem_to_radeon_bo(fb->obj[0]); in dce4_crtc_do_set_base()
1461 struct drm_device *dev = crtc->dev; in avivo_crtc_do_set_base()
1462 struct radeon_device *rdev = dev->dev_private; in avivo_crtc_do_set_base()
1474 if (!atomic && !crtc->primary->fb) { in avivo_crtc_do_set_base()
1482 target_fb = crtc->primary->fb; in avivo_crtc_do_set_base()
1484 obj = target_fb->obj[0]; in avivo_crtc_do_set_base()
1499 return -EINVAL; in avivo_crtc_do_set_base()
1505 switch (target_fb->format->format) { in avivo_crtc_do_set_base()
1553 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ in avivo_crtc_do_set_base()
1561 if (rdev->family >= CHIP_R600) in avivo_crtc_do_set_base()
1573 &target_fb->format->format); in avivo_crtc_do_set_base()
1574 return -EINVAL; in avivo_crtc_do_set_base()
1577 if (rdev->family >= CHIP_R600) { in avivo_crtc_do_set_base()
1590 if (radeon_crtc->crtc_id == 0) in avivo_crtc_do_set_base()
1598 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0); in avivo_crtc_do_set_base()
1600 if (rdev->family >= CHIP_RV770) { in avivo_crtc_do_set_base()
1601 if (radeon_crtc->crtc_id) { in avivo_crtc_do_set_base()
1609 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in avivo_crtc_do_set_base()
1612 radeon_crtc->crtc_offset, (u32) fb_location); in avivo_crtc_do_set_base()
1613 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); in avivo_crtc_do_set_base()
1614 if (rdev->family >= CHIP_R600) in avivo_crtc_do_set_base()
1615 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); in avivo_crtc_do_set_base()
1618 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, in avivo_crtc_do_set_base()
1624 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); in avivo_crtc_do_set_base()
1625 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); in avivo_crtc_do_set_base()
1626 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); in avivo_crtc_do_set_base()
1627 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); in avivo_crtc_do_set_base()
1628 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); in avivo_crtc_do_set_base()
1629 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); in avivo_crtc_do_set_base()
1631 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; in avivo_crtc_do_set_base()
1632 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); in avivo_crtc_do_set_base()
1633 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); in avivo_crtc_do_set_base()
1635 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, in avivo_crtc_do_set_base()
1636 target_fb->height); in avivo_crtc_do_set_base()
1639 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, in avivo_crtc_do_set_base()
1641 viewport_w = crtc->mode.hdisplay; in avivo_crtc_do_set_base()
1642 viewport_h = (crtc->mode.vdisplay + 1) & ~1; in avivo_crtc_do_set_base()
1643 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, in avivo_crtc_do_set_base()
1647 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3); in avivo_crtc_do_set_base()
1649 if (!atomic && fb && fb != crtc->primary->fb) { in avivo_crtc_do_set_base()
1650 rbo = gem_to_radeon_bo(fb->obj[0]); in avivo_crtc_do_set_base()
1667 struct drm_device *dev = crtc->dev; in atombios_crtc_set_base()
1668 struct radeon_device *rdev = dev->dev_private; in atombios_crtc_set_base()
1682 struct drm_device *dev = crtc->dev; in atombios_crtc_set_base_atomic()
1683 struct radeon_device *rdev = dev->dev_private; in atombios_crtc_set_base_atomic()
1696 struct drm_device *dev = crtc->dev; in radeon_legacy_atom_fixup()
1697 struct radeon_device *rdev = dev->dev_private; in radeon_legacy_atom_fixup()
1701 switch (radeon_crtc->crtc_id) { in radeon_legacy_atom_fixup()
1718 * radeon_get_pll_use_mask - look up a mask of which pplls are in use
1726 struct drm_device *dev = crtc->dev; in radeon_get_pll_use_mask()
1731 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { in radeon_get_pll_use_mask()
1736 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) in radeon_get_pll_use_mask()
1737 pll_in_use |= (1 << test_radeon_crtc->pll_id); in radeon_get_pll_use_mask()
1743 * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP
1753 struct drm_device *dev = crtc->dev; in radeon_get_shared_dp_ppll()
1754 struct radeon_device *rdev = dev->dev_private; in radeon_get_shared_dp_ppll()
1758 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { in radeon_get_shared_dp_ppll()
1762 if (test_radeon_crtc->encoder && in radeon_get_shared_dp_ppll()
1763 ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { in radeon_get_shared_dp_ppll()
1766 test_radeon_crtc->pll_id == ATOM_PPLL2) in radeon_get_shared_dp_ppll()
1769 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) in radeon_get_shared_dp_ppll()
1770 return test_radeon_crtc->pll_id; in radeon_get_shared_dp_ppll()
1777 * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
1781 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
1787 struct drm_device *dev = crtc->dev; in radeon_get_shared_nondp_ppll()
1788 struct radeon_device *rdev = dev->dev_private; in radeon_get_shared_nondp_ppll()
1793 adjusted_clock = radeon_crtc->adjusted_clock; in radeon_get_shared_nondp_ppll()
1798 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { in radeon_get_shared_nondp_ppll()
1802 if (test_radeon_crtc->encoder && in radeon_get_shared_nondp_ppll()
1803 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { in radeon_get_shared_nondp_ppll()
1806 test_radeon_crtc->pll_id == ATOM_PPLL2) in radeon_get_shared_nondp_ppll()
1809 if (test_radeon_crtc->connector == radeon_crtc->connector) { in radeon_get_shared_nondp_ppll()
1811 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) in radeon_get_shared_nondp_ppll()
1812 return test_radeon_crtc->pll_id; in radeon_get_shared_nondp_ppll()
1814 /* for non-DP check the clock */ in radeon_get_shared_nondp_ppll()
1815 test_adjusted_clock = test_radeon_crtc->adjusted_clock; in radeon_get_shared_nondp_ppll()
1816 if ((crtc->mode.clock == test_crtc->mode.clock) && in radeon_get_shared_nondp_ppll()
1818 (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) && in radeon_get_shared_nondp_ppll()
1819 (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)) in radeon_get_shared_nondp_ppll()
1820 return test_radeon_crtc->pll_id; in radeon_get_shared_nondp_ppll()
1827 * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc.
1832 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
1843 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
1845 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1848 * - PPLL2 is only available to UNIPHYA (both DP and non-DP)
1849 * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP)
1852 * - PPLL0 is available to all UNIPHY (DP only)
1853 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1856 * - DCPLL is available to all UNIPHY (DP only)
1857 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1860 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1866 struct drm_device *dev = crtc->dev; in radeon_atom_pick_pll()
1867 struct radeon_device *rdev = dev->dev_private; in radeon_atom_pick_pll()
1869 to_radeon_encoder(radeon_crtc->encoder); in radeon_atom_pick_pll()
1874 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { in radeon_atom_pick_pll()
1875 if (rdev->clock.dp_extclk) in radeon_atom_pick_pll()
1891 if ((rdev->family == CHIP_KABINI) || in radeon_atom_pick_pll()
1892 (rdev->family == CHIP_MULLINS)) { in radeon_atom_pick_pll()
1914 struct radeon_encoder_atom_dig *dig = in radeon_atom_pick_pll() local
1915 radeon_encoder->enc_priv; in radeon_atom_pick_pll()
1917 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) && in radeon_atom_pick_pll()
1918 (dig->linkb == false)) in radeon_atom_pick_pll()
1921 else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { in radeon_atom_pick_pll()
1923 if (rdev->clock.dp_extclk) in radeon_atom_pick_pll()
1948 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { in radeon_atom_pick_pll()
1949 if (rdev->clock.dp_extclk) in radeon_atom_pick_pll()
1971 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { in radeon_atom_pick_pll()
1972 if (rdev->clock.dp_extclk) in radeon_atom_pick_pll()
2002 /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */ in radeon_atom_pick_pll()
2017 return radeon_crtc->crtc_id; in radeon_atom_pick_pll()
2025 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); in radeon_atom_disp_eng_pll_init()
2030 rdev->clock.default_dispclk); in radeon_atom_disp_eng_pll_init()
2032 atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss); in radeon_atom_disp_eng_pll_init()
2034 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); in radeon_atom_disp_eng_pll_init()
2036 atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss); in radeon_atom_disp_eng_pll_init()
2047 struct drm_device *dev = crtc->dev; in atombios_crtc_mode_set()
2048 struct radeon_device *rdev = dev->dev_private; in atombios_crtc_mode_set()
2050 to_radeon_encoder(radeon_crtc->encoder); in atombios_crtc_mode_set()
2053 if (radeon_encoder->active_device & in atombios_crtc_mode_set()
2057 if (!radeon_crtc->adjusted_clock) in atombios_crtc_mode_set()
2058 return -EINVAL; in atombios_crtc_mode_set()
2071 if (radeon_crtc->crtc_id == 0) in atombios_crtc_mode_set()
2080 radeon_crtc->hw_mode = *adjusted_mode; in atombios_crtc_mode_set()
2090 struct drm_device *dev = crtc->dev; in atombios_crtc_mode_fixup()
2094 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { in atombios_crtc_mode_fixup()
2095 if (encoder->crtc == crtc) { in atombios_crtc_mode_fixup()
2096 radeon_crtc->encoder = encoder; in atombios_crtc_mode_fixup()
2097 radeon_crtc->connector = radeon_get_connector_for_encoder(encoder); in atombios_crtc_mode_fixup()
2101 if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) { in atombios_crtc_mode_fixup()
2102 radeon_crtc->encoder = NULL; in atombios_crtc_mode_fixup()
2103 radeon_crtc->connector = NULL; in atombios_crtc_mode_fixup()
2106 if (radeon_crtc->encoder) { in atombios_crtc_mode_fixup()
2108 to_radeon_encoder(radeon_crtc->encoder); in atombios_crtc_mode_fixup()
2110 radeon_crtc->output_csc = radeon_encoder->output_csc; in atombios_crtc_mode_fixup()
2117 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc); in atombios_crtc_mode_fixup()
2118 /* if we can't get a PPLL for a non-DP encoder, fail */ in atombios_crtc_mode_fixup()
2119 if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) && in atombios_crtc_mode_fixup()
2120 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) in atombios_crtc_mode_fixup()
2128 struct drm_device *dev = crtc->dev; in atombios_crtc_prepare()
2129 struct radeon_device *rdev = dev->dev_private; in atombios_crtc_prepare()
2148 struct drm_device *dev = crtc->dev; in atombios_crtc_disable()
2149 struct radeon_device *rdev = dev->dev_private; in atombios_crtc_disable()
2154 if (crtc->primary->fb) { in atombios_crtc_disable()
2158 rbo = gem_to_radeon_bo(crtc->primary->fb->obj[0]); in atombios_crtc_disable()
2169 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0); in atombios_crtc_disable()
2171 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0); in atombios_crtc_disable()
2176 for (i = 0; i < rdev->num_crtc; i++) { in atombios_crtc_disable()
2177 if (rdev->mode_info.crtcs[i] && in atombios_crtc_disable()
2178 rdev->mode_info.crtcs[i]->enabled && in atombios_crtc_disable()
2179 i != radeon_crtc->crtc_id && in atombios_crtc_disable()
2180 radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) { in atombios_crtc_disable()
2188 switch (radeon_crtc->pll_id) { in atombios_crtc_disable()
2192 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, in atombios_crtc_disable()
2197 if ((rdev->family == CHIP_ARUBA) || in atombios_crtc_disable()
2198 (rdev->family == CHIP_KAVERI) || in atombios_crtc_disable()
2199 (rdev->family == CHIP_BONAIRE) || in atombios_crtc_disable()
2200 (rdev->family == CHIP_HAWAII)) in atombios_crtc_disable()
2201 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, in atombios_crtc_disable()
2208 radeon_crtc->pll_id = ATOM_PPLL_INVALID; in atombios_crtc_disable()
2209 radeon_crtc->adjusted_clock = 0; in atombios_crtc_disable()
2210 radeon_crtc->encoder = NULL; in atombios_crtc_disable()
2211 radeon_crtc->connector = NULL; in atombios_crtc_disable()
2229 struct radeon_device *rdev = dev->dev_private; in radeon_atombios_init_crtc()
2232 switch (radeon_crtc->crtc_id) { in radeon_atombios_init_crtc()
2235 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET; in radeon_atombios_init_crtc()
2238 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; in radeon_atombios_init_crtc()
2241 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET; in radeon_atombios_init_crtc()
2244 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET; in radeon_atombios_init_crtc()
2247 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET; in radeon_atombios_init_crtc()
2250 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET; in radeon_atombios_init_crtc()
2254 if (radeon_crtc->crtc_id == 1) in radeon_atombios_init_crtc()
2255 radeon_crtc->crtc_offset = in radeon_atombios_init_crtc()
2256 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; in radeon_atombios_init_crtc()
2258 radeon_crtc->crtc_offset = 0; in radeon_atombios_init_crtc()
2260 radeon_crtc->pll_id = ATOM_PPLL_INVALID; in radeon_atombios_init_crtc()
2261 radeon_crtc->adjusted_clock = 0; in radeon_atombios_init_crtc()
2262 radeon_crtc->encoder = NULL; in radeon_atombios_init_crtc()
2263 radeon_crtc->connector = NULL; in radeon_atombios_init_crtc()
2264 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); in radeon_atombios_init_crtc()