Lines Matching full:ppll
1545 // 0 means disable PPLL
1552 UCHAR ucCRTC; // Which CRTC uses this Ppll
1565 // 0 means disable PPLL
1572 UCHAR ucCRTC; // Which CRTC uses this Ppll
1612 … // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0.
1625 … // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source
1641 // 0 means disable PPLL/DCPLL.
1649 UCHAR ucMiscInfo; // bit[0]= Force program PPLL
1652 // bit[4]= RefClock source for PPLL.
1675 … // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
1678 … // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
1697 UCHAR ucMiscInfo; // bit[0]= Force program PPLL
1700 // bit[4]= RefClock source for PPLL.
1782 …ULONG ulDispPllFreq; // return display PPLL freq which is used to generate the pix…
1783 … // if it is none-zero, it is used to be calculated the other ppll parameter fb_divide…
1784 … // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider
1923 //This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devi…
2685 … //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input cl…
2724 … //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input cl…
3643 … Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS Others:TBD