Lines Matching +full:1 +full:khz
59 #define ATOM_DAC_B 1
63 #define ATOM_CRTC2 1
71 #define ATOM_DIGB 1
74 #define ATOM_PPLL2 1
85 #define ENCODER_REFCLK_SRC_P2PLL 1
91 #define ATOM_SCALER2 1
94 #define ATOM_SCALER_CENTER 1
99 #define ATOM_ENABLE 1
109 #define ATOM_BLANKING 1
113 #define ATOM_CURSOR2 1
116 #define ATOM_ICON2 1
119 #define ATOM_CRT2 1
121 #define ATOM_TV_NTSC 1
131 #define ATOM_DAC1_PS2 1
142 #define ATOM_PM_STANDBY 1
146 /* Bit0:{=0:single, =1:dual},
147 Bit1 {=0:666RGB, =1:888RGB},
149 Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}*/
182 #define HW_ASSISTED_I2C_STATUS_SUCCESS 1
184 #pragma pack(1) /* BIOS data must use byte alignment */
357 USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag
363 USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag
387 #define COMPUTE_MEMORY_PLL_PARAM 1
397 …ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYT…
403 …ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYT…
411 UCHAR ucAction; //0:reserved //1:Memory //2:Engine
431 …pplicable to both memory and engine clock change,when set, it means this is 1st time to change clo…
438 …pplicable to both memory and engine clock change,when set, it means this is 1st time to change clo…
444 …ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PL…
445 ULONG ulClockFreq:24; // in unit of 10kHz
447 ULONG ulClockFreq:24; // in unit of 10kHz
448 …ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PL…
473 #define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN 1
504 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
536 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode
549 …UCHAR ucInputFlag; //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-Stro…
584 ULONG ulTargetEngineClock; //In 10Khz unit
589 ULONG ulTargetEngineClock; //In 10Khz unit
598 ULONG ulTargetMemoryClock; //In 10Khz unit
603 ULONG ulTargetMemoryClock; //In 10Khz unit
612 ULONG ulDefaultEngineClock; //In 10Khz unit
613 ULONG ulDefaultMemoryClock; //In 10Khz unit
676 USHORT usPixelClock; // in 10KHz; for bios convenient
677 …tion of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0)
679 // 1: setup and turn on encoder
692 USHORT usPixelClock; // in 10KHz; for bios convenient
696 // =1: PHY linkB if bfLanes<3
700 // =1: LVTMA
702 // =1: turn on encoder
705 // =1: LVDS encoder
737 #define ATOM_ENCODER_MODE_LVDS 1
753 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF
754 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F
755 UCHAR ucReserved:1;
756 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
758 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
759 UCHAR ucReserved:1;
760 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F
761 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF
769 USHORT usPixelClock; // in 10KHz; for bios convenient
774 // =1: LVDS encoder
813 //ucTableFormatRevision=1
819 UCHAR ucReserved1:1;
820 …UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as D…
822 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
824 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
826 …UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as D…
827 UCHAR ucReserved1:1;
844 USHORT usPixelClock; // in 10KHz; for bios convenient
850 // =1: LVDS encoder
857 // =1: internal DP2
865 //ucTableFormatRevision=1
872 UCHAR ucReserved1:1;
873 …UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as D…
875 …UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to prev…
877 …UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to prev…
879 …UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as D…
880 UCHAR ucReserved1:1;
900 USHORT usPixelClock; // in 10KHz; for bios convenient
909 // =1: LVDS encoder
916 // =1: internal DP2
921 …UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to prev…
952 USHORT usPixelClock; // in 10KHz; for bios convenient
958 // =1: 8 lane Link ( Dual Links TMDS )
959 // [1]=0: InCoherent mode
960 // =1: Coherent Mode
963 // =1: PHY linkB if bfLanes<3
967 // =1: lane 4~7
971 // =1: turn on encoder
1007 #define ATOM_TRANSMITTER_ACTION_ENABLE 1
1025 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1026 // =1 Dig Transmitter 2 ( Uniphy CD )
1028 UCHAR ucReserved:1;
1029 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector
1030 …UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/…
1031 …UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when…
1032 …// =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means ma…
1034 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1035 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1037 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1038 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1039 …UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when…
1040 …// =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means ma…
1041 …UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/…
1042 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector
1043 UCHAR ucReserved:1;
1044 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1045 // =1 Dig Transmitter 2 ( Uniphy CD )
1080 USHORT usPixelClock; // in 10KHz; for bios convenient
1092 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1093 // =1 Dig Transmitter 2 ( Uniphy CD )
1095 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
1096 …UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path …
1097 …UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when…
1098 …// =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means ma…
1099 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1100 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1102 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1103 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1104 …UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when…
1105 …// =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means ma…
1106 …UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path …
1107 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
1108 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1109 // =1 Dig Transmitter 2 ( Uniphy CD )
1119 USHORT usPixelClock; // in 10KHz; for bios convenient
1162 // ucTableFormatRevision=1
1188 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1189 // =1 Dig Transmitter 2 ( Uniphy CD )
1191 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
1192 …UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path …
1193 …UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when…
1194 …// =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means ma…
1195 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1196 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1198 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1199 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1200 …UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when…
1201 …// =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means ma…
1202 …UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path …
1203 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
1204 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1205 // =1 Dig Transmitter 2 ( Uniphy CD )
1214 USHORT usPixelClock; // in 10KHz; for bios convenient
1257 UCHAR ucReservd1:1;
1260 UCHAR ucCoherentMode:1;
1261 UCHAR ucReserved:1;
1263 UCHAR ucReserved:1;
1264 UCHAR ucCoherentMode:1;
1267 UCHAR ucReservd1:1;
1273 …USHORT usSymClock; // Encoder Clock in 10kHz,(DP mode)= linkclock/10, (TMDS/LVDS/HDMI)= p…
1274 …UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIP…
1276 UCHAR ucLaneNum; // indicate lane number 1-8
1291 #define ATOM_PHY_ID_UNIPHYB 1
1309 #define ATOM_TRANSMITTER_DIGMODE_V5_LVDS 1
1357 // ucTableFormatRevision=1
1364 USHORT usPixelClock; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT
1529 //#define ATOM_ENCODER_MODE_LVDS 1
1541 //Major revision=1., Minor revision=1
1544 …USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_D…
1556 //Major revision=1., Minor revision=2, add ucMiscIfno
1564 …USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_D…
1576 //Major revision=1., Minor revision=3, structure/definition change
1611 …USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_D…
1624 …UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC …
1625 … // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source
1626 …// bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the sour…
1650 // bit[1]= when VGA timing is used.
1651 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
1654 // =1: other external clock source, which is pre-defined
1657 …ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 (…
1698 // bit[1]= when VGA timing is used.
1699 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
1702 …// =1: other external clock source, which is pre-defined …
1705 …ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 (…
1714 …DMI_36BPP_V6 0x08 //for V6, the correct defintion for 36bpp should be 2 for 36bpp(2:1)
1716 …DMI_30BPP_V6 0x04 //for V6, the correct defintion for 30bpp should be 1 for 36bpp(5:4)
1729 …UCHAR ucRefDivSrc; // =1: reference clock source from XTALIN, =0: source from PCI…
1813 ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit
1822 ULONG ulReturnEngineClock; // current engine speed in 10KHz unit
1836 … //WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte
1844 #define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES 1
1854 //1bytePS+offsetPS
1860 UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2
1884 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected
1891 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected
1905 …UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int.…
1911 //ucTableFormatRevision=1,ucTableContentRevision=2
1915 …UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int.…
1927 …UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int…
1938 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
1939 // Bit[1]: 1-Ext. 0-Int.
1940 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
1963 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
1964 // Bit[1]: 1-Ext. 0-Int.
1965 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
2002 ULONG ulTargetMemoryClock; //In 10Khz unit
2017 USHORT usPixelClock; // in 10KHz; for bios convenient
2019 // =1: Enable dual link
2021 // =1: 888RGB
2023 // 1: setup and turn on encoder
2035 //ucTableFormatRevision=1,ucTableContentRevision=2
2038 USHORT usPixelClock; // in 10KHz; for bios convenient
2041 // 1: setup and turn on encoder
2043 // =1: Enable truncate
2045 // =1: 888RGB
2047 // =1: Enable spatial dithering
2049 // =1: 888RGB
2051 // =1: Enable temporal dithering
2053 // =1: 888RGB
2055 // =1: Gray level 4
2057 // =1: 25FRC_SEL pattern F
2059 // =1: 50FRC_SEL pattern B
2063 // =1: 75FRC_SEL pattern F
2089 …AR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:88…
2116 //ucTableFormatRevision=1,ucTableContentRevision=3
2147 //ucTableFormatRevision=1
2148 //ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for
2150 // =1: coherent mode
2174 #define PANEL_ENCODER_ACTION_COHERENTSEQ (ATOM_ENABLE+1)
2198 #define SET_VOLTAGE_TYPE_ASIC_VDDC 1
2233 …USHORT usVoltageLevel; // real voltage level in unit of mv or Voltage Phase (0, 1, …
2237 #define VOLTAGE_TYPE_VDDC 1
2271 … // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage …
2291 // GetVoltageInfo v1.1 ucVoltageMode
2310 … // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage …
2330 USHORT usPixelClock; // in 10KHz; for bios convenient
2333 // 1: setup and turn on encoder
2419 …UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM aud…
2420 …UCHAR ucMiscInfo2; // I2S input config (0) I2S output config (1) I2S Audio…
2423 …UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical co…
2424 …UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical co…
2425 …UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical co…
2426 …UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical co…
2427 …UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical co…
2436 // Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted;
2437 // Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported;
2438 // Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported;
2443 #define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memclk S…
2444 #define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engclk S…
2452 #define ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT 0x0008 // (valid from v2.1 ): =1: memclk ss en…
2453 #define ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT 0x0010 // (valid from v2.1 ): =1: engclk ss en…
2461 USHORT Reserved:1;
2462 USHORT SCL2Redefined:1;
2463 USHORT PostWithoutModeSet:1;
2465 USHORT HyperMemory_Support:1;
2466 USHORT PPMode_Assigned:1;
2467 USHORT WMI_SUPPORT:1;
2468 USHORT GPUControlsBL:1;
2469 USHORT EngineClockSS_Support:1;
2470 USHORT MemoryClockSS_Support:1;
2471 USHORT ExtendedDesktopSupport:1;
2472 USHORT DualCRTC_Support:1;
2473 USHORT FirmwarePosted:1;
2475 USHORT FirmwarePosted:1;
2476 USHORT DualCRTC_Support:1;
2477 USHORT ExtendedDesktopSupport:1;
2478 USHORT MemoryClockSS_Support:1;
2479 USHORT EngineClockSS_Support:1;
2480 USHORT GPUControlsBL:1;
2481 USHORT WMI_SUPPORT:1;
2482 USHORT PPMode_Assigned:1;
2483 USHORT HyperMemory_Support:1;
2485 USHORT PostWithoutModeSet:1;
2486 USHORT SCL2Redefined:1;
2487 USHORT Reserved:1;
2510 ULONG ulDefaultEngineClock; //In 10Khz unit
2511 ULONG ulDefaultMemoryClock; //In 10Khz unit
2512 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2513 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2514 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2515 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2516 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2517 ULONG ulASICMaxEngineClock; //In 10Khz unit
2518 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2522 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
2523 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
2524 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
2525 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
2526 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
2527 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
2528 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2529 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2530 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
2531 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above…
2533 USHORT usReferenceClock; //In 10Khz unit
2534 … usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
2544 ULONG ulDefaultEngineClock; //In 10Khz unit
2545 ULONG ulDefaultMemoryClock; //In 10Khz unit
2546 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2547 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2548 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2549 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2550 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2551 ULONG ulASICMaxEngineClock; //In 10Khz unit
2552 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2557 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2558 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
2559 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
2560 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
2561 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
2562 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
2563 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
2564 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2565 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2566 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
2567 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
2569 USHORT usReferenceClock; //In 10Khz unit
2570 … usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
2580 ULONG ulDefaultEngineClock; //In 10Khz unit
2581 ULONG ulDefaultMemoryClock; //In 10Khz unit
2582 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2583 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2584 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2585 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2586 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2587 ULONG ulASICMaxEngineClock; //In 10Khz unit
2588 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2593 ULONG ul3DAccelerationEngineClock;//In 10Khz unit
2594 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2595 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
2596 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
2597 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
2598 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
2599 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
2600 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
2601 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2602 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2603 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
2604 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
2606 USHORT usReferenceClock; //In 10Khz unit
2607 … usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
2617 ULONG ulDefaultEngineClock; //In 10Khz unit
2618 ULONG ulDefaultMemoryClock; //In 10Khz unit
2619 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2620 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2621 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2622 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2623 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2624 ULONG ulASICMaxEngineClock; //In 10Khz unit
2625 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2631 ULONG ul3DAccelerationEngineClock;//In 10Khz unit
2632 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2633 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
2634 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
2635 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
2636 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
2637 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
2638 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
2639 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2640 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2641 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
2642 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
2644 USHORT usReferenceClock; //In 10Khz unit
2645 … usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
2656 ULONG ulDefaultEngineClock; //In 10Khz unit
2657 ULONG ulDefaultMemoryClock; //In 10Khz unit
2660 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2661 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2662 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2664 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit
2671 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2672 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
2673 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
2674 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
2675 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
2676 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
2677 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
2678 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2679 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2680 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
2681 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
2683 USHORT usCoreReferenceClock; //In 10Khz unit
2684 USHORT usMemoryReferenceClock; //In 10Khz unit
2685 …USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mod…
2697 ULONG ulDefaultEngineClock; //In 10Khz unit
2698 ULONG ulDefaultMemoryClock; //In 10Khz unit
2699 ULONG ulSPLL_OutputFreq; //In 10Khz unit
2700 ULONG ulGPUPLL_OutputFreq; //In 10Khz unit
2701 … ulReserved1; //Was ulMaxEngineClockPLL_Output; //In 10Khz unit*
2702 … ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit*
2703 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2705 …ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency…
2712 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2717 …USHORT usReserved11; //Was usMaxPixelClock; //In 10Khz uni…
2718 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2719 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
2722 USHORT usCoreReferenceClock; //In 10Khz unit
2723 USHORT usMemoryReferenceClock; //In 10Khz unit
2724 …USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mod…
2750 ULONG ulBootUpEngineClock; //in 10kHz unit
2751 ULONG ulBootUpMemoryClock; //in 10kHz unit
2752 ULONG ulMaxSystemMemoryClock; //in 10kHz unit
2753 ULONG ulMinSystemMemoryClock; //in 10kHz unit
2762 … usCapabilityFlag; //Bit0=1 indicates the fake HDMI support,Bit1=0/1 …
2763 //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card
2764 //Bit[4]==1: P/2 mode, ==0: P/1 mode
2771 …UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is re…
2799 …uty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0
2822 ULONG ulBootUpEngineClock; //in 10kHz unit
2824 ULONG ulBootUpUMAClock; //in 10kHz unit
2825 ULONG ulBootUpSidePortClock; //in 10kHz unit
2826 ULONG ulMinSidePortClock; //in 10kHz unit
2833 …UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is rese…
2843 ULONG ulHTLinkFreq; //in 10Khz
2850 ULONG ulHighVoltageHTLinkFreq; // in 10Khz
2851 ULONG ulLowVoltageHTLinkFreq; // in 10Khz
2862 ulBootUpEngineClock: Boot-up Engine Clock in 10Khz;
2863 ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present
2864 ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not …
2867 Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode;
2868 Bit[1]=1: system boots up at AMD overdrived state or user customized mode. In this case, driver wi…
2870 Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used.
2871 Bit[3]=1: Only one power state(Performance) will be supported.
2873 Bit[4]=1: CLMC is supported and enabled on current system.
2875 Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT…
2877 Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v…
2879 Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using l…
2881 Bit[8]=1: CDLF is supported and enabled on current system.
2883 Bit[9]=1: DLL Shut Down feature is enabled on current system.
2888 ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion;
2892 …fig of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; b…
2893 …me DDI slot/connector on docking station (bit 4=1 lane 3:0; bit 5=1 lane 7:4; bit 6=1 lane 11:8; b…
2917 ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Pharaoh, other bits rese…
2924 …sMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1
2929 ulHTLinkFreq: Bootup HT link Frequency in 10Khz.
2957 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__GRIFFIN 1
2995 ULONG ulBootUpEngineClock; //in 10kHz unit
2996 …ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the sourc…
2997 …ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relation…
2998 ULONG ulBootUpUMAClock; //in 10kHz unit
3016 …UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is rese…
3059 #define ATOM_DIGITAL_ENCODER 1
3087 #define ATOM_MAX_SUPPORTED_DEVICE_INFO (ATOM_DEVICE_DFP3_INDEX+1)
3089 #define ATOM_MAX_SUPPORTED_DEVICE_INFO_3 (ATOM_DEVICE_DFP5_INDEX + 1 )
3091 #define ATOM_MAX_SUPPORTED_DEVICE (ATOM_DEVICE_RESERVEDF_INDEX+1)
3153 // Bits0 = 0 - no CRT1 support= 1- CRT1 is supported
3154 // Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported
3155 // Bit 2 = 0 - no TV1 support= 1- TV1 is supported
3156 // Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported
3157 // Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported
3158 // Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported
3159 // Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported
3160 // Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported
3161 // Bit 8 = 0 - no CV support= 1- CV is supported
3162 // Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported
3163 // Bit 10 = 0 - no DFP4 support= 1- DFP4 is supported
3164 // Bit 11 = 0 - no DFP5 support= 1- DFP5 is supported
3174 // [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection)
3176 // [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use
3184 UCHAR bfHW_Capable:1;
3190 UCHAR bfHW_Capable:1;
3244 USHORT RGB888:1;
3245 USHORT DoubleClock:1;
3246 USHORT Interlace:1;
3247 USHORT CompositeSync:1;
3248 USHORT V_ReplicationBy2:1;
3249 USHORT H_ReplicationBy2:1;
3250 USHORT VerticalCutOff:1;
3251 USHORT VSyncPolarity:1; //0=Active High, 1=Active Low
3252 USHORT HSyncPolarity:1; //0=Active High, 1=Active Low
3253 USHORT HorizontalCutOff:1;
3255 USHORT HorizontalCutOff:1;
3256 USHORT HSyncPolarity:1; //0=Active High, 1=Active Low
3257 USHORT VSyncPolarity:1; //0=Active High, 1=Active Low
3258 USHORT VerticalCutOff:1;
3259 USHORT H_ReplicationBy2:1;
3260 USHORT V_ReplicationBy2:1;
3261 USHORT CompositeSync:1;
3262 USHORT Interlace:1;
3263 USHORT DoubleClock:1;
3264 USHORT RGB888:1;
3286 #define ATOM_HSYNC_POLARITY 0x02 //0=Active High, 1=Active Low
3287 #define ATOM_VSYNC_POLARITY 0x04 //0=Active High, 1=Active Low
3376 USHORT usPixelClock; //in 10Khz unit
3416 //ucTableFormatRevision=1
3417 //ucTableContentRevision=1
3427 …UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:88…
3428 … // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
3429 … // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}
3430 … // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}
3436 //ucTableFormatRevision=1
3447 …UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:88…
3448 … // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
3449 … // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}
3450 … // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}
3479 // 0 0 1 - 6 Bits per Primary Color
3480 // 0 1 0 - 8 Bits per Primary Color
3481 // 0 1 1 - 10 Bits per Primary Color
3482 // 1 0 0 - 12 Bits per Primary Color
3483 // 1 0 1 - 14 Bits per Primary Color
3484 // 1 1 0 - 16 Bits per Primary Color
3485 // 1 1 1 - Reserved
3489 // Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled}
3498 // ucTableFormatRevision=1
3509 // Bit0: {=0:single, =1:dual},
3510 … // Bit1: {=0:LDI format for RGB888, =1 FPDI format for RGB888} // was {=0:666RGB, =1:888RGB},
3522 … // Bit2: a quick reference whether an embadded panel (LCD1 ) is LVDS (0) or eDP (1)
3562 // 0 0 1 - 6 Bits per Primary Color
3563 // 0 1 0 - 8 Bits per Primary Color
3564 // 0 1 1 - 10 Bits per Primary Color
3565 // 1 0 0 - 12 Bits per Primary Color
3566 // 1 0 1 - 14 Bits per Primary Color
3567 // 1 1 0 - 16 Bits per Primary Color
3568 // 1 1 1 - Reserved
3610 #define LCD_MODE_CAP_BL_OFF 1
3618 UCHAR ucFakeEDIDString[1]; // This actually has ucFakeEdidLength elements.
3628 #define LCD_MODE_PATCH_RECORD_MODE_TYPE 1
3638 //ucTableFormatRevision=1
3643 … ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1…
3679 //ATOM_TV_NTSC 1
3728 UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP
3729 …UCHAR ucMaxDownSpread; //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change acc…
3826 // ucTableFormatRevision=1,ucTableContentRevision=4, the structure remains
3846 #define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO 1
3896 ATOM_GPIO_PIN_ASSIGNMENT asGPIO_Pin[1];
3958 UCHAR ucPinActiveState; //ucPinActiveState: Bit0=1 active high, =0 active low
3973 //ucTableContentRevision=1
4023 …USHORT usGraphicObjIds[1]; //1st Encoder Obj source from GPU to las…
4032 … //usGraphicObjIds[0]= GPU internal encoder, usGraphicObjIds[1]= external encoder
4040 ATOM_DISPLAY_OBJECT_PATH asDispPath[1];
4056 ATOM_OBJECT asObjects[1];
4062 USHORT usSrcObjectID[1];
4064 USHORT usDstObjectID[1];
4071 #define EXT_HPDPIN_LUTINDEX_1 1
4078 #define MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES (EXT_HPDPIN_LUTINDEX_7+1)
4081 #define EXT_AUXDDC_LUTINDEX_1 1
4088 #define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES (EXT_AUXDDC_LUTINDEX_7+1)
4092 //Bit[1:0]: Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: fro…
4093 //Bit[3:2]: Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: fro…
4094 //Bit[5:4]: Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: fro…
4095 //Bit[7:6]: Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: fro…
4112 //Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: …
4113 //Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: …
4114 //Bit[5:4]: Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: …
4115 //Bit[7:6]: Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: …
4144 … // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted
4165 …UCHAR ucFixDPVoltageSwing; // usCaps[1]=1, this indicate DP_L…
4177 #define ATOM_I2C_RECORD_TYPE 1
4236 …ATOM_CONNECTOR_DEVICE_TAG asDeviceTag[1]; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT"…
4244 …UCHAR ucConfigGPIOState; //Set to 1 when it's active high to enable external …
4253 UCHAR ucCTL1GPIOState; //Set to 1 when it's active high
4255 UCHAR ucCTL2GPIOState; //Set to 1 when it's active high
4257 UCHAR ucCTL3GPIOState; //Set to 1 when it's active high
4266 …UCHAR ucTVActiveState; //Indicating when the pin==0 or 1 when TV is c…
4273 UCHAR ucTMSGPIOState; //Set to 1 when it's active high
4275 UCHAR ucTCKGPIOState; //Set to 1 when it's active high
4277 UCHAR ucTDOGPIOState; //Set to 1 when it's active high
4279 UCHAR ucTDIGPIOState; //Set to 1 when it's active high
4296 …ATOM_GPIO_PIN_CONTROL_PAIR asGpio[1]; // the real gpio pin pair determined by number…
4313 #define ATOM_GPIO_INDEX_GLSYNC_HSYNC 1
4342 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable
4343 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability.
4345 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability.
4346 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable
4354 #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1
4384 … //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: mu…
4433 #define CONNECTOR_TYPE_DVI_D 1
4447 ATOM_CONNECTOR_LAYOUT_INFO asConnInfo[1];
4476 USHORT usVoltageBaseLevel; // In number of 1mv unit
4477 …USHORT usVoltageStep; // Indicating in how many mv increament is one step, 1mv …
4479 UCHAR ucFlag; // bit0=0 :step is 1mv =1 0.5mv
4603 VOLTAGE_LUT_ENTRY asVolI2cLut[1]; // end with 0xff
4608 #define VOLTAGE_DATA_TWO_BYTE 1
4618 VOLTAGE_LUT_ENTRY_V2 asVolGpioLut[1];
4628 LEAKAGE_VOLTAGE_LUT_ENTRY_V2 asLeakageIdLut[1];
4639 // 1:0 – offset trim,
4671 #define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE 1
4672 #define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE 1
4756 ATOM_POWER_SOURCE_OBJECT asPwrObj[1];
4775 …mSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
4780 …upportedSCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
4786 #define ATOM_IGP_INFO_V6_SYSTEM_CONFIG__PCIE_POWER_GATING_ENABLE 1 // refer to ul…
4864 ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equa…
4865 ulDentistVCOFreq: Dentist VCO clock in 10kHz unit.
4866 ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit.
4881 =1: TMDS/HDMI Coherent Mode use signel PLL mode.
4883 =1: Disable HW AUX mode dettion logic
4890 …1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determin…
4891 … VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,
4897 … VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1
4906 ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on W…
4908 =1: PCIE Power Gating Enabled
4909 Bit[1]=0: DDR-DLL shut-down feature disabled.
4910 1: DDR-DLL shut-down feature enabled.
4912 … 1: DDR-PLL Power down feature enabled.
4924 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved.
4931 … Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz.
4932 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
4935 usPCIEClkSSPercentage: PCIE Clock Spred Spectrum Percentage in unit 0.01%; 100 mean 1%.
4936 usPCIEClkSSType: PCIE Clock Spred Spectrum Type. 0 for Down spread(default); 1 for…
4939 usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, …
4941 usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, u…
4944 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1:…
4945 …panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and uppe…
4946 … [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color
4947 …it3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc paramete…
4948 …y of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active l…
5079 ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equa…
5080 ulDentistVCOFreq: Dentist VCO clock in 10kHz unit.
5081 ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit.
5093 ulOtherDisplayMisc: bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b )…
5094 … =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS.
5095 … bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS
5096 … =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS
5098 … =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS
5100 …=1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD pane…
5102 =1: TMDS/HDMI Coherent Mode use signel PLL mode.
5103 bit[1]=0: DP mode use cascade PLL mode ( New for Trinity )
5104 =1: DP mode use single PLL mode
5106 =1: Disable AUX HW mode detection logic
5114 …1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determin…
5115 … VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,
5121 … VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1
5130 ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on W…
5132 =1: PCIE Power Gating Enabled
5133 Bit[1]=0: DDR-DLL shut-down feature disabled.
5134 1: DDR-DLL shut-down feature enabled.
5136 … 1: DDR-PLL Power down feature enabled.
5150 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved.
5157 … Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz.
5158 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
5161 usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%.
5162 usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 fo…
5165 usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, …
5167 usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, u…
5170 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1:…
5171 …panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and uppe…
5172 … [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color
5173 …it3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc paramete…
5174 …y of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active l…
5175 …[bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to ove…
5176 ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite Tr…
5209 ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB ps…
5280 ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equa…
5281 ulDentistVCOFreq: Dentist VCO clock in 10kHz unit.
5282 ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit.
5296 … bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS.
5297 … =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS.
5298 … bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS
5299 … =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS
5301 … =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS
5303 …=1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD pane…
5307 =1: Disable AUX HW mode detection logic
5309 =1: Enable DFS bypass feature
5315 …1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determin…
5316 … VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,
5322 … VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1
5332 =1: PCIE Power Gating Enabled
5333 Bit[1]=0: DDR-DLL shut-down feature disabled.
5334 1: DDR-DLL shut-down feature enabled.
5336 1: DDR-PLL Power down feature enabled.
5338 =1: GNB DPM is enabled
5349 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3;=5:GDDR5; [7:4] is reserved.
5357 …eed while memory runs in self-refresh state, used to calculate self-refresh latency. Unit in 10kHz.
5361 usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%.
5362 usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 fo…
5365 usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, …
5367 usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, u…
5375 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1:…
5376 …panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and uppe…
5377 … [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color
5378 …it3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc paramete…
5379 …y of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active l…
5380 …[bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to ove…
5381 ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite Tr…
5416 ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB P-…
5436 #define ICS91719 1
5443 …UCHAR ucI2CData[1]; //I2C data in bytes, s…
5454 ATOM_I2C_DATA_RECORD asI2CData[1];
5461 ATOM_I2C_DEVICE_SETUP_INFO asI2CSetup[1];
5472 ULONG ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz
5474 USHORT usSpreadRateInKhz; //in unit of kHz, modulation freq
5476 UCHAR ucSpreadSpectrumMode; //Bit1=0 Down Spread,=1 Center Spread.
5482 #define ASIC_INTERNAL_MEMORY_SS 1
5497 … ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
5502 … ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1…
5523 ATOM_ASIC_SS_ASSIGNMENT_V2 asSpreadSpectrum[1]; //this is point only.
5528 … ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
5533 … ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1…
5545 ATOM_ASIC_SS_ASSIGNMENT_V3 asSpreadSpectrum[1]; //this is pointer only.
5551 #define ATOM_ROM_LOCATION_DEF 1
5609 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1
5882 #define ATOM_S6_SCALER_CHANGE_SHIFT 1
6004 ULONG ulTargetMemoryClock; //In 10Khz unit
6030 UCHAR ucPadding[1];
6036 #define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION 1
6059 UCHAR ucSurface; // Surface 1 or 2
6067 UCHAR ucSurface; // Surface 1 or 2
6076 UCHAR ucSurface; // Surface 1 or 2
6088 UCHAR ucSurface; // Surface 1 or 2
6139 #define PALETTE_DATA_AUTO_FILL 1
6153 #define HDP1_INTERRUPT_ID 1
6162 #define INTERRUPT_SERVICE_GEN_SW_INT 1
6166 #define INTERRUPT_STATUS__INT_TRIGGER 1
6179 #define INDIRECT_IO_PLL 1
6285 ULONG aulMemData[1];
6298 ATOM_INIT_REG_INDEX_FORMAT asRegIndexBuf[1];
6299 ATOM_MEMORY_SETTING_DATA_BLOCK asRegDataBuf[1];
6311 #define INDEX_ACCESS_RANGE_BEGIN (VALUE_DWORD + 1)
6312 #define INDEX_ACCESS_RANGE_END (INDEX_ACCESS_RANGE_BEGIN + 1)
6313 #define VALUE_INDEX_ACCESS_SINGLE (INDEX_ACCESS_RANGE_END + 1)
6443 …ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below t…
6479 …ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below t…
6512 …ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below t…
6563 UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8
6605 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
6608 …ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1…
6626 …UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
6647 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
6650 …ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1…
6662 …UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
6678 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
6681 …ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1…
6693 …UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
6723 …UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
6757 …teRemap; // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =…
6818 #define SW_I2C_IO_GET 1
6830 #define SW_I2C_CNTL_WRITE 1
6926 UCHAR ReservedForPageFunction;//db 1 ; reserved for page function
7015 UCHAR ucEncoderID; //available 1st encoder ( default )
7043 ASIC_TRANSMITTER_INFO asTransmitterInfo[1];
7044 ASIC_ENCODER_INFO asEncoderInfo[1];
7053 ASIC_TRANSMITTER_INFO asTransmitterInfo[1];
7054 ASIC_ENCODER_INFO asEncoderInfo[1];
7075 UCHAR ucEncoderID; // available 1st encoder ( default )
7095 ASIC_TRANSMITTER_INFO_V2 asTransmitterInfo[1]; // for alligment only
7104 CLOCK_SRC_XO_IN=1,
7142 …UCHAR ucHPD_ID; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, …
7239 #define HW_I2C_WRITE 1
7265 #define ATOM_FEATURE_NOT_SUPPORTED 1
7278 UCHAR ucHWBlkInst; // HW block instance, 0, 1, 2, ...
7288 #define SELECT_DISP_PLL 1
7327 ULONG ulAnalogSetting[1];
7332 CLOCK_CONDITION_SETTING_ENTRY asClkCondSettingEntry[1];
7349 PHY_CONDITION_REG_VAL asRegVal[1];
7355 PHY_CONDITION_REG_VAL_V2 asRegVal[1];
7362 PHY_CONDITION_REG_INFO asAnalogSetting[1];
7369 PHY_CONDITION_REG_INFO_V2 asAnalogSetting[1];
7381 #define GFX_HARVESTING_RB_ID 1
7414 USHORT usMaxFrequency; // in 10kHz unit
7432 …UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active L…
7437 …UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active L…
7442 …UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active L…
7451 // = 1 - VGA connector
7466 // = 1 - DACA
7545 USHORT usMaxFrequency; // in 10Khz
7553 UCHAR ucPadding[1];
7559 UCHAR ucPadding[1];
7585 #define ATOM_XTMDS_ASIC_SI164_ID 1
7599 …UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,…
7643 #define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM,…
7653 #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Grou…
7669 //ucTableFormatRevision=1
7670 //ucTableContentRevision=1
7686 //ucTableContentRevision=1
7917 #pragma pack(1)
7967 UCHAR VbiosContent[1];
7972 UCHAR Lib1Content[1];