Lines Matching +full:level +full:- +full:low

1 /* SPDX-License-Identifier: GPL-2.0 */
6  * (C) COPYRIGHT 2010-2018 ARM Limited. All rights reserved.
12 #define GPU_L2_FEATURES			0x004	/* (RO) Level 2 cache features */
87 #define GPU_SHADER_PRESENT_LO		0x100	/* (RO) Shader core present bitmap, low word */
89 #define GPU_TILER_PRESENT_LO		0x110	/* (RO) Tiler core present bitmap, low word */
92 #define GPU_L2_PRESENT_LO		0x120	/* (RO) Level 2 cache present bitmap, low word */
93 #define GPU_L2_PRESENT_HI		0x124	/* (RO) Level 2 cache present bitmap, high word */
99 #define GPU_STACK_PRESENT_LO		0xE00   /* (RO) Core stack present bitmap, low word */
102 #define SHADER_READY_LO			0x140	/* (RO) Shader core ready bitmap, low word */
105 #define TILER_READY_LO			0x150	/* (RO) Tiler core ready bitmap, low word */
108 #define L2_READY_LO			0x160	/* (RO) Level 2 cache ready bitmap, low word */
109 #define L2_READY_HI			0x164	/* (RO) Level 2 cache ready bitmap, high word */
111 #define STACK_READY_LO			0xE10   /* (RO) Core stack ready bitmap, low word */
115 #define SHADER_PWRON_LO			0x180	/* (WO) Shader core power on bitmap, low word */
118 #define TILER_PWRON_LO			0x190	/* (WO) Tiler core power on bitmap, low word */
121 #define L2_PWRON_LO			0x1A0	/* (WO) Level 2 cache power on bitmap, low word */
122 #define L2_PWRON_HI			0x1A4	/* (WO) Level 2 cache power on bitmap, high word */
124 #define STACK_PWRON_LO			0xE20   /* (RO) Core stack power on bitmap, low word */
128 #define SHADER_PWROFF_LO		0x1C0	/* (WO) Shader core power off bitmap, low word */
131 #define TILER_PWROFF_LO			0x1D0	/* (WO) Tiler core power off bitmap, low word */
134 #define L2_PWROFF_LO			0x1E0	/* (WO) Level 2 cache power off bitmap, low word */
135 #define L2_PWROFF_HI			0x1E4	/* (WO) Level 2 cache power off bitmap, high word */
137 #define STACK_PWROFF_LO			0xE30   /* (RO) Core stack power off bitmap, low word */
141 #define SHADER_PWRTRANS_LO		0x200	/* (RO) Shader core power transition bitmap, low word */
144 #define TILER_PWRTRANS_LO		0x210	/* (RO) Tiler core power transition bitmap, low word */
147 #define L2_PWRTRANS_LO			0x220	/* (RO) Level 2 cache power transition bitmap, low word */
148 #define L2_PWRTRANS_HI			0x224	/* (RO) Level 2 cache power transition bitmap, high word */
150 #define STACK_PWRTRANS_LO		0xE40   /* (RO) Core stack power transition bitmap, low word */
154 #define SHADER_PWRACTIVE_LO		0x240	/* (RO) Shader core active bitmap, low word */
157 #define TILER_PWRACTIVE_LO		0x250	/* (RO) Tiler core active bitmap, low word */
160 #define L2_PWRACTIVE_LO			0x260	/* (RO) Level 2 cache active bitmap, low word */
161 #define L2_PWRACTIVE_HI			0x264	/* (RO) Level 2 cache active bitmap, high word */
281 						   (deprecated - only for use with T60x) */
290 …LO(as)		(MMU_AS(as) + 0x00) /* (RW) Translation Table Base Address for address space n, low word */
292 #define AS_MEMATTR_LO(as)		(MMU_AS(as) + 0x08) /* (RW) Memory attributes for address space n, low w…
294 …S_LOCKADDR_LO(as)		(MMU_AS(as) + 0x10) /* (RW) Lock region address for address space n, low word */
298 #define AS_FAULTADDRESS_LO(as)		(MMU_AS(as) + 0x20) /* (RO) Fault Address for address space n, low …
302 …O(as)		(MMU_AS(as) + 0x30) /* (RW) Translation table configuration for address space n, low word */
304 …TEXTRA_LO(as)		(MMU_AS(as) + 0x38) /* (RO) Secondary fault address for address space n, low word */
329 #define gpu_write(dev, reg, data) writel(data, dev->iomem + reg)
330 #define gpu_read(dev, reg) readl(dev->iomem + reg)