Lines Matching +full:high +full:- +full:level

1 /* SPDX-License-Identifier: GPL-2.0 */
6  * (C) COPYRIGHT 2010-2018 ARM Limited. All rights reserved.
12 #define GPU_L2_FEATURES			0x004	/* (RO) Level 2 cache features */
88 #define GPU_SHADER_PRESENT_HI		0x104	/* (RO) Shader core present bitmap, high word */
90 #define GPU_TILER_PRESENT_HI		0x114	/* (RO) Tiler core present bitmap, high word */
92 #define GPU_L2_PRESENT_LO		0x120	/* (RO) Level 2 cache present bitmap, low word */
93 #define GPU_L2_PRESENT_HI		0x124	/* (RO) Level 2 cache present bitmap, high word */
100 #define GPU_STACK_PRESENT_HI		0xE04   /* (RO) Core stack present bitmap, high word */
103 #define SHADER_READY_HI			0x144	/* (RO) Shader core ready bitmap, high word */
106 #define TILER_READY_HI			0x154	/* (RO) Tiler core ready bitmap, high word */
108 #define L2_READY_LO			0x160	/* (RO) Level 2 cache ready bitmap, low word */
109 #define L2_READY_HI			0x164	/* (RO) Level 2 cache ready bitmap, high word */
112 #define STACK_READY_HI			0xE14   /* (RO) Core stack ready bitmap, high word */
116 #define SHADER_PWRON_HI			0x184	/* (WO) Shader core power on bitmap, high word */
119 #define TILER_PWRON_HI			0x194	/* (WO) Tiler core power on bitmap, high word */
121 #define L2_PWRON_LO			0x1A0	/* (WO) Level 2 cache power on bitmap, low word */
122 #define L2_PWRON_HI			0x1A4	/* (WO) Level 2 cache power on bitmap, high word */
125 #define STACK_PWRON_HI			0xE24   /* (RO) Core stack power on bitmap, high word */
129 #define SHADER_PWROFF_HI		0x1C4	/* (WO) Shader core power off bitmap, high word */
132 #define TILER_PWROFF_HI			0x1D4	/* (WO) Tiler core power off bitmap, high word */
134 #define L2_PWROFF_LO			0x1E0	/* (WO) Level 2 cache power off bitmap, low word */
135 #define L2_PWROFF_HI			0x1E4	/* (WO) Level 2 cache power off bitmap, high word */
138 #define STACK_PWROFF_HI			0xE34   /* (RO) Core stack power off bitmap, high word */
142 #define SHADER_PWRTRANS_HI		0x204	/* (RO) Shader core power transition bitmap, high word */
145 #define TILER_PWRTRANS_HI		0x214	/* (RO) Tiler core power transition bitmap, high word */
147 #define L2_PWRTRANS_LO			0x220	/* (RO) Level 2 cache power transition bitmap, low word */
148 #define L2_PWRTRANS_HI			0x224	/* (RO) Level 2 cache power transition bitmap, high word */
151 #define STACK_PWRTRANS_HI		0xE44   /* (RO) Core stack power transition bitmap, high word */
155 #define SHADER_PWRACTIVE_HI		0x244	/* (RO) Shader core active bitmap, high word */
158 #define TILER_PWRACTIVE_HI		0x254	/* (RO) Tiler core active bitmap, high word */
160 #define L2_PWRACTIVE_LO			0x260	/* (RO) Level 2 cache active bitmap, low word */
161 #define L2_PWRACTIVE_HI			0x264	/* (RO) Level 2 cache active bitmap, high word */
281 						   (deprecated - only for use with T60x) */
291 …I(as)		(MMU_AS(as) + 0x04) /* (RW) Translation Table Base Address for address space n, high word */
293 #define AS_MEMATTR_HI(as)		(MMU_AS(as) + 0x0C) /* (RW) Memory attributes for address space n, high …
295 …_LOCKADDR_HI(as)		(MMU_AS(as) + 0x14) /* (RW) Lock region address for address space n, high word */
299 #define AS_FAULTADDRESS_HI(as)		(MMU_AS(as) + 0x24) /* (RO) Fault Address for address space n, high…
303 …(as)		(MMU_AS(as) + 0x34) /* (RW) Translation table configuration for address space n, high word */
305 …EXTRA_HI(as)		(MMU_AS(as) + 0x3C) /* (RO) Secondary fault address for address space n, high word */
329 #define gpu_write(dev, reg, data) writel(data, dev->iomem + reg)
330 #define gpu_read(dev, reg) readl(dev->iomem + reg)