Lines Matching +full:0 +full:x44
21 #define DSI_CMD2BKX_SEL 0xFF
24 #define DSI_CMD2_BK0_PVGAMCTRL 0xB0 /* Positive Voltage Gamma Control */
25 #define DSI_CMD2_BK0_NVGAMCTRL 0xB1 /* Negative Voltage Gamma Control */
26 #define DSI_CMD2_BK0_LNESET 0xC0 /* Display Line setting */
27 #define DSI_CMD2_BK0_PORCTRL 0xC1 /* Porch control */
28 #define DSI_CMD2_BK0_INVSEL 0xC2 /* Inversion selection, Frame Rate Control */
31 #define DSI_CMD2_BK1_VRHS 0xB0 /* Vop amplitude setting */
32 #define DSI_CMD2_BK1_VCOM 0xB1 /* VCOM amplitude setting */
33 #define DSI_CMD2_BK1_VGHSS 0xB2 /* VGH Voltage setting */
34 #define DSI_CMD2_BK1_TESTCMD 0xB3 /* TEST Command Setting */
35 #define DSI_CMD2_BK1_VGLS 0xB5 /* VGL Voltage setting */
36 #define DSI_CMD2_BK1_PWCTLR1 0xB7 /* Power Control 1 */
37 #define DSI_CMD2_BK1_PWCTLR2 0xB8 /* Power Control 2 */
38 #define DSI_CMD2_BK1_SPD1 0xC1 /* Source pre_drive timing set1 */
39 #define DSI_CMD2_BK1_SPD2 0xC2 /* Source EQ2 Setting */
40 #define DSI_CMD2_BK1_MIPISET1 0xD0 /* MIPI Setting 1 */
46 * BIT[1:0]...BKXSEL
50 * 0:00 = Command2 disable
52 #define DSI_CMD2BK0_SEL 0x10
53 #define DSI_CMD2BK1_SEL 0x11
54 #define DSI_CMD2BK3_SEL 0x13
55 #define DSI_CMD2BKX_SEL_NONE 0x00
59 #define DSI_CMD2_BK0_GAMCTRL_VC0_MASK GENMASK(3, 0)
60 #define DSI_CMD2_BK0_GAMCTRL_VC4_MASK GENMASK(5, 0)
61 #define DSI_CMD2_BK0_GAMCTRL_VC8_MASK GENMASK(5, 0)
62 #define DSI_CMD2_BK0_GAMCTRL_VC16_MASK GENMASK(4, 0)
63 #define DSI_CMD2_BK0_GAMCTRL_VC24_MASK GENMASK(4, 0)
64 #define DSI_CMD2_BK0_GAMCTRL_VC52_MASK GENMASK(3, 0)
65 #define DSI_CMD2_BK0_GAMCTRL_VC80_MASK GENMASK(5, 0)
66 #define DSI_CMD2_BK0_GAMCTRL_VC108_MASK GENMASK(3, 0)
67 #define DSI_CMD2_BK0_GAMCTRL_VC147_MASK GENMASK(3, 0)
68 #define DSI_CMD2_BK0_GAMCTRL_VC175_MASK GENMASK(5, 0)
69 #define DSI_CMD2_BK0_GAMCTRL_VC203_MASK GENMASK(3, 0)
70 #define DSI_CMD2_BK0_GAMCTRL_VC231_MASK GENMASK(4, 0)
71 #define DSI_CMD2_BK0_GAMCTRL_VC239_MASK GENMASK(4, 0)
72 #define DSI_CMD2_BK0_GAMCTRL_VC247_MASK GENMASK(5, 0)
73 #define DSI_CMD2_BK0_GAMCTRL_VC251_MASK GENMASK(5, 0)
74 #define DSI_CMD2_BK0_GAMCTRL_VC255_MASK GENMASK(4, 0)
75 #define DSI_CMD2_BK0_LNESET_LINE_MASK GENMASK(6, 0)
77 #define DSI_CMD2_BK0_LNESET_LINEDELTA GENMASK(1, 0)
78 #define DSI_CMD2_BK0_PORCTRL_VBP_MASK GENMASK(7, 0)
79 #define DSI_CMD2_BK0_PORCTRL_VFP_MASK GENMASK(7, 0)
81 #define DSI_CMD2_BK0_INVSEL_NLINV_MASK GENMASK(2, 0)
82 #define DSI_CMD2_BK0_INVSEL_RTNI_MASK GENMASK(4, 0)
85 #define DSI_CMD2_BK1_VRHA_MASK GENMASK(7, 0)
86 #define DSI_CMD2_BK1_VCOM_MASK GENMASK(7, 0)
87 #define DSI_CMD2_BK1_VGHSS_MASK GENMASK(3, 0)
90 #define DSI_CMD2_BK1_VGLS_MASK GENMASK(3, 0)
93 #define DSI_CMD2_BK1_PWRCTRL1_APOS_MASK GENMASK(1, 0)
95 #define DSI_CMD2_BK1_PWRCTRL2_AVCL_MASK GENMASK(1, 0)
97 #define DSI_CMD2_BK1_SPD1_T2D_MASK GENMASK(3, 0)
99 #define DSI_CMD2_BK1_SPD2_T3D_MASK GENMASK(3, 0)
107 OP_BIAS_OFF = 0,
176 { -7060, 0x0 }, { -7470, 0x1 }, in st7701_vgls_map()
177 { -7910, 0x2 }, { -8140, 0x3 }, in st7701_vgls_map()
178 { -8650, 0x4 }, { -8920, 0x5 }, in st7701_vgls_map()
179 { -9210, 0x6 }, { -9510, 0x7 }, in st7701_vgls_map()
180 { -9830, 0x8 }, { -10170, 0x9 }, in st7701_vgls_map()
181 { -10530, 0xa }, { -10910, 0xb }, in st7701_vgls_map()
182 { -11310, 0xc }, { -11730, 0xd }, in st7701_vgls_map()
183 { -12200, 0xe }, { -12690, 0xf } in st7701_vgls_map()
187 for (i = 0; i < ARRAY_SIZE(map); i++) in st7701_vgls_map()
191 return 0; in st7701_vgls_map()
201 ST7701_DSI(st7701, MIPI_DCS_SOFT_RESET, 0x00); in st7701_init_sequence()
206 ST7701_DSI(st7701, MIPI_DCS_EXIT_SLEEP_MODE, 0x00); in st7701_init_sequence()
212 0x77, 0x01, 0x00, 0x00, DSI_CMD2BK0_SEL); in st7701_init_sequence()
219 * Line[6:0]: select number of vertical lines of the TFT matrix in in st7701_init_sequence()
222 * Line_delta[1:0]: add 0/2/4/6 extra lines to line count selected in st7701_init_sequence()
223 * using Line[6:0] in st7701_init_sequence()
226 * LN = ((Line[6:0] + 1) * 8) + (LDE_EN ? Line_delta[1:0] * 2 : 0) in st7701_init_sequence()
230 (linecountrem2 ? DSI_CMD2_BK0_LNESET_LDE_EN : 0), in st7701_init_sequence()
239 * PCLK = 512 + (RTNI[4:0] * 16) in st7701_init_sequence()
251 0x77, 0x01, 0x00, 0x00, DSI_CMD2BK1_SEL); in st7701_init_sequence()
253 /* Vop = 3.5375V + (VRHA[7:0] * 0.0125V) */ in st7701_init_sequence()
258 /* Vcom = 0.1V + (VCOM[7:0] * 0.0125V) */ in st7701_init_sequence()
263 /* Vgh = 11.5V + (VGHSS[7:0] * 0.5V) */ in st7701_init_sequence()
286 /* Avdd = 6.2V + (AVDD[1:0] * 0.2V) , Avcl = -4.4V - (AVCL[1:0] * 0.2V) */ in st7701_init_sequence()
293 /* T2D = 0.2us * T2D[3:0] */ in st7701_init_sequence()
299 /* T3D = 4us + (0.8us * T3D[3:0]) */ in st7701_init_sequence()
307 (desc->eot_en ? DSI_CMD2_BK1_MIPISET1_EOT_EN : 0)); in st7701_init_sequence()
316 ST7701_DSI(st7701, 0xE0, 0x00, 0x00, 0x02); in ts8550b_gip_sequence()
317 ST7701_DSI(st7701, 0xE1, 0x0B, 0x00, 0x0D, 0x00, 0x0C, 0x00, 0x0E, in ts8550b_gip_sequence()
318 0x00, 0x00, 0x44, 0x44); in ts8550b_gip_sequence()
319 ST7701_DSI(st7701, 0xE2, 0x33, 0x33, 0x44, 0x44, 0x64, 0x00, 0x66, in ts8550b_gip_sequence()
320 0x00, 0x65, 0x00, 0x67, 0x00, 0x00); in ts8550b_gip_sequence()
321 ST7701_DSI(st7701, 0xE3, 0x00, 0x00, 0x33, 0x33); in ts8550b_gip_sequence()
322 ST7701_DSI(st7701, 0xE4, 0x44, 0x44); in ts8550b_gip_sequence()
323 ST7701_DSI(st7701, 0xE5, 0x0C, 0x78, 0x3C, 0xA0, 0x0E, 0x78, 0x3C, in ts8550b_gip_sequence()
324 0xA0, 0x10, 0x78, 0x3C, 0xA0, 0x12, 0x78, 0x3C, 0xA0); in ts8550b_gip_sequence()
325 ST7701_DSI(st7701, 0xE6, 0x00, 0x00, 0x33, 0x33); in ts8550b_gip_sequence()
326 ST7701_DSI(st7701, 0xE7, 0x44, 0x44); in ts8550b_gip_sequence()
327 ST7701_DSI(st7701, 0xE8, 0x0D, 0x78, 0x3C, 0xA0, 0x0F, 0x78, 0x3C, in ts8550b_gip_sequence()
328 0xA0, 0x11, 0x78, 0x3C, 0xA0, 0x13, 0x78, 0x3C, 0xA0); in ts8550b_gip_sequence()
329 ST7701_DSI(st7701, 0xEB, 0x02, 0x02, 0x39, 0x39, 0xEE, 0x44, 0x00); in ts8550b_gip_sequence()
330 ST7701_DSI(st7701, 0xEC, 0x00, 0x00); in ts8550b_gip_sequence()
331 ST7701_DSI(st7701, 0xED, 0xFF, 0xF1, 0x04, 0x56, 0x72, 0x3F, 0xFF, in ts8550b_gip_sequence()
332 0xFF, 0xFF, 0xFF, 0xF3, 0x27, 0x65, 0x40, 0x1F, 0xFF); in ts8550b_gip_sequence()
337 ST7701_DSI(st7701, 0xEE, 0x42); in dmt028vghmcmi_1a_gip_sequence()
338 ST7701_DSI(st7701, 0xE0, 0x00, 0x00, 0x02); in dmt028vghmcmi_1a_gip_sequence()
340 ST7701_DSI(st7701, 0xE1, in dmt028vghmcmi_1a_gip_sequence()
341 0x04, 0xA0, 0x06, 0xA0, in dmt028vghmcmi_1a_gip_sequence()
342 0x05, 0xA0, 0x07, 0xA0, in dmt028vghmcmi_1a_gip_sequence()
343 0x00, 0x44, 0x44); in dmt028vghmcmi_1a_gip_sequence()
344 ST7701_DSI(st7701, 0xE2, in dmt028vghmcmi_1a_gip_sequence()
345 0x00, 0x00, 0x00, 0x00, in dmt028vghmcmi_1a_gip_sequence()
346 0x00, 0x00, 0x00, 0x00, in dmt028vghmcmi_1a_gip_sequence()
347 0x00, 0x00, 0x00, 0x00); in dmt028vghmcmi_1a_gip_sequence()
348 ST7701_DSI(st7701, 0xE3, in dmt028vghmcmi_1a_gip_sequence()
349 0x00, 0x00, 0x22, 0x22); in dmt028vghmcmi_1a_gip_sequence()
350 ST7701_DSI(st7701, 0xE4, 0x44, 0x44); in dmt028vghmcmi_1a_gip_sequence()
351 ST7701_DSI(st7701, 0xE5, in dmt028vghmcmi_1a_gip_sequence()
352 0x0C, 0x90, 0xA0, 0xA0, in dmt028vghmcmi_1a_gip_sequence()
353 0x0E, 0x92, 0xA0, 0xA0, in dmt028vghmcmi_1a_gip_sequence()
354 0x08, 0x8C, 0xA0, 0xA0, in dmt028vghmcmi_1a_gip_sequence()
355 0x0A, 0x8E, 0xA0, 0xA0); in dmt028vghmcmi_1a_gip_sequence()
356 ST7701_DSI(st7701, 0xE6, in dmt028vghmcmi_1a_gip_sequence()
357 0x00, 0x00, 0x22, 0x22); in dmt028vghmcmi_1a_gip_sequence()
358 ST7701_DSI(st7701, 0xE7, 0x44, 0x44); in dmt028vghmcmi_1a_gip_sequence()
359 ST7701_DSI(st7701, 0xE8, in dmt028vghmcmi_1a_gip_sequence()
360 0x0D, 0x91, 0xA0, 0xA0, in dmt028vghmcmi_1a_gip_sequence()
361 0x0F, 0x93, 0xA0, 0xA0, in dmt028vghmcmi_1a_gip_sequence()
362 0x09, 0x8D, 0xA0, 0xA0, in dmt028vghmcmi_1a_gip_sequence()
363 0x0B, 0x8F, 0xA0, 0xA0); in dmt028vghmcmi_1a_gip_sequence()
364 ST7701_DSI(st7701, 0xEB, in dmt028vghmcmi_1a_gip_sequence()
365 0x00, 0x00, 0xE4, 0xE4, in dmt028vghmcmi_1a_gip_sequence()
366 0x44, 0x00, 0x00); in dmt028vghmcmi_1a_gip_sequence()
367 ST7701_DSI(st7701, 0xED, in dmt028vghmcmi_1a_gip_sequence()
368 0xFF, 0xF5, 0x47, 0x6F, in dmt028vghmcmi_1a_gip_sequence()
369 0x0B, 0xA1, 0xAB, 0xFF, in dmt028vghmcmi_1a_gip_sequence()
370 0xFF, 0xBA, 0x1A, 0xB0, in dmt028vghmcmi_1a_gip_sequence()
371 0xF6, 0x74, 0x5F, 0xFF); in dmt028vghmcmi_1a_gip_sequence()
372 ST7701_DSI(st7701, 0xEF, in dmt028vghmcmi_1a_gip_sequence()
373 0x08, 0x08, 0x08, 0x40, in dmt028vghmcmi_1a_gip_sequence()
374 0x3F, 0x64); in dmt028vghmcmi_1a_gip_sequence()
377 0x77, 0x01, 0x00, 0x00, DSI_CMD2BKX_SEL_NONE); in dmt028vghmcmi_1a_gip_sequence()
380 0x77, 0x01, 0x00, 0x00, DSI_CMD2BK3_SEL); in dmt028vghmcmi_1a_gip_sequence()
381 ST7701_DSI(st7701, 0xE6, 0x7C); in dmt028vghmcmi_1a_gip_sequence()
382 ST7701_DSI(st7701, 0xE8, 0x00, 0x0E); in dmt028vghmcmi_1a_gip_sequence()
385 0x77, 0x01, 0x00, 0x00, DSI_CMD2BKX_SEL_NONE); in dmt028vghmcmi_1a_gip_sequence()
386 ST7701_DSI(st7701, 0x11); in dmt028vghmcmi_1a_gip_sequence()
390 0x77, 0x01, 0x00, 0x00, DSI_CMD2BK3_SEL); in dmt028vghmcmi_1a_gip_sequence()
391 ST7701_DSI(st7701, 0xE8, 0x00, 0x0C); in dmt028vghmcmi_1a_gip_sequence()
393 ST7701_DSI(st7701, 0xE8, 0x00, 0x00); in dmt028vghmcmi_1a_gip_sequence()
396 0x77, 0x01, 0x00, 0x00, DSI_CMD2BKX_SEL_NONE); in dmt028vghmcmi_1a_gip_sequence()
397 ST7701_DSI(st7701, 0x11); in dmt028vghmcmi_1a_gip_sequence()
399 ST7701_DSI(st7701, 0xE8, 0x00, 0x00); in dmt028vghmcmi_1a_gip_sequence()
402 0x77, 0x01, 0x00, 0x00, DSI_CMD2BKX_SEL_NONE); in dmt028vghmcmi_1a_gip_sequence()
404 ST7701_DSI(st7701, 0x3A, 0x70); in dmt028vghmcmi_1a_gip_sequence()
412 gpiod_set_value(st7701->reset, 0); in st7701_prepare()
416 if (ret < 0) in st7701_prepare()
430 0x77, 0x01, 0x00, 0x00, DSI_CMD2BKX_SEL_NONE); in st7701_prepare()
432 return 0; in st7701_prepare()
439 ST7701_DSI(st7701, MIPI_DCS_SET_DISPLAY_ON, 0x00); in st7701_enable()
441 return 0; in st7701_enable()
448 ST7701_DSI(st7701, MIPI_DCS_SET_DISPLAY_OFF, 0x00); in st7701_disable()
450 return 0; in st7701_disable()
457 ST7701_DSI(st7701, MIPI_DCS_ENTER_SLEEP_MODE, 0x00); in st7701_unprepare()
461 gpiod_set_value(st7701->reset, 0); in st7701_unprepare()
476 return 0; in st7701_unprepare()
537 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
538 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
539 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
540 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xe),
541 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
542 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x15),
543 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xf),
545 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
546 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11),
547 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x8),
548 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x8),
549 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
551 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8),
552 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x23),
553 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4),
554 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
555 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13),
557 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0x12),
558 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
559 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x2b),
560 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
561 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x34),
562 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
563 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f)
566 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
567 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
568 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
569 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xe),
570 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0x2) |
571 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x15),
572 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xf),
574 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
575 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x13),
576 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x7),
577 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x9),
578 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
580 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8),
581 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x22),
582 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4),
583 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
584 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x10),
586 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0xe),
587 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
588 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x2c),
589 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
590 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x34),
591 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
592 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f)
638 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
639 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
640 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
641 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0x10),
642 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
643 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x17),
644 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xd),
646 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
647 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11),
648 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x6),
649 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x5),
650 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
652 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x7),
653 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x1f),
654 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4),
655 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
656 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x11),
658 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0xe),
659 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
660 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x29),
661 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
662 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x30),
663 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
664 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f)
667 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
668 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
669 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
670 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC4_MASK, 0xd),
671 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
672 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC8_MASK, 0x14),
673 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC16_MASK, 0xe),
675 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
676 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11),
677 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC52_MASK, 0x6),
678 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC80_MASK, 0x4),
679 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
681 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8),
682 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC175_MASK, 0x20),
683 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC203_MASK, 0x5),
684 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
685 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13),
687 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC239_MASK, 0x13),
688 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
689 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC247_MASK, 0x26),
690 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
691 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC251_MASK, 0x30),
692 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
693 CFIELD_PREP(DSI_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f)
727 st7701->supplies[0].supply = "VCC"; in st7701_dsi_probe()
732 if (ret < 0) in st7701_dsi_probe()