35 		if (ret < 0)						\
37 	} while (0)
43 	gpiod_set_value_cansleep(ctx->reset_gpio, 0);  in s6e88a0_ams452ef01_reset()
57 	dsi_dcs_write_seq(dsi, 0xf0, 0x5a, 0x5a); // enable LEVEL2 commands  in s6e88a0_ams452ef01_on()
58 	dsi_dcs_write_seq(dsi, 0xcc, 0x4c); // set Pixel Clock Divider polarity  in s6e88a0_ams452ef01_on()
61 	if (ret < 0) {  in s6e88a0_ams452ef01_on()
68 	dsi_dcs_write_seq(dsi, 0xca,  in s6e88a0_ams452ef01_on()
69 			  0x01, 0x00, 0x01, 0x00, 0x01, 0x00,	// V255 RR,GG,BB  in s6e88a0_ams452ef01_on()
70 			  0x80, 0x80, 0x80,			// V203 R,G,B  in s6e88a0_ams452ef01_on()
71 			  0x80, 0x80, 0x80,			// V151 R,G,B  in s6e88a0_ams452ef01_on()
72 			  0x80, 0x80, 0x80,			// V87  R,G,B  in s6e88a0_ams452ef01_on()
73 			  0x80, 0x80, 0x80,			// V51  R,G,B  in s6e88a0_ams452ef01_on()
74 			  0x80, 0x80, 0x80,			// V35  R,G,B  in s6e88a0_ams452ef01_on()
75 			  0x80, 0x80, 0x80,			// V23  R,G,B  in s6e88a0_ams452ef01_on()
76 			  0x80, 0x80, 0x80,			// V11  R,G,B  in s6e88a0_ams452ef01_on()
77 			  0x6b, 0x68, 0x71,			// V3   R,G,B  in s6e88a0_ams452ef01_on()
78 			  0x00, 0x00, 0x00);			// V1   R,G,B  in s6e88a0_ams452ef01_on()
80 	dsi_dcs_write_seq(dsi, 0xb2, 0x40, 0x0a, 0x17, 0x00, 0x0a);  in s6e88a0_ams452ef01_on()
81 	dsi_dcs_write_seq(dsi, 0xb6, 0x2c, 0x0b); // set default elvss voltage  in s6e88a0_ams452ef01_on()
82 	dsi_dcs_write_seq(dsi, MIPI_DCS_WRITE_POWER_SAVE, 0x00);  in s6e88a0_ams452ef01_on()
83 	dsi_dcs_write_seq(dsi, 0xf7, 0x03); // gamma/aor update  in s6e88a0_ams452ef01_on()
84 	dsi_dcs_write_seq(dsi, 0xf0, 0xa5, 0xa5); // disable LEVEL2 commands  in s6e88a0_ams452ef01_on()
87 	if (ret < 0) {  in s6e88a0_ams452ef01_on()
92 	return 0;  in s6e88a0_ams452ef01_on()
104 	if (ret < 0) {  in s6e88a0_ams452ef01_off()
111 	if (ret < 0) {  in s6e88a0_ams452ef01_off()
117 	return 0;  in s6e88a0_ams452ef01_off()
127 		return 0;  in s6e88a0_ams452ef01_prepare()
130 	if (ret < 0) {  in s6e88a0_ams452ef01_prepare()
138 	if (ret < 0) {  in s6e88a0_ams452ef01_prepare()
140 		gpiod_set_value_cansleep(ctx->reset_gpio, 0);  in s6e88a0_ams452ef01_prepare()
147 	return 0;  in s6e88a0_ams452ef01_prepare()
157 		return 0;  in s6e88a0_ams452ef01_unprepare()
160 	if (ret < 0)  in s6e88a0_ams452ef01_unprepare()
163 	gpiod_set_value_cansleep(ctx->reset_gpio, 0);  in s6e88a0_ams452ef01_unprepare()
167 	return 0;  in s6e88a0_ams452ef01_unprepare()
219 	ctx->supplies[0].supply = "vdd3";  in s6e88a0_ams452ef01_probe()
223 	if (ret < 0) {  in s6e88a0_ams452ef01_probe()
248 	if (ret < 0) {  in s6e88a0_ams452ef01_probe()
254 	return 0;  in s6e88a0_ams452ef01_probe()
263 	if (ret < 0)  in s6e88a0_ams452ef01_remove()