Lines Matching +full:20 +full:us
282 * 0x00 = 0.0 us to 0x0f = 7.5 us in steps of 0.5us. The default
283 * is 0x07 = 3.5 us.
317 * 0x00 = 0us .. 0xFF = 12.75us in 0.05us steps
319 * 0x00 = 0us .. 0xFF = 12.75us in 0.05us steps
563 * Source data hold time, default 0x05 = 2.5us in nt35510_setup_display()
564 * 0x00..0x3F = 0 .. 31.5us in steps of 0.5us in nt35510_setup_display()
565 * 0x0A = 5us in nt35510_setup_display()
573 /* EQ control for gate signals, 0x00 = 0 us */ in nt35510_setup_display()
598 * 258..1024 (+1) pixel clock ticks for one scanline. At 20MHz pixel in nt35510_setup_display()
599 * clock this covers the range of 12.90us .. 51.20us in steps of in nt35510_setup_display()
600 * 0.05us, the default is 0x184 (388) representing 389 ticks. in nt35510_setup_display()
605 * PSEL for active and idle off mode, how much the 20MHz clock in nt35510_setup_display()
687 /* Active min 10 us according to datasheet, let's say 20 */ in nt35510_power_on()
688 usleep_range(20, 1000); in nt35510_power_on()
889 * 20 MHz (period time 50ns, see figure 7.6.6. page 366). in nt35510_probe()
1018 * Frame rate = (20 MHz / 1) / (389 * (7 + 50 + 800)) ~= 60 Hz
1021 /* The internal pixel clock of the NT35510 is 20 MHz */
1053 /* SDEQCTR: source driver EQ mode 2, 2.5 us rise time on each step */
1063 /* PSEL: divide pixel clock 20MHz with 1 (no clock downscaling) */