36 static struct dmm *omap_dmm;
76 static int dmm_dma_copy(struct dmm *dmm, dma_addr_t src, dma_addr_t dst)  in dmm_dma_copy()  argument
82 	tx = dmaengine_prep_dma_memcpy(dmm->wa_dma_chan, dst, src, 4, 0);  in dmm_dma_copy()
84 		dev_err(dmm->dev, "Failed to prepare DMA memcpy\n");  in dmm_dma_copy()
90 		dev_err(dmm->dev, "Failed to do DMA tx_submit\n");  in dmm_dma_copy()
94 	status = dma_sync_wait(dmm->wa_dma_chan, cookie);  in dmm_dma_copy()
96 		dev_err(dmm->dev, "i878 wa DMA copy failure\n");  in dmm_dma_copy()
98 	dmaengine_terminate_all(dmm->wa_dma_chan);  in dmm_dma_copy()
102 static u32 dmm_read_wa(struct dmm *dmm, u32 reg)  in dmm_read_wa()  argument
107 	src = dmm->phys_base + reg;  in dmm_read_wa()
108 	dst = dmm->wa_dma_handle;  in dmm_read_wa()
110 	r = dmm_dma_copy(dmm, src, dst);  in dmm_read_wa()
112 		dev_err(dmm->dev, "sDMA read transfer timeout\n");  in dmm_read_wa()
113 		return readl(dmm->base + reg);  in dmm_read_wa()
122 	return readl(dmm->wa_dma_data);  in dmm_read_wa()
125 static void dmm_write_wa(struct dmm *dmm, u32 val, u32 reg)  in dmm_write_wa()  argument
130 	writel(val, dmm->wa_dma_data);  in dmm_write_wa()
139 	src = dmm->wa_dma_handle;  in dmm_write_wa()
140 	dst = dmm->phys_base + reg;  in dmm_write_wa()
142 	r = dmm_dma_copy(dmm, src, dst);  in dmm_write_wa()
144 		dev_err(dmm->dev, "sDMA write transfer timeout\n");  in dmm_write_wa()
145 		writel(val, dmm->base + reg);  in dmm_write_wa()
149 static u32 dmm_read(struct dmm *dmm, u32 reg)  in dmm_read()  argument
151 	if (dmm->dmm_workaround) {  in dmm_read()
155 		spin_lock_irqsave(&dmm->wa_lock, flags);  in dmm_read()
156 		v = dmm_read_wa(dmm, reg);  in dmm_read()
157 		spin_unlock_irqrestore(&dmm->wa_lock, flags);  in dmm_read()
161 		return readl(dmm->base + reg);  in dmm_read()
165 static void dmm_write(struct dmm *dmm, u32 val, u32 reg)  in dmm_write()  argument
167 	if (dmm->dmm_workaround) {  in dmm_write()
170 		spin_lock_irqsave(&dmm->wa_lock, flags);  in dmm_write()
171 		dmm_write_wa(dmm, val, reg);  in dmm_write()
172 		spin_unlock_irqrestore(&dmm->wa_lock, flags);  in dmm_write()
174 		writel(val, dmm->base + reg);  in dmm_write()
178 static int dmm_workaround_init(struct dmm *dmm)  in dmm_workaround_init()  argument
182 	spin_lock_init(&dmm->wa_lock);  in dmm_workaround_init()
184 	dmm->wa_dma_data = dma_alloc_coherent(dmm->dev,  sizeof(u32),  in dmm_workaround_init()
185 					      &dmm->wa_dma_handle, GFP_KERNEL);  in dmm_workaround_init()
186 	if (!dmm->wa_dma_data)  in dmm_workaround_init()
192 	dmm->wa_dma_chan = dma_request_channel(mask, NULL, NULL);  in dmm_workaround_init()
193 	if (!dmm->wa_dma_chan) {  in dmm_workaround_init()
194 		dma_free_coherent(dmm->dev, 4, dmm->wa_dma_data, dmm->wa_dma_handle);  in dmm_workaround_init()
201 static void dmm_workaround_uninit(struct dmm *dmm)  in dmm_workaround_uninit()  argument
203 	dma_release_channel(dmm->wa_dma_chan);  in dmm_workaround_uninit()
205 	dma_free_coherent(dmm->dev, 4, dmm->wa_dma_data, dmm->wa_dma_handle);  in dmm_workaround_uninit()
232 	struct dmm *dmm = engine->dmm;  in wait_status()  local
237 		r = dmm_read(dmm, reg[PAT_STATUS][engine->id]);  in wait_status()
240 			dev_err(dmm->dev,  in wait_status()
250 			dev_err(dmm->dev,  in wait_status()
276 	struct dmm *dmm = arg;  in omap_dmm_irq_handler()  local
277 	u32 status = dmm_read(dmm, DMM_PAT_IRQSTATUS);  in omap_dmm_irq_handler()
281 	dmm_write(dmm, status, DMM_PAT_IRQSTATUS);  in omap_dmm_irq_handler()
283 	for (i = 0; i < dmm->num_engines; i++) {  in omap_dmm_irq_handler()
285 			dev_err(dmm->dev,  in omap_dmm_irq_handler()
290 			if (dmm->engines[i].async)  in omap_dmm_irq_handler()
291 				release_engine(&dmm->engines[i]);  in omap_dmm_irq_handler()
293 			complete(&dmm->engines[i].compl);  in omap_dmm_irq_handler()
305 static struct dmm_txn *dmm_txn_init(struct dmm *dmm, struct tcm *tcm)  in dmm_txn_init()  argument
321 	if (!list_empty(&dmm->idle_head)) {  in dmm_txn_init()
322 		engine = list_entry(dmm->idle_head.next, struct refill_engine,  in dmm_txn_init()
380 			page_to_phys(pages[n]) : engine->dmm->dummy_pa;  in dmm_txn_append()
395 	struct dmm *dmm = engine->dmm;  in dmm_txn_commit()  local
398 		dev_err(engine->dmm->dev, "need at least one txn\n");  in dmm_txn_commit()
417 	dmm_write(dmm, 0x0, reg[PAT_DESCR][engine->id]);  in dmm_txn_commit()
433 	dmm_write(dmm, engine->refill_pa, reg[PAT_DESCR][engine->id]);  in dmm_txn_commit()
438 			dev_err(dmm->dev, "timed out waiting for done\n");  in dmm_txn_commit()
897 		omap_dmm->engines[i].dmm = omap_dmm;  in omap_dmm_probe()