52 	struct nvkm_device *device = fifo->base.engine.subdev.device;  in nv04_fifo_pause()  local
58 	nvkm_wr32(device, NV03_PFIFO_CACHES, 0x00000000);  in nv04_fifo_pause()
59 	nvkm_mask(device, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0x00000000);  in nv04_fifo_pause()
70 	nvkm_msec(device, 2000,  in nv04_fifo_pause()
71 		u32 tmp = nvkm_rd32(device, NV04_PFIFO_CACHE1_PULL0);  in nv04_fifo_pause()
76 	if (nvkm_rd32(device, NV04_PFIFO_CACHE1_PULL0) &  in nv04_fifo_pause()
78 		nvkm_wr32(device, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR);  in nv04_fifo_pause()
80 	nvkm_wr32(device, NV04_PFIFO_CACHE1_HASH, 0x00000000);  in nv04_fifo_pause()
88 	struct nvkm_device *device = fifo->base.engine.subdev.device;  in nv04_fifo_start()  local
91 	nvkm_mask(device, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0x00000001);  in nv04_fifo_start()
92 	nvkm_wr32(device, NV03_PFIFO_CACHES, 0x00000001);  in nv04_fifo_start()
112 	return nvkm_device_engine(fifo->engine.subdev.device, type, 0);  in nv04_fifo_id_engine()
140 nv04_fifo_swmthd(struct nvkm_device *device, u32 chid, u32 addr, u32 data)  in nv04_fifo_swmthd()  argument
142 	struct nvkm_sw *sw = device->sw;  in nv04_fifo_swmthd()
146 	u32 engine = nvkm_rd32(device, 0x003280);  in nv04_fifo_swmthd()
151 		nvkm_wr32(device, 0x003280, (engine &= ~mask));  in nv04_fifo_swmthd()
154 		data = nvkm_rd32(device, 0x003258) & 0x0000ffff;  in nv04_fifo_swmthd()
172 	struct nvkm_device *device = subdev->device;  in nv04_fifo_cache_error()  local
175 	u32 pull0 = nvkm_rd32(device, 0x003250);  in nv04_fifo_cache_error()
186 	if (device->card_type < NV_40) {  in nv04_fifo_cache_error()
187 		mthd = nvkm_rd32(device, NV04_PFIFO_CACHE1_METHOD(ptr));  in nv04_fifo_cache_error()
188 		data = nvkm_rd32(device, NV04_PFIFO_CACHE1_DATA(ptr));  in nv04_fifo_cache_error()
190 		mthd = nvkm_rd32(device, NV40_PFIFO_CACHE1_METHOD(ptr));  in nv04_fifo_cache_error()
191 		data = nvkm_rd32(device, NV40_PFIFO_CACHE1_DATA(ptr));  in nv04_fifo_cache_error()
195 	    !nv04_fifo_swmthd(device, chid, mthd, data)) {  in nv04_fifo_cache_error()
204 	nvkm_wr32(device, NV04_PFIFO_CACHE1_DMA_PUSH, 0);  in nv04_fifo_cache_error()
205 	nvkm_wr32(device, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR);  in nv04_fifo_cache_error()
207 	nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0,  in nv04_fifo_cache_error()
208 		nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH0) & ~1);  in nv04_fifo_cache_error()
209 	nvkm_wr32(device, NV03_PFIFO_CACHE1_GET, get + 4);  in nv04_fifo_cache_error()
210 	nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0,  in nv04_fifo_cache_error()
211 		nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH0) | 1);  in nv04_fifo_cache_error()
212 	nvkm_wr32(device, NV04_PFIFO_CACHE1_HASH, 0);  in nv04_fifo_cache_error()
214 	nvkm_wr32(device, NV04_PFIFO_CACHE1_DMA_PUSH,  in nv04_fifo_cache_error()
215 		nvkm_rd32(device, NV04_PFIFO_CACHE1_DMA_PUSH) | 1);  in nv04_fifo_cache_error()
216 	nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1);  in nv04_fifo_cache_error()
223 	struct nvkm_device *device = subdev->device;  in nv04_fifo_dma_pusher()  local
224 	u32 dma_get = nvkm_rd32(device, 0x003244);  in nv04_fifo_dma_pusher()
225 	u32 dma_put = nvkm_rd32(device, 0x003240);  in nv04_fifo_dma_pusher()
226 	u32 push = nvkm_rd32(device, 0x003220);  in nv04_fifo_dma_pusher()
227 	u32 state = nvkm_rd32(device, 0x003228);  in nv04_fifo_dma_pusher()
234 	if (device->card_type == NV_50) {  in nv04_fifo_dma_pusher()
235 		u32 ho_get = nvkm_rd32(device, 0x003328);  in nv04_fifo_dma_pusher()
236 		u32 ho_put = nvkm_rd32(device, 0x003320);  in nv04_fifo_dma_pusher()
237 		u32 ib_get = nvkm_rd32(device, 0x003334);  in nv04_fifo_dma_pusher()
238 		u32 ib_put = nvkm_rd32(device, 0x003330);  in nv04_fifo_dma_pusher()
248 		nvkm_wr32(device, 0x003364, 0x00000000);  in nv04_fifo_dma_pusher()
250 			nvkm_wr32(device, 0x003244, dma_put);  in nv04_fifo_dma_pusher()
251 			nvkm_wr32(device, 0x003328, ho_put);  in nv04_fifo_dma_pusher()
254 			nvkm_wr32(device, 0x003334, ib_put);  in nv04_fifo_dma_pusher()
262 			nvkm_wr32(device, 0x003244, dma_put);  in nv04_fifo_dma_pusher()
266 	nvkm_wr32(device, 0x003228, 0x00000000);  in nv04_fifo_dma_pusher()
267 	nvkm_wr32(device, 0x003220, 0x00000001);  in nv04_fifo_dma_pusher()
268 	nvkm_wr32(device, 0x002100, NV_PFIFO_INTR_DMA_PUSHER);  in nv04_fifo_dma_pusher()
276 	struct nvkm_device *device = subdev->device;  in nv04_fifo_intr()  local
277 	u32 mask = nvkm_rd32(device, NV03_PFIFO_INTR_EN_0);  in nv04_fifo_intr()
278 	u32 stat = nvkm_rd32(device, NV03_PFIFO_INTR_0) & mask;  in nv04_fifo_intr()
281 	reassign = nvkm_rd32(device, NV03_PFIFO_CACHES) & 1;  in nv04_fifo_intr()
282 	nvkm_wr32(device, NV03_PFIFO_CACHES, 0);  in nv04_fifo_intr()
284 	chid = nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH1) & (fifo->base.nr - 1);  in nv04_fifo_intr()
285 	get  = nvkm_rd32(device, NV03_PFIFO_CACHE1_GET);  in nv04_fifo_intr()
299 		nvkm_wr32(device, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_SEMAPHORE);  in nv04_fifo_intr()
301 		sem = nvkm_rd32(device, NV10_PFIFO_CACHE1_SEMAPHORE);  in nv04_fifo_intr()
302 		nvkm_wr32(device, NV10_PFIFO_CACHE1_SEMAPHORE, sem | 0x1);  in nv04_fifo_intr()
304 		nvkm_wr32(device, NV03_PFIFO_CACHE1_GET, get + 4);  in nv04_fifo_intr()
305 		nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1);  in nv04_fifo_intr()
308 	if (device->card_type == NV_50) {  in nv04_fifo_intr()
311 			nvkm_wr32(device, 0x002100, 0x00000010);  in nv04_fifo_intr()
315 			nvkm_wr32(device, 0x002100, 0x40000000);  in nv04_fifo_intr()
323 		nvkm_mask(device, NV03_PFIFO_INTR_EN_0, stat, 0x00000000);  in nv04_fifo_intr()
324 		nvkm_wr32(device, NV03_PFIFO_INTR_0, stat);  in nv04_fifo_intr()
327 	nvkm_wr32(device, NV03_PFIFO_CACHES, reassign);  in nv04_fifo_intr()
334 	struct nvkm_device *device = fifo->base.engine.subdev.device;  in nv04_fifo_init()  local
335 	struct nvkm_instmem *imem = device->imem;  in nv04_fifo_init()
340 	nvkm_wr32(device, NV04_PFIFO_DELAY_0, 0x000000ff);  in nv04_fifo_init()
341 	nvkm_wr32(device, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff);  in nv04_fifo_init()
343 	nvkm_wr32(device, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |  in nv04_fifo_init()
346 	nvkm_wr32(device, NV03_PFIFO_RAMRO, nvkm_memory_addr(ramro) >> 8);  in nv04_fifo_init()
347 	nvkm_wr32(device, NV03_PFIFO_RAMFC, nvkm_memory_addr(ramfc) >> 8);  in nv04_fifo_init()
349 	nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->base.nr - 1);  in nv04_fifo_init()
351 	nvkm_wr32(device, NV03_PFIFO_INTR_0, 0xffffffff);  in nv04_fifo_init()
352 	nvkm_wr32(device, NV03_PFIFO_INTR_EN_0, 0xffffffff);  in nv04_fifo_init()
354 	nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1);  in nv04_fifo_init()
355 	nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1);  in nv04_fifo_init()
356 	nvkm_wr32(device, NV03_PFIFO_CACHES, 1);  in nv04_fifo_init()
360 nv04_fifo_new_(const struct nvkm_fifo_func *func, struct nvkm_device *device,  in nv04_fifo_new_()  argument
372 	ret = nvkm_fifo_ctor(func, device, type, inst, nr, &fifo->base);  in nv04_fifo_new_()
395 nv04_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,  in nv04_fifo_new()  argument
398 	return nv04_fifo_new_(&nv04_fifo, device, type, inst, 16, nv04_fifo_ramfc, pfifo);  in nv04_fifo_new()