160 nv50_sor_clock(struct nvkm_ior *sor)  in nv50_sor_clock()  argument
162 	struct nvkm_device *device = sor->disp->engine.subdev.device;  in nv50_sor_clock()
163 	const int  div = sor->asy.link == 3;  in nv50_sor_clock()
164 	const u32 soff = nv50_ior_base(sor);  in nv50_sor_clock()
179 nv50_sor_power(struct nvkm_ior *sor, bool normal, bool pu, bool data, bool vsync, bool hsync)  in nv50_sor_power()  argument
181 	struct nvkm_device *device = sor->disp->engine.subdev.device;  in nv50_sor_power()
182 	const u32  soff = nv50_ior_base(sor);  in nv50_sor_power()
198 nv50_sor_state(struct nvkm_ior *sor, struct nvkm_ior_state *state)  in nv50_sor_state()  argument
200 	struct nvkm_device *device = sor->disp->engine.subdev.device;  in nv50_sor_state()
201 	const u32 coff = sor->id * 8 + (state == &sor->arm) * 4;  in nv50_sor_state()
228 	return nvkm_ior_new_(&nv50_sor, disp, SOR, id, false);  in nv50_sor_new()
901 		{    "SOR", 2, &nv50_disp_core_mthd_sor  },
1017 	if (ior->type == SOR) {  in nv50_disp_super_ied_on()
1250 	if (ior->type == SOR && ior->asy.proto == LVDS) {  in nv50_disp_super_2_2()
1251 		head->asy.or.depth = (disp->sor.lvdsconf & 0x0200) ? 24 : 18;  in nv50_disp_super_2_2()
1252 		ior->asy.link      = (disp->sor.lvdsconf & 0x0100) ? 3  : 1;  in nv50_disp_super_2_2()
1266 	if (ior->type == SOR && ior->asy.proto == DP)  in nv50_disp_super_2_2()
1526 	/* ... SOR caps */  in nv50_disp_init()
1527 	for (i = 0; i < disp->sor.nr; i++) {  in nv50_disp_init()
1599 	disp->sor.nr = func->sor.cnt(disp, &disp->sor.mask);  in nv50_disp_oneinit()
1600 	nvkm_debug(subdev, "   SOR(s): %d (%02lx)\n", disp->sor.nr, disp->sor.mask);  in nv50_disp_oneinit()
1601 	for_each_set_bit(i, &disp->sor.mask, disp->sor.nr) {  in nv50_disp_oneinit()
1602 		ret = func->sor.new(disp, i);  in nv50_disp_oneinit()
1625 	.sor = { .cnt = nv50_sor_cnt, .new = nv50_sor_new },