Lines Matching +full:0 +full:x2184
41 const u32 hoff = 0x800 * head; in gv100_sor_hda_device_entry()
43 nvkm_mask(device, 0x616528 + hoff, 0x00000070, head << 4); in gv100_sor_hda_device_entry()
57 const u32 hoff = head * 0x800; in gv100_sor_dp_watermark()
59 nvkm_mask(device, 0x616550 + hoff, 0x0c00003f, 0x08000000 | watermark); in gv100_sor_dp_watermark()
66 const u32 hoff = head * 0x800; in gv100_sor_dp_audio_sym()
68 nvkm_mask(device, 0x616568 + hoff, 0x0000ffff, h); in gv100_sor_dp_audio_sym()
69 nvkm_mask(device, 0x61656c + hoff, 0x00ffffff, v); in gv100_sor_dp_audio_sym()
76 const u32 hoff = 0x800 * head; in gv100_sor_dp_audio()
77 const u32 data = 0x80000000 | (0x00000001 * enable); in gv100_sor_dp_audio()
78 const u32 mask = 0x8000000d; in gv100_sor_dp_audio()
80 nvkm_mask(device, 0x616560 + hoff, mask, data); in gv100_sor_dp_audio()
82 if (!(nvkm_rd32(device, 0x616560 + hoff) & 0x80000000)) in gv100_sor_dp_audio()
89 .lanes = { 0, 1, 2, 3 },
104 const u32 ctrl = 0x40000000 * enable | in gv100_sor_hdmi_ctrl()
107 const u32 hoff = head * 0x800; in gv100_sor_hdmi_ctrl()
108 const u32 hdmi = head * 0x400; in gv100_sor_hdmi_ctrl()
115 if (!(ctrl & 0x40000000)) { in gv100_sor_hdmi_ctrl()
116 nvkm_mask(device, 0x6165c0 + hoff, 0x40000000, 0x00000000); in gv100_sor_hdmi_ctrl()
117 nvkm_mask(device, 0x6f0100 + hdmi, 0x00000001, 0x00000000); in gv100_sor_hdmi_ctrl()
118 nvkm_mask(device, 0x6f00c0 + hdmi, 0x00000001, 0x00000000); in gv100_sor_hdmi_ctrl()
119 nvkm_mask(device, 0x6f0000 + hdmi, 0x00000001, 0x00000000); in gv100_sor_hdmi_ctrl()
124 nvkm_mask(device, 0x6f0000 + hdmi, 0x00000001, 0x00000000); in gv100_sor_hdmi_ctrl()
126 nvkm_wr32(device, 0x6f0008 + hdmi, avi_infoframe.header); in gv100_sor_hdmi_ctrl()
127 nvkm_wr32(device, 0x6f000c + hdmi, avi_infoframe.subpack0_low); in gv100_sor_hdmi_ctrl()
128 nvkm_wr32(device, 0x6f0010 + hdmi, avi_infoframe.subpack0_high); in gv100_sor_hdmi_ctrl()
129 nvkm_wr32(device, 0x6f0014 + hdmi, avi_infoframe.subpack1_low); in gv100_sor_hdmi_ctrl()
130 nvkm_wr32(device, 0x6f0018 + hdmi, avi_infoframe.subpack1_high); in gv100_sor_hdmi_ctrl()
131 nvkm_mask(device, 0x6f0000 + hdmi, 0x00000001, 0x00000001); in gv100_sor_hdmi_ctrl()
135 nvkm_mask(device, 0x6f0100 + hdmi, 0x00010001, 0x00000000); in gv100_sor_hdmi_ctrl()
137 nvkm_wr32(device, 0x6f0108 + hdmi, vendor_infoframe.header); in gv100_sor_hdmi_ctrl()
138 nvkm_wr32(device, 0x6f010c + hdmi, vendor_infoframe.subpack0_low); in gv100_sor_hdmi_ctrl()
139 nvkm_wr32(device, 0x6f0110 + hdmi, vendor_infoframe.subpack0_high); in gv100_sor_hdmi_ctrl()
140 nvkm_wr32(device, 0x6f0114 + hdmi, 0x00000000); in gv100_sor_hdmi_ctrl()
141 nvkm_wr32(device, 0x6f0118 + hdmi, 0x00000000); in gv100_sor_hdmi_ctrl()
142 nvkm_wr32(device, 0x6f011c + hdmi, 0x00000000); in gv100_sor_hdmi_ctrl()
143 nvkm_wr32(device, 0x6f0120 + hdmi, 0x00000000); in gv100_sor_hdmi_ctrl()
144 nvkm_wr32(device, 0x6f0124 + hdmi, 0x00000000); in gv100_sor_hdmi_ctrl()
145 nvkm_mask(device, 0x6f0100 + hdmi, 0x00000001, 0x00000001); in gv100_sor_hdmi_ctrl()
150 nvkm_mask(device, 0x6f00c0 + hdmi, 0x00000001, 0x00000000); in gv100_sor_hdmi_ctrl()
151 nvkm_wr32(device, 0x6f00cc + hdmi, 0x00000010); in gv100_sor_hdmi_ctrl()
152 nvkm_mask(device, 0x6f00c0 + hdmi, 0x00000001, 0x00000001); in gv100_sor_hdmi_ctrl()
155 nvkm_wr32(device, 0x6f0080 + hdmi, 0x82000000); in gv100_sor_hdmi_ctrl()
158 nvkm_mask(device, 0x6165c0 + hoff, 0x401f007f, ctrl); in gv100_sor_hdmi_ctrl()
165 const u32 coff = (state == &sor->arm) * 0x8000 + sor->id * 0x20; in gv100_sor_state()
166 u32 ctrl = nvkm_rd32(device, 0x680300 + coff); in gv100_sor_state()
168 state->proto_evo = (ctrl & 0x00000f00) >> 8; in gv100_sor_state()
170 case 0: state->proto = LVDS; state->link = 1; break; in gv100_sor_state()
181 state->head = ctrl & 0x000000ff; in gv100_sor_state()
207 if (!((hda = nvkm_rd32(device, 0x08a15c)) & 0x40000000)) in gv100_sor_new()
208 hda = nvkm_rd32(device, 0x118fb0) >> 8; in gv100_sor_new()
218 *pmask = (nvkm_rd32(device, 0x610060) & 0x0000ff00) >> 8; in gv100_sor_cnt()
219 return (nvkm_rd32(device, 0x610074) & 0x00000f00) >> 8; in gv100_sor_cnt()
226 nvkm_mask(device, 0x611d80 + (head->id * 4), 0x00000004, 0x00000000); in gv100_head_vblank_put()
233 nvkm_mask(device, 0x611d80 + (head->id * 4), 0x00000004, 0x00000004); in gv100_head_vblank_get()
240 const u32 hoff = head->id * 0x800; in gv100_head_rgpos()
242 *vline = nvkm_rd32(device, 0x616330 + hoff) & 0x0000ffff; in gv100_head_rgpos()
243 *hline = nvkm_rd32(device, 0x616334 + hoff) & 0x0000ffff; in gv100_head_rgpos()
250 const u32 hoff = (state == &head->arm) * 0x8000 + head->id * 0x400; in gv100_head_state()
253 data = nvkm_rd32(device, 0x682064 + hoff); in gv100_head_state()
254 state->vtotal = (data & 0xffff0000) >> 16; in gv100_head_state()
255 state->htotal = (data & 0x0000ffff); in gv100_head_state()
256 data = nvkm_rd32(device, 0x682068 + hoff); in gv100_head_state()
257 state->vsynce = (data & 0xffff0000) >> 16; in gv100_head_state()
258 state->hsynce = (data & 0x0000ffff); in gv100_head_state()
259 data = nvkm_rd32(device, 0x68206c + hoff); in gv100_head_state()
260 state->vblanke = (data & 0xffff0000) >> 16; in gv100_head_state()
261 state->hblanke = (data & 0x0000ffff); in gv100_head_state()
262 data = nvkm_rd32(device, 0x682070 + hoff); in gv100_head_state()
263 state->vblanks = (data & 0xffff0000) >> 16; in gv100_head_state()
264 state->hblanks = (data & 0x0000ffff); in gv100_head_state()
265 state->hz = nvkm_rd32(device, 0x68200c + hoff); in gv100_head_state()
267 data = nvkm_rd32(device, 0x682004 + hoff); in gv100_head_state()
268 switch ((data & 0x000000f0) >> 4) { in gv100_head_state()
293 if (!(nvkm_rd32(device, 0x610060) & (0x00000001 << id))) in gv100_head_new()
294 return 0; in gv100_head_new()
304 *pmask = nvkm_rd32(device, 0x610060) & 0x000000ff; in gv100_head_cnt()
305 return nvkm_rd32(device, 0x610074) & 0x0000000f; in gv100_head_cnt()
315 *psize = 0x1000; in gv100_disp_chan_user()
316 return 0x690000 + ((chan->chid.user - 1) * 0x1000); in gv100_disp_chan_user()
323 const u32 soff = (chan->chid.ctrl - 1) * 0x04; in gv100_disp_dmac_idle()
325 u32 stat = nvkm_rd32(device, 0x610664 + soff); in gv100_disp_dmac_idle()
326 if ((stat & 0x000f0000) == 0x00040000) in gv100_disp_dmac_idle()
327 return 0; in gv100_disp_dmac_idle()
337 chan->chid.user << 25 | 0x00000040); in gv100_disp_dmac_bind()
344 const u32 uoff = (chan->chid.ctrl - 1) * 0x1000; in gv100_disp_dmac_fini()
345 const u32 coff = chan->chid.ctrl * 0x04; in gv100_disp_dmac_fini()
346 nvkm_mask(device, 0x6104e0 + coff, 0x00000010, 0x00000000); in gv100_disp_dmac_fini()
348 nvkm_mask(device, 0x6104e0 + coff, 0x00000002, 0x00000000); in gv100_disp_dmac_fini()
349 chan->suspend_put = nvkm_rd32(device, 0x690000 + uoff); in gv100_disp_dmac_fini()
357 const u32 uoff = (chan->chid.ctrl - 1) * 0x1000; in gv100_disp_dmac_init()
358 const u32 poff = chan->chid.ctrl * 0x10; in gv100_disp_dmac_init()
359 const u32 coff = chan->chid.ctrl * 0x04; in gv100_disp_dmac_init()
361 nvkm_wr32(device, 0x610b24 + poff, lower_32_bits(chan->push)); in gv100_disp_dmac_init()
362 nvkm_wr32(device, 0x610b20 + poff, upper_32_bits(chan->push)); in gv100_disp_dmac_init()
363 nvkm_wr32(device, 0x610b28 + poff, 0x00000001); in gv100_disp_dmac_init()
364 nvkm_wr32(device, 0x610b2c + poff, 0x00000040); in gv100_disp_dmac_init()
366 nvkm_mask(device, 0x6104e0 + coff, 0x00000010, 0x00000010); in gv100_disp_dmac_init()
367 nvkm_wr32(device, 0x690000 + uoff, chan->suspend_put); in gv100_disp_dmac_init()
368 nvkm_wr32(device, 0x6104e0 + coff, 0x00000013); in gv100_disp_dmac_init()
376 const u32 mask = 0x00000001 << chan->head; in gv100_disp_wimm_intr()
377 const u32 data = en ? mask : 0; in gv100_disp_wimm_intr()
378 nvkm_mask(device, 0x611da8, mask, data); in gv100_disp_wimm_intr()
399 .mthd = 0x0000,
400 .addr = 0x000000,
402 { 0x0200, 0x690200 },
403 { 0x020c, 0x69020c },
404 { 0x0210, 0x690210 },
405 { 0x0214, 0x690214 },
406 { 0x0218, 0x690218 },
407 { 0x021c, 0x69021c },
408 { 0x0220, 0x690220 },
409 { 0x0224, 0x690224 },
410 { 0x0228, 0x690228 },
411 { 0x022c, 0x69022c },
412 { 0x0230, 0x690230 },
413 { 0x0234, 0x690234 },
414 { 0x0238, 0x690238 },
415 { 0x0240, 0x690240 },
416 { 0x0244, 0x690244 },
417 { 0x0248, 0x690248 },
418 { 0x024c, 0x69024c },
419 { 0x0250, 0x690250 },
420 { 0x0254, 0x690254 },
421 { 0x0260, 0x690260 },
422 { 0x0264, 0x690264 },
423 { 0x0268, 0x690268 },
424 { 0x026c, 0x69026c },
425 { 0x0270, 0x690270 },
426 { 0x0274, 0x690274 },
427 { 0x0280, 0x690280 },
428 { 0x0284, 0x690284 },
429 { 0x0288, 0x690288 },
430 { 0x028c, 0x69028c },
431 { 0x0290, 0x690290 },
432 { 0x0298, 0x690298 },
433 { 0x029c, 0x69029c },
434 { 0x02a0, 0x6902a0 },
435 { 0x02a4, 0x6902a4 },
436 { 0x02a8, 0x6902a8 },
437 { 0x02ac, 0x6902ac },
438 { 0x02b0, 0x6902b0 },
439 { 0x02b4, 0x6902b4 },
440 { 0x02b8, 0x6902b8 },
441 { 0x02bc, 0x6902bc },
442 { 0x02c0, 0x6902c0 },
443 { 0x02c4, 0x6902c4 },
444 { 0x02c8, 0x6902c8 },
445 { 0x02cc, 0x6902cc },
446 { 0x02d0, 0x6902d0 },
447 { 0x02d4, 0x6902d4 },
448 { 0x02d8, 0x6902d8 },
449 { 0x02dc, 0x6902dc },
450 { 0x02e0, 0x6902e0 },
451 { 0x02e4, 0x6902e4 },
452 { 0x02e8, 0x6902e8 },
453 { 0x02ec, 0x6902ec },
454 { 0x02f0, 0x6902f0 },
455 { 0x02f4, 0x6902f4 },
456 { 0x02f8, 0x6902f8 },
457 { 0x02fc, 0x6902fc },
458 { 0x0300, 0x690300 },
459 { 0x0304, 0x690304 },
460 { 0x0308, 0x690308 },
461 { 0x0310, 0x690310 },
462 { 0x0314, 0x690314 },
463 { 0x0318, 0x690318 },
464 { 0x031c, 0x69031c },
465 { 0x0320, 0x690320 },
466 { 0x0324, 0x690324 },
467 { 0x0328, 0x690328 },
468 { 0x032c, 0x69032c },
469 { 0x033c, 0x69033c },
470 { 0x0340, 0x690340 },
471 { 0x0344, 0x690344 },
472 { 0x0348, 0x690348 },
473 { 0x034c, 0x69034c },
474 { 0x0350, 0x690350 },
475 { 0x0354, 0x690354 },
476 { 0x0358, 0x690358 },
477 { 0x0364, 0x690364 },
478 { 0x0368, 0x690368 },
479 { 0x036c, 0x69036c },
480 { 0x0370, 0x690370 },
481 { 0x0374, 0x690374 },
482 { 0x0380, 0x690380 },
490 .addr = 0x001000,
491 .prev = 0x000800,
502 const u32 mask = 0x00000001 << chan->head; in gv100_disp_wndw_intr()
503 const u32 data = en ? mask : 0; in gv100_disp_wndw_intr()
504 nvkm_mask(device, 0x611da4, mask, data); in gv100_disp_wndw_intr()
530 *pmask = nvkm_rd32(device, 0x610064); in gv100_disp_wndw_cnt()
531 return (nvkm_rd32(device, 0x610074) & 0x03f00000) >> 20; in gv100_disp_wndw_cnt()
538 const u32 soff = (chan->chid.ctrl - 1) * 0x04; in gv100_disp_curs_idle()
540 u32 stat = nvkm_rd32(device, 0x610664 + soff); in gv100_disp_curs_idle()
541 if ((stat & 0x00070000) == 0x00040000) in gv100_disp_curs_idle()
542 return 0; in gv100_disp_curs_idle()
551 const u32 mask = 0x00010000 << chan->head; in gv100_disp_curs_intr()
552 const u32 data = en ? mask : 0; in gv100_disp_curs_intr()
553 nvkm_mask(device, 0x611dac, mask, data); in gv100_disp_curs_intr()
561 nvkm_mask(device, 0x6104e0 + hoff, 0x00000010, 0x00000010); in gv100_disp_curs_fini()
563 nvkm_mask(device, 0x6104e0 + hoff, 0x00000001, 0x00000000); in gv100_disp_curs_fini()
571 nvkm_wr32(device, 0x6104e0 + chan->chid.ctrl * 4, 0x00000001); in gv100_disp_curs_init()
592 .mthd = 0x0000,
593 .addr = 0x000000,
595 { 0x0200, 0x680200 },
596 { 0x0208, 0x680208 },
597 { 0x020c, 0x68020c },
598 { 0x0210, 0x680210 },
599 { 0x0214, 0x680214 },
600 { 0x0218, 0x680218 },
601 { 0x021c, 0x68021c },
608 .mthd = 0x0020,
609 .addr = 0x000020,
611 { 0x0300, 0x680300 },
612 { 0x0304, 0x680304 },
613 { 0x0308, 0x680308 },
614 { 0x030c, 0x68030c },
621 .mthd = 0x0080,
622 .addr = 0x000080,
624 { 0x1000, 0x681000 },
625 { 0x1004, 0x681004 },
626 { 0x1008, 0x681008 },
627 { 0x100c, 0x68100c },
628 { 0x1010, 0x681010 },
635 .mthd = 0x0400,
636 .addr = 0x000400,
638 { 0x2000, 0x682000 },
639 { 0x2004, 0x682004 },
640 { 0x2008, 0x682008 },
641 { 0x200c, 0x68200c },
642 { 0x2014, 0x682014 },
643 { 0x2018, 0x682018 },
644 { 0x201c, 0x68201c },
645 { 0x2020, 0x682020 },
646 { 0x2028, 0x682028 },
647 { 0x202c, 0x68202c },
648 { 0x2030, 0x682030 },
649 { 0x2038, 0x682038 },
650 { 0x203c, 0x68203c },
651 { 0x2048, 0x682048 },
652 { 0x204c, 0x68204c },
653 { 0x2050, 0x682050 },
654 { 0x2054, 0x682054 },
655 { 0x2058, 0x682058 },
656 { 0x205c, 0x68205c },
657 { 0x2060, 0x682060 },
658 { 0x2064, 0x682064 },
659 { 0x2068, 0x682068 },
660 { 0x206c, 0x68206c },
661 { 0x2070, 0x682070 },
662 { 0x2074, 0x682074 },
663 { 0x2078, 0x682078 },
664 { 0x207c, 0x68207c },
665 { 0x2080, 0x682080 },
666 { 0x2088, 0x682088 },
667 { 0x2090, 0x682090 },
668 { 0x209c, 0x68209c },
669 { 0x20a0, 0x6820a0 },
670 { 0x20a4, 0x6820a4 },
671 { 0x20a8, 0x6820a8 },
672 { 0x20ac, 0x6820ac },
673 { 0x2180, 0x682180 },
674 { 0x2184, 0x682184 },
675 { 0x218c, 0x68218c },
676 { 0x2194, 0x682194 },
677 { 0x2198, 0x682198 },
678 { 0x219c, 0x68219c },
679 { 0x21a0, 0x6821a0 },
680 { 0x21a4, 0x6821a4 },
681 { 0x2214, 0x682214 },
682 { 0x2218, 0x682218 },
690 .addr = 0x000000,
691 .prev = 0x008000,
706 u32 stat = nvkm_rd32(device, 0x610630); in gv100_disp_core_idle()
707 if ((stat & 0x001f0000) == 0x000b0000) in gv100_disp_core_idle()
708 return 0; in gv100_disp_core_idle()
716 *psize = 0x10000; in gv100_disp_core_user()
717 return 0x680000; in gv100_disp_core_user()
724 const u32 mask = 0x00000001; in gv100_disp_core_intr()
725 const u32 data = en ? mask : 0; in gv100_disp_core_intr()
726 nvkm_mask(device, 0x611dac, mask, data); in gv100_disp_core_intr()
733 nvkm_mask(device, 0x6104e0, 0x00000010, 0x00000000); in gv100_disp_core_fini()
735 nvkm_mask(device, 0x6104e0, 0x00000002, 0x00000000); in gv100_disp_core_fini()
736 chan->suspend_put = nvkm_rd32(device, 0x680000); in gv100_disp_core_fini()
745 nvkm_wr32(device, 0x610b24, lower_32_bits(chan->push)); in gv100_disp_core_init()
746 nvkm_wr32(device, 0x610b20, upper_32_bits(chan->push)); in gv100_disp_core_init()
747 nvkm_wr32(device, 0x610b28, 0x00000001); in gv100_disp_core_init()
748 nvkm_wr32(device, 0x610b2c, 0x00000040); in gv100_disp_core_init()
750 nvkm_mask(device, 0x6104e0, 0x00000010, 0x00000010); in gv100_disp_core_init()
751 nvkm_wr32(device, 0x680000, chan->suspend_put); in gv100_disp_core_init()
752 nvkm_wr32(device, 0x6104e0, 0x00000013); in gv100_disp_core_init()
769 .ctrl = 0,
770 .user = 0,
788 *addr = 0x640000 + device->func->resource_addr(device, 0); in gv100_disp_caps_map()
789 *size = 0x1000; in gv100_disp_caps_map()
790 return 0; in gv100_disp_caps_map()
811 return 0; in gv100_disp_caps_new()
824 stat = nvkm_rd32(device, 0x6107a8); in gv100_disp_super()
828 mask[head->id] = nvkm_rd32(device, 0x6107ac + (head->id * 4)); in gv100_disp_super()
832 if (disp->super.pending & 0x00000001) { in gv100_disp_super()
833 nv50_disp_chan_mthd(disp->chan[0], NV_DBG_DEBUG); in gv100_disp_super()
836 if (!(mask[head->id] & 0x00001000)) in gv100_disp_super()
841 if (disp->super.pending & 0x00000002) { in gv100_disp_super()
843 if (!(mask[head->id] & 0x00001000)) in gv100_disp_super()
849 if (!(mask[head->id] & 0x00010000)) in gv100_disp_super()
854 if (!(mask[head->id] & 0x00001000)) in gv100_disp_super()
859 if (disp->super.pending & 0x00000004) { in gv100_disp_super()
861 if (!(mask[head->id] & 0x00001000)) in gv100_disp_super()
868 nvkm_wr32(device, 0x6107ac + (head->id * 4), 0x00000000); in gv100_disp_super()
870 nvkm_wr32(device, 0x6107a8, 0x80000000); in gv100_disp_super()
879 u32 stat = nvkm_rd32(device, 0x611020 + (chid * 12)); in gv100_disp_exception()
880 u32 type = (stat & 0x00007000) >> 12; in gv100_disp_exception()
881 u32 mthd = (stat & 0x00000fff) << 2; in gv100_disp_exception()
891 u32 data = nvkm_rd32(device, 0x611024 + (chid * 12)); in gv100_disp_exception()
892 u32 code = nvkm_rd32(device, 0x611028 + (chid * 12)); in gv100_disp_exception()
905 case 0x0200: in gv100_disp_exception()
913 nvkm_wr32(device, 0x611020 + (chid * 12), 0x90000000); in gv100_disp_exception()
921 u32 stat = nvkm_rd32(device, 0x611c30); in gv100_disp_intr_ctrl_disp()
923 if (stat & 0x00000007) { in gv100_disp_intr_ctrl_disp()
924 disp->super.pending = (stat & 0x00000007); in gv100_disp_intr_ctrl_disp()
926 nvkm_wr32(device, 0x611860, disp->super.pending); in gv100_disp_intr_ctrl_disp()
927 stat &= ~0x00000007; in gv100_disp_intr_ctrl_disp()
933 if (stat & 0x00000008) in gv100_disp_intr_ctrl_disp()
934 stat &= ~0x00000008; in gv100_disp_intr_ctrl_disp()
936 if (stat & 0x00000080) { in gv100_disp_intr_ctrl_disp()
937 u32 error = nvkm_mask(device, 0x611848, 0x00000000, 0x00000000); in gv100_disp_intr_ctrl_disp()
939 stat &= ~0x00000080; in gv100_disp_intr_ctrl_disp()
942 if (stat & 0x00000100) { in gv100_disp_intr_ctrl_disp()
943 unsigned long wndws = nvkm_rd32(device, 0x611858); in gv100_disp_intr_ctrl_disp()
944 unsigned long other = nvkm_rd32(device, 0x61185c); in gv100_disp_intr_ctrl_disp()
947 nvkm_wr32(device, 0x611858, wndws); in gv100_disp_intr_ctrl_disp()
948 nvkm_wr32(device, 0x61185c, other); in gv100_disp_intr_ctrl_disp()
951 if (other & 0x00000001) in gv100_disp_intr_ctrl_disp()
952 nv50_disp_chan_uevent_send(disp, 0); in gv100_disp_intr_ctrl_disp()
969 u32 stat = nvkm_rd32(device, 0x611854); in gv100_disp_intr_exc_other()
973 if (stat & 0x00000001) { in gv100_disp_intr_exc_other()
974 nvkm_wr32(device, 0x611854, 0x00000001); in gv100_disp_intr_exc_other()
975 gv100_disp_exception(disp, 0); in gv100_disp_intr_exc_other()
976 stat &= ~0x00000001; in gv100_disp_intr_exc_other()
979 if ((mask = (stat & 0x00ff0000) >> 16)) { in gv100_disp_intr_exc_other()
981 nvkm_wr32(device, 0x611854, 0x00010000 << head); in gv100_disp_intr_exc_other()
983 stat &= ~(0x00010000 << head); in gv100_disp_intr_exc_other()
989 nvkm_wr32(device, 0x611854, stat); in gv100_disp_intr_exc_other()
998 unsigned long stat = nvkm_rd32(device, 0x611850); in gv100_disp_intr_exc_winim()
1002 nvkm_wr32(device, 0x611850, BIT(wndw)); in gv100_disp_intr_exc_winim()
1009 nvkm_wr32(device, 0x611850, stat); in gv100_disp_intr_exc_winim()
1018 unsigned long stat = nvkm_rd32(device, 0x61184c); in gv100_disp_intr_exc_win()
1022 nvkm_wr32(device, 0x61184c, BIT(wndw)); in gv100_disp_intr_exc_win()
1029 nvkm_wr32(device, 0x61184c, stat); in gv100_disp_intr_exc_win()
1038 u32 stat = nvkm_rd32(device, 0x611800 + (head * 0x04)); in gv100_disp_intr_head_timing()
1041 if (stat & 0x00000003) { in gv100_disp_intr_head_timing()
1042 nvkm_wr32(device, 0x611800 + (head * 0x04), stat & 0x00000003); in gv100_disp_intr_head_timing()
1043 stat &= ~0x00000003; in gv100_disp_intr_head_timing()
1046 if (stat & 0x00000004) { in gv100_disp_intr_head_timing()
1048 nvkm_wr32(device, 0x611800 + (head * 0x04), 0x00000004); in gv100_disp_intr_head_timing()
1049 stat &= ~0x00000004; in gv100_disp_intr_head_timing()
1054 nvkm_wr32(device, 0x611800 + (head * 0x04), stat); in gv100_disp_intr_head_timing()
1063 u32 stat = nvkm_rd32(device, 0x611ec0); in gv100_disp_intr()
1067 if ((mask = (stat & 0x000000ff))) { in gv100_disp_intr()
1074 if (stat & 0x00000200) { in gv100_disp_intr()
1076 stat &= ~0x00000200; in gv100_disp_intr()
1079 if (stat & 0x00000400) { in gv100_disp_intr()
1081 stat &= ~0x00000400; in gv100_disp_intr()
1084 if (stat & 0x00000800) { in gv100_disp_intr()
1086 stat &= ~0x00000800; in gv100_disp_intr()
1089 if (stat & 0x00001000) { in gv100_disp_intr()
1091 stat &= ~0x00001000; in gv100_disp_intr()
1102 nvkm_wr32(device, 0x611db0, 0x00000000); in gv100_disp_fini()
1114 if (nvkm_rd32(device, 0x6254e8) & 0x00000002) { in gv100_disp_init()
1115 nvkm_mask(device, 0x6254e8, 0x00000001, 0x00000000); in gv100_disp_init()
1117 if (!(nvkm_rd32(device, 0x6254e8) & 0x00000002)) in gv100_disp_init()
1119 ) < 0) in gv100_disp_init()
1124 tmp = nvkm_rd32(device, 0x610068); in gv100_disp_init()
1125 nvkm_wr32(device, 0x640008, tmp); in gv100_disp_init()
1128 for (i = 0; i < disp->sor.nr; i++) { in gv100_disp_init()
1129 tmp = nvkm_rd32(device, 0x61c000 + (i * 0x800)); in gv100_disp_init()
1130 nvkm_mask(device, 0x640000, 0x00000100 << i, 0x00000100 << i); in gv100_disp_init()
1131 nvkm_wr32(device, 0x640144 + (i * 0x08), tmp); in gv100_disp_init()
1139 tmp = nvkm_rd32(device, 0x616300 + (id * 0x800)); in gv100_disp_init()
1140 nvkm_wr32(device, 0x640048 + (id * 0x020), tmp); in gv100_disp_init()
1143 for (j = 0; j < 6 * 4; j += 4) { in gv100_disp_init()
1144 tmp = nvkm_rd32(device, 0x616100 + (id * 0x800) + j); in gv100_disp_init()
1145 nvkm_wr32(device, 0x640030 + (id * 0x20) + j, tmp); in gv100_disp_init()
1150 for (i = 0; i < disp->wndw.nr; i++) { in gv100_disp_init()
1151 nvkm_mask(device, 0x640004, 1 << i, 1 << i); in gv100_disp_init()
1152 for (j = 0; j < 6 * 4; j += 4) { in gv100_disp_init()
1153 tmp = nvkm_rd32(device, 0x630050 + (i * 0x800) + j); in gv100_disp_init()
1154 nvkm_wr32(device, 0x6401e4 + (i * 0x20) + j, tmp); in gv100_disp_init()
1159 for (i = 0; i < 4; i++) { in gv100_disp_init()
1160 tmp = nvkm_rd32(device, 0x62e000 + (i * 0x04)); in gv100_disp_init()
1161 nvkm_wr32(device, 0x640010 + (i * 0x04), tmp); in gv100_disp_init()
1164 nvkm_mask(device, 0x610078, 0x00000001, 0x00000001); in gv100_disp_init()
1168 case NVKM_MEM_TARGET_VRAM: tmp = 0x00000001; break; in gv100_disp_init()
1169 case NVKM_MEM_TARGET_NCOH: tmp = 0x00000002; break; in gv100_disp_init()
1170 case NVKM_MEM_TARGET_HOST: tmp = 0x00000003; break; in gv100_disp_init()
1174 nvkm_wr32(device, 0x610010, 0x00000008 | tmp); in gv100_disp_init()
1175 nvkm_wr32(device, 0x610014, disp->inst->addr >> 16); in gv100_disp_init()
1178 nvkm_wr32(device, 0x611cf0, 0x00000187); /* MSK. */ in gv100_disp_init()
1179 nvkm_wr32(device, 0x611db0, 0x00000187); /* EN. */ in gv100_disp_init()
1182 nvkm_wr32(device, 0x611cec, disp->head.mask << 16 | in gv100_disp_init()
1183 0x00000001); /* MSK. */ in gv100_disp_init()
1184 nvkm_wr32(device, 0x611dac, 0x00000000); /* EN. */ in gv100_disp_init()
1187 nvkm_wr32(device, 0x611ce8, disp->wndw.mask); /* MSK. */ in gv100_disp_init()
1188 nvkm_wr32(device, 0x611da8, 0x00000000); /* EN. */ in gv100_disp_init()
1191 nvkm_wr32(device, 0x611ce4, disp->wndw.mask); /* MSK. */ in gv100_disp_init()
1192 nvkm_wr32(device, 0x611da4, 0x00000000); /* EN. */ in gv100_disp_init()
1197 nvkm_wr32(device, 0x611cc0 + hoff, 0x00000004); /* MSK. */ in gv100_disp_init()
1198 nvkm_wr32(device, 0x611d80 + hoff, 0x00000000); /* EN. */ in gv100_disp_init()
1202 nvkm_wr32(device, 0x611cf4, 0x00000000); /* MSK. */ in gv100_disp_init()
1203 nvkm_wr32(device, 0x611db4, 0x00000000); /* EN. */ in gv100_disp_init()
1204 return 0; in gv100_disp_init()
1218 .ramht_size = 0x2000,
1219 .root = { 0, 0,GV100_DISP },
1222 {{ 0, 0,GV100_DISP_CURSOR }, nvkm_disp_chan_new, &gv100_disp_curs },
1223 {{ 0, 0,GV100_DISP_WINDOW_IMM_CHANNEL_DMA}, nvkm_disp_wndw_new, &gv100_disp_wimm },
1224 {{ 0, 0,GV100_DISP_CORE_CHANNEL_DMA }, nvkm_disp_core_new, &gv100_disp_core },
1225 {{ 0, 0,GV100_DISP_WINDOW_CHANNEL_DMA }, nvkm_disp_wndw_new, &gv100_disp_wndw },