Lines Matching +full:0 +full:x000000ff
56 static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_PHY_LN()
58 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_PHY_LN_CFG_0()
60 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } in REG_DSI_28nm_PHY_LN_CFG_1()
62 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } in REG_DSI_28nm_PHY_LN_CFG_2()
64 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; } in REG_DSI_28nm_PHY_LN_CFG_3()
66 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; } in REG_DSI_28nm_PHY_LN_CFG_4()
68 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0… in REG_DSI_28nm_PHY_LN_TEST_DATAPATH()
70 static inline uint32_t REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; } in REG_DSI_28nm_PHY_LN_DEBUG_SEL()
72 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; } in REG_DSI_28nm_PHY_LN_TEST_STR_0()
74 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; } in REG_DSI_28nm_PHY_LN_TEST_STR_1()
76 #define REG_DSI_28nm_PHY_LNCK_CFG_0 0x00000100
78 #define REG_DSI_28nm_PHY_LNCK_CFG_1 0x00000104
80 #define REG_DSI_28nm_PHY_LNCK_CFG_2 0x00000108
82 #define REG_DSI_28nm_PHY_LNCK_CFG_3 0x0000010c
84 #define REG_DSI_28nm_PHY_LNCK_CFG_4 0x00000110
86 #define REG_DSI_28nm_PHY_LNCK_TEST_DATAPATH 0x00000114
88 #define REG_DSI_28nm_PHY_LNCK_DEBUG_SEL 0x00000118
90 #define REG_DSI_28nm_PHY_LNCK_TEST_STR0 0x0000011c
92 #define REG_DSI_28nm_PHY_LNCK_TEST_STR1 0x00000120
94 #define REG_DSI_28nm_PHY_TIMING_CTRL_0 0x00000140
95 #define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
96 #define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
102 #define REG_DSI_28nm_PHY_TIMING_CTRL_1 0x00000144
103 #define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
104 #define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
110 #define REG_DSI_28nm_PHY_TIMING_CTRL_2 0x00000148
111 #define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
112 #define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
118 #define REG_DSI_28nm_PHY_TIMING_CTRL_3 0x0000014c
119 #define DSI_28nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001
121 #define REG_DSI_28nm_PHY_TIMING_CTRL_4 0x00000150
122 #define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
123 #define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
129 #define REG_DSI_28nm_PHY_TIMING_CTRL_5 0x00000154
130 #define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
131 #define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
137 #define REG_DSI_28nm_PHY_TIMING_CTRL_6 0x00000158
138 #define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
139 #define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
145 #define REG_DSI_28nm_PHY_TIMING_CTRL_7 0x0000015c
146 #define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
147 #define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
153 #define REG_DSI_28nm_PHY_TIMING_CTRL_8 0x00000160
154 #define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
155 #define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
161 #define REG_DSI_28nm_PHY_TIMING_CTRL_9 0x00000164
162 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
163 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
168 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
175 #define REG_DSI_28nm_PHY_TIMING_CTRL_10 0x00000168
176 #define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
177 #define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
183 #define REG_DSI_28nm_PHY_TIMING_CTRL_11 0x0000016c
184 #define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
185 #define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
191 #define REG_DSI_28nm_PHY_CTRL_0 0x00000170
193 #define REG_DSI_28nm_PHY_CTRL_1 0x00000174
195 #define REG_DSI_28nm_PHY_CTRL_2 0x00000178
197 #define REG_DSI_28nm_PHY_CTRL_3 0x0000017c
199 #define REG_DSI_28nm_PHY_CTRL_4 0x00000180
201 #define REG_DSI_28nm_PHY_STRENGTH_0 0x00000184
203 #define REG_DSI_28nm_PHY_STRENGTH_1 0x00000188
205 #define REG_DSI_28nm_PHY_BIST_CTRL_0 0x000001b4
207 #define REG_DSI_28nm_PHY_BIST_CTRL_1 0x000001b8
209 #define REG_DSI_28nm_PHY_BIST_CTRL_2 0x000001bc
211 #define REG_DSI_28nm_PHY_BIST_CTRL_3 0x000001c0
213 #define REG_DSI_28nm_PHY_BIST_CTRL_4 0x000001c4
215 #define REG_DSI_28nm_PHY_BIST_CTRL_5 0x000001c8
217 #define REG_DSI_28nm_PHY_GLBL_TEST_CTRL 0x000001d4
218 #define DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001
220 #define REG_DSI_28nm_PHY_LDO_CNTRL 0x000001dc
222 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_0 0x00000000
224 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_1 0x00000004
226 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_2 0x00000008
228 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_3 0x0000000c
230 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_4 0x00000010
232 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_5 0x00000014
234 #define REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018
236 #define REG_DSI_28nm_PHY_PLL_REFCLK_CFG 0x00000000
237 #define DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR 0x00000001
239 #define REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004
241 #define REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008
243 #define REG_DSI_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c
245 #define REG_DSI_28nm_PHY_PLL_VREG_CFG 0x00000010
246 #define DSI_28nm_PHY_PLL_VREG_CFG_POSTDIV1_BYPASS_B 0x00000002
248 #define REG_DSI_28nm_PHY_PLL_PWRGEN_CFG 0x00000014
250 #define REG_DSI_28nm_PHY_PLL_DMUX_CFG 0x00000018
252 #define REG_DSI_28nm_PHY_PLL_AMUX_CFG 0x0000001c
254 #define REG_DSI_28nm_PHY_PLL_GLB_CFG 0x00000020
255 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001
256 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002
257 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004
258 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008
260 #define REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024
262 #define REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028
264 #define REG_DSI_28nm_PHY_PLL_LPFR_CFG 0x0000002c
266 #define REG_DSI_28nm_PHY_PLL_LPFC1_CFG 0x00000030
268 #define REG_DSI_28nm_PHY_PLL_LPFC2_CFG 0x00000034
270 #define REG_DSI_28nm_PHY_PLL_SDM_CFG0 0x00000038
271 #define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK 0x0000003f
272 #define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT 0
277 #define DSI_28nm_PHY_PLL_SDM_CFG0_BYP 0x00000040
279 #define REG_DSI_28nm_PHY_PLL_SDM_CFG1 0x0000003c
280 #define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK 0x0000003f
281 #define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT 0
286 #define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK 0x00000040
293 #define REG_DSI_28nm_PHY_PLL_SDM_CFG2 0x00000040
294 #define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK 0x000000ff
295 #define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT 0
301 #define REG_DSI_28nm_PHY_PLL_SDM_CFG3 0x00000044
302 #define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK 0x000000ff
303 #define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT 0
309 #define REG_DSI_28nm_PHY_PLL_SDM_CFG4 0x00000048
311 #define REG_DSI_28nm_PHY_PLL_SSC_CFG0 0x0000004c
313 #define REG_DSI_28nm_PHY_PLL_SSC_CFG1 0x00000050
315 #define REG_DSI_28nm_PHY_PLL_SSC_CFG2 0x00000054
317 #define REG_DSI_28nm_PHY_PLL_SSC_CFG3 0x00000058
319 #define REG_DSI_28nm_PHY_PLL_LKDET_CFG0 0x0000005c
321 #define REG_DSI_28nm_PHY_PLL_LKDET_CFG1 0x00000060
323 #define REG_DSI_28nm_PHY_PLL_LKDET_CFG2 0x00000064
325 #define REG_DSI_28nm_PHY_PLL_TEST_CFG 0x00000068
326 #define DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001
328 #define REG_DSI_28nm_PHY_PLL_CAL_CFG0 0x0000006c
330 #define REG_DSI_28nm_PHY_PLL_CAL_CFG1 0x00000070
332 #define REG_DSI_28nm_PHY_PLL_CAL_CFG2 0x00000074
334 #define REG_DSI_28nm_PHY_PLL_CAL_CFG3 0x00000078
336 #define REG_DSI_28nm_PHY_PLL_CAL_CFG4 0x0000007c
338 #define REG_DSI_28nm_PHY_PLL_CAL_CFG5 0x00000080
340 #define REG_DSI_28nm_PHY_PLL_CAL_CFG6 0x00000084
342 #define REG_DSI_28nm_PHY_PLL_CAL_CFG7 0x00000088
344 #define REG_DSI_28nm_PHY_PLL_CAL_CFG8 0x0000008c
346 #define REG_DSI_28nm_PHY_PLL_CAL_CFG9 0x00000090
348 #define REG_DSI_28nm_PHY_PLL_CAL_CFG10 0x00000094
350 #define REG_DSI_28nm_PHY_PLL_CAL_CFG11 0x00000098
352 #define REG_DSI_28nm_PHY_PLL_EFUSE_CFG 0x0000009c
354 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0
356 #define REG_DSI_28nm_PHY_PLL_CTRL_42 0x000000a4
358 #define REG_DSI_28nm_PHY_PLL_CTRL_43 0x000000a8
360 #define REG_DSI_28nm_PHY_PLL_CTRL_44 0x000000ac
362 #define REG_DSI_28nm_PHY_PLL_CTRL_45 0x000000b0
364 #define REG_DSI_28nm_PHY_PLL_CTRL_46 0x000000b4
366 #define REG_DSI_28nm_PHY_PLL_CTRL_47 0x000000b8
368 #define REG_DSI_28nm_PHY_PLL_CTRL_48 0x000000bc
370 #define REG_DSI_28nm_PHY_PLL_STATUS 0x000000c0
371 #define DSI_28nm_PHY_PLL_STATUS_PLL_RDY 0x00000001
373 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS0 0x000000c4
375 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS1 0x000000c8
377 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS2 0x000000cc
379 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS3 0x000000d0
381 #define REG_DSI_28nm_PHY_PLL_CTRL_54 0x000000d4