201 static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data)  in dsi_write()  function
692 	dsi_write(msm_host, REG_DSI_INTR_CTRL, intr);  in dsi_intr_ctrl()
739 		dsi_write(msm_host, REG_DSI_CTRL, 0);  in dsi_ctrl_config()
760 		dsi_write(msm_host, REG_DSI_VID_CFG0, data);  in dsi_ctrl_config()
764 		dsi_write(msm_host, REG_DSI_VID_CFG1, 0);  in dsi_ctrl_config()
769 		dsi_write(msm_host, REG_DSI_CMD_CFG0, data);  in dsi_ctrl_config()
776 		dsi_write(msm_host, REG_DSI_CMD_CFG1, data);  in dsi_ctrl_config()
779 	dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL,  in dsi_ctrl_config()
792 	dsi_write(msm_host, REG_DSI_TRIG_CTRL, data);  in dsi_ctrl_config()
796 	dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data);  in dsi_ctrl_config()
801 		dsi_write(msm_host, REG_DSI_T_CLK_PRE_EXTEND,  in dsi_ctrl_config()
807 	dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data);  in dsi_ctrl_config()
810 	dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0);  in dsi_ctrl_config()
814 	dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);  in dsi_ctrl_config()
821 	dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,  in dsi_ctrl_config()
830 		dsi_write(msm_host, REG_DSI_LANE_CTRL,  in dsi_ctrl_config()
836 	dsi_write(msm_host, REG_DSI_CTRL, data);  in dsi_ctrl_config()
839 		dsi_write(msm_host, REG_DSI_CPHY_MODE_CTRL, BIT(0));  in dsi_ctrl_config()
897 		dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg_ctrl);  in dsi_update_dsc_timing()
898 		dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2);  in dsi_update_dsc_timing()
900 		dsi_write(msm_host, REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg);  in dsi_update_dsc_timing()
968 		dsi_write(msm_host, REG_DSI_ACTIVE_H,  in dsi_timing_setup()
971 		dsi_write(msm_host, REG_DSI_ACTIVE_V,  in dsi_timing_setup()
974 		dsi_write(msm_host, REG_DSI_TOTAL,  in dsi_timing_setup()
978 		dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC,  in dsi_timing_setup()
981 		dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0);  in dsi_timing_setup()
982 		dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS,  in dsi_timing_setup()
995 		dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL,  in dsi_timing_setup()
1002 		dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_TOTAL,  in dsi_timing_setup()
1015 		dsi_write(msm_host, REG_DSI_CTRL, ctrl & ~DSI_CTRL_ENABLE);  in dsi_sw_reset()
1023 	dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);  in dsi_sw_reset()
1027 	dsi_write(msm_host, REG_DSI_RESET, 1);  in dsi_sw_reset()
1029 	dsi_write(msm_host, REG_DSI_RESET, 0);  in dsi_sw_reset()
1033 		dsi_write(msm_host, REG_DSI_CTRL, ctrl);  in dsi_sw_reset()
1060 	dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl);  in dsi_op_mode_config()
1074 	dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data);  in dsi_set_tx_power_mode()
1452 		dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status);  in dsi_ack_err_status()
1454 		dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0);  in dsi_ack_err_status()
1466 		dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status);  in dsi_timeout_status()
1482 		dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status);  in dsi_dln0_phy_err()
1495 		dsi_write(msm_host, REG_DSI_FIFO_STATUS, status);  in dsi_fifo_status()
1510 		dsi_write(msm_host, REG_DSI_STATUS0, status);  in dsi_status()
1523 		dsi_write(msm_host, REG_DSI_CLK_STATUS, status);  in dsi_clk_status()
1554 	dsi_write(msm_host, REG_DSI_INTR_CTRL, isr);  in dsi_host_irq()
2134 	dsi_write(msm_host, REG_DSI_CTRL,  in msm_dsi_host_xfer_prepare()
2150 	dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore);  in msm_dsi_host_xfer_restore()
2218 			dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL,  in msm_dsi_host_cmd_rx()
2221 			dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0);  in msm_dsi_host_cmd_rx()
2312 	dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base);  in msm_dsi_host_cmd_xfer_commit()
2313 	dsi_write(msm_host, REG_DSI_DMA_LEN, len);  in msm_dsi_host_cmd_xfer_commit()
2314 	dsi_write(msm_host, REG_DSI_TRIG_DMA, 1);  in msm_dsi_host_cmd_xfer_commit()
2333 	dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET);  in msm_dsi_host_reset_phy()
2337 	dsi_write(msm_host, REG_DSI_PHY_RESET, 0);  in msm_dsi_host_reset_phy()
2598 	dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_VIDEO_INIT_VAL, 0xff);  in msm_dsi_host_video_test_pattern_setup()
2600 	dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL,  in msm_dsi_host_video_test_pattern_setup()
2603 	dsi_write(msm_host, REG_DSI_TPG_VIDEO_CONFIG,  in msm_dsi_host_video_test_pattern_setup()
2608 	dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg);  in msm_dsi_host_video_test_pattern_setup()
2620 	dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0, 0xff);  in msm_dsi_host_cmd_test_pattern_setup()
2624 	dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg);  in msm_dsi_host_cmd_test_pattern_setup()
2626 	dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL2,  in msm_dsi_host_cmd_test_pattern_setup()
2645 	dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, (reg | DSI_TEST_PATTERN_GEN_CTRL_EN));  in msm_dsi_host_test_pattern_en()
2649 		dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER,  in msm_dsi_host_test_pattern_en()