191 static inline uint32_t MDSS_HW_VERSION_STEP(uint32_t val)  in MDSS_HW_VERSION_STEP()
197 static inline uint32_t MDSS_HW_VERSION_MINOR(uint32_t val)  in MDSS_HW_VERSION_MINOR()
203 static inline uint32_t MDSS_HW_VERSION_MAJOR(uint32_t val)  in MDSS_HW_VERSION_MAJOR()
218 static inline uint32_t MDP5_HW_VERSION_STEP(uint32_t val)  in MDP5_HW_VERSION_STEP()
224 static inline uint32_t MDP5_HW_VERSION_MINOR(uint32_t val)  in MDP5_HW_VERSION_MINOR()
230 static inline uint32_t MDP5_HW_VERSION_MAJOR(uint32_t val)  in MDP5_HW_VERSION_MAJOR()
238 static inline uint32_t MDP5_DISP_INTF_SEL_INTF0(enum mdp5_intf_type val)  in MDP5_DISP_INTF_SEL_INTF0()
244 static inline uint32_t MDP5_DISP_INTF_SEL_INTF1(enum mdp5_intf_type val)  in MDP5_DISP_INTF_SEL_INTF1()
250 static inline uint32_t MDP5_DISP_INTF_SEL_INTF2(enum mdp5_intf_type val)  in MDP5_DISP_INTF_SEL_INTF2()
256 static inline uint32_t MDP5_DISP_INTF_SEL_INTF3(enum mdp5_intf_type val)  in MDP5_DISP_INTF_SEL_INTF3()
276 static inline uint32_t REG_MDP5_SMP_ALLOC_W(uint32_t i0) { return 0x00000080 + 0x4*i0; }  in REG_MDP5_SMP_ALLOC_W()
278 static inline uint32_t REG_MDP5_SMP_ALLOC_W_REG(uint32_t i0) { return 0x00000080 + 0x4*i0; }  in REG_MDP5_SMP_ALLOC_W_REG()
281 static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT0(uint32_t val)  in MDP5_SMP_ALLOC_W_REG_CLIENT0()
287 static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT1(uint32_t val)  in MDP5_SMP_ALLOC_W_REG_CLIENT1()
293 static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT2(uint32_t val)  in MDP5_SMP_ALLOC_W_REG_CLIENT2()
298 static inline uint32_t REG_MDP5_SMP_ALLOC_R(uint32_t i0) { return 0x00000130 + 0x4*i0; }  in REG_MDP5_SMP_ALLOC_R()
300 static inline uint32_t REG_MDP5_SMP_ALLOC_R_REG(uint32_t i0) { return 0x00000130 + 0x4*i0; }  in REG_MDP5_SMP_ALLOC_R_REG()
303 static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT0(uint32_t val)  in MDP5_SMP_ALLOC_R_REG_CLIENT0()
309 static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT1(uint32_t val)  in MDP5_SMP_ALLOC_R_REG_CLIENT1()
315 static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT2(uint32_t val)  in MDP5_SMP_ALLOC_R_REG_CLIENT2()
320 static inline uint32_t __offset_IGC(enum mdp5_igc_type idx)  in __offset_IGC()
330 static inline uint32_t REG_MDP5_IGC(enum mdp5_igc_type i0) { return 0x00000000 + __offset_IGC(i0); }  in REG_MDP5_IGC()
332 static inline uint32_t REG_MDP5_IGC_LUT(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + _…  in REG_MDP5_IGC_LUT()
334 static inline uint32_t REG_MDP5_IGC_LUT_REG(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000…  in REG_MDP5_IGC_LUT_REG()
337 static inline uint32_t MDP5_IGC_LUT_REG_VAL(uint32_t val)  in MDP5_IGC_LUT_REG_VAL()
360 static inline uint32_t __offset_CTL(uint32_t idx)  in __offset_CTL()
371 static inline uint32_t REG_MDP5_CTL(uint32_t i0) { return 0x00000000 + __offset_CTL(i0); }  in REG_MDP5_CTL()
373 static inline uint32_t __offset_LAYER(uint32_t idx)  in __offset_LAYER()
385 static inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_…  in REG_MDP5_CTL_LAYER()
387 static inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __off…  in REG_MDP5_CTL_LAYER_REG()
390 static inline uint32_t MDP5_CTL_LAYER_REG_VIG0(uint32_t val)  in MDP5_CTL_LAYER_REG_VIG0()
396 static inline uint32_t MDP5_CTL_LAYER_REG_VIG1(uint32_t val)  in MDP5_CTL_LAYER_REG_VIG1()
402 static inline uint32_t MDP5_CTL_LAYER_REG_VIG2(uint32_t val)  in MDP5_CTL_LAYER_REG_VIG2()
408 static inline uint32_t MDP5_CTL_LAYER_REG_RGB0(uint32_t val)  in MDP5_CTL_LAYER_REG_RGB0()
414 static inline uint32_t MDP5_CTL_LAYER_REG_RGB1(uint32_t val)  in MDP5_CTL_LAYER_REG_RGB1()
420 static inline uint32_t MDP5_CTL_LAYER_REG_RGB2(uint32_t val)  in MDP5_CTL_LAYER_REG_RGB2()
426 static inline uint32_t MDP5_CTL_LAYER_REG_DMA0(uint32_t val)  in MDP5_CTL_LAYER_REG_DMA0()
432 static inline uint32_t MDP5_CTL_LAYER_REG_DMA1(uint32_t val)  in MDP5_CTL_LAYER_REG_DMA1()
440 static inline uint32_t MDP5_CTL_LAYER_REG_VIG3(uint32_t val)  in MDP5_CTL_LAYER_REG_VIG3()
446 static inline uint32_t MDP5_CTL_LAYER_REG_RGB3(uint32_t val)  in MDP5_CTL_LAYER_REG_RGB3()
451 static inline uint32_t REG_MDP5_CTL_OP(uint32_t i0) { return 0x00000014 + __offset_CTL(i0); }  in REG_MDP5_CTL_OP()
454 static inline uint32_t MDP5_CTL_OP_MODE(enum mdp5_ctl_mode val)  in MDP5_CTL_OP_MODE()
460 static inline uint32_t MDP5_CTL_OP_INTF_NUM(enum mdp5_intfnum val)  in MDP5_CTL_OP_INTF_NUM()
468 static inline uint32_t MDP5_CTL_OP_PACK_3D(enum mdp5_pack_3d val)  in MDP5_CTL_OP_PACK_3D()
473 static inline uint32_t REG_MDP5_CTL_FLUSH(uint32_t i0) { return 0x00000018 + __offset_CTL(i0); }  in REG_MDP5_CTL_FLUSH()
504 static inline uint32_t REG_MDP5_CTL_START(uint32_t i0) { return 0x0000001c + __offset_CTL(i0); }  in REG_MDP5_CTL_START()
506 static inline uint32_t REG_MDP5_CTL_PACK_3D(uint32_t i0) { return 0x00000020 + __offset_CTL(i0); }  in REG_MDP5_CTL_PACK_3D()
508 static inline uint32_t __offset_LAYER_EXT(uint32_t idx)  in __offset_LAYER_EXT()
520 static inline uint32_t REG_MDP5_CTL_LAYER_EXT(uint32_t i0, uint32_t i1) { return 0x00000000 + __off…  in REG_MDP5_CTL_LAYER_EXT()
522 static inline uint32_t REG_MDP5_CTL_LAYER_EXT_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + _…  in REG_MDP5_CTL_LAYER_EXT_REG()
535 static inline uint32_t MDP5_CTL_LAYER_EXT_REG_CURSOR0(enum mdp_mixer_stage_id val)  in MDP5_CTL_LAYER_EXT_REG_CURSOR0()
541 static inline uint32_t MDP5_CTL_LAYER_EXT_REG_CURSOR1(enum mdp_mixer_stage_id val)  in MDP5_CTL_LAYER_EXT_REG_CURSOR1()
546 static inline uint32_t __offset_PIPE(enum mdp5_pipe idx)  in __offset_PIPE()
565 static inline uint32_t REG_MDP5_PIPE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); }  in REG_MDP5_PIPE()
567 static inline uint32_t REG_MDP5_PIPE_OP_MODE(enum mdp5_pipe i0) { return 0x00000200 + __offset_PIPE…  in REG_MDP5_PIPE_OP_MODE()
570 static inline uint32_t MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(enum mdp5_data_format val)  in MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT()
576 static inline uint32_t MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(enum mdp5_data_format val)  in MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT()
582 static inline uint32_t REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0) { return 0x000002c4 + __offse…  in REG_MDP5_PIPE_HIST_CTL_BASE()
584 static inline uint32_t REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0) { return 0x000002f0 + __offse…  in REG_MDP5_PIPE_HIST_LUT_BASE()
586 static inline uint32_t REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0) { return 0x00000300 + __offse…  in REG_MDP5_PIPE_HIST_LUT_SWAP()
588 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(enum mdp5_pipe i0) { return 0x00000320 + …  in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0()
591 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(uint32_t val)  in MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11()
597 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(uint32_t val)  in MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12()
602 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(enum mdp5_pipe i0) { return 0x00000324 + …  in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1()
605 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(uint32_t val)  in MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13()
611 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(uint32_t val)  in MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21()
616 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(enum mdp5_pipe i0) { return 0x00000328 + …  in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2()
619 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(uint32_t val)  in MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22()
625 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(uint32_t val)  in MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23()
630 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(enum mdp5_pipe i0) { return 0x0000032c + …  in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3()
633 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(uint32_t val)  in MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31()
639 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(uint32_t val)  in MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32()
644 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(enum mdp5_pipe i0) { return 0x00000330 + …  in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4()
647 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(uint32_t val)  in MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33()
652 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x000…  in REG_MDP5_PIPE_CSC_1_PRE_CLAMP()
654 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0…  in REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG()
657 static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(uint32_t val)  in MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH()
663 static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(uint32_t val)  in MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW()
668 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00…  in REG_MDP5_PIPE_CSC_1_POST_CLAMP()
670 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return …  in REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG()
673 static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(uint32_t val)  in MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH()
679 static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(uint32_t val)  in MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW()
684 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x0000…  in REG_MDP5_PIPE_CSC_1_PRE_BIAS()
686 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x…  in REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG()
689 static inline uint32_t MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(uint32_t val)  in MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE()
694 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x000…  in REG_MDP5_PIPE_CSC_1_POST_BIAS()
696 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0…  in REG_MDP5_PIPE_CSC_1_POST_BIAS_REG()
699 static inline uint32_t MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(uint32_t val)  in MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE()
704 static inline uint32_t REG_MDP5_PIPE_SRC_SIZE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIP…  in REG_MDP5_PIPE_SRC_SIZE()
707 static inline uint32_t MDP5_PIPE_SRC_SIZE_HEIGHT(uint32_t val)  in MDP5_PIPE_SRC_SIZE_HEIGHT()
713 static inline uint32_t MDP5_PIPE_SRC_SIZE_WIDTH(uint32_t val)  in MDP5_PIPE_SRC_SIZE_WIDTH()
718 static inline uint32_t REG_MDP5_PIPE_SRC_IMG_SIZE(enum mdp5_pipe i0) { return 0x00000004 + __offset…  in REG_MDP5_PIPE_SRC_IMG_SIZE()
721 static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(uint32_t val)  in MDP5_PIPE_SRC_IMG_SIZE_HEIGHT()
727 static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_WIDTH(uint32_t val)  in MDP5_PIPE_SRC_IMG_SIZE_WIDTH()
732 static inline uint32_t REG_MDP5_PIPE_SRC_XY(enum mdp5_pipe i0) { return 0x00000008 + __offset_PIPE(…  in REG_MDP5_PIPE_SRC_XY()
735 static inline uint32_t MDP5_PIPE_SRC_XY_Y(uint32_t val)  in MDP5_PIPE_SRC_XY_Y()
741 static inline uint32_t MDP5_PIPE_SRC_XY_X(uint32_t val)  in MDP5_PIPE_SRC_XY_X()
746 static inline uint32_t REG_MDP5_PIPE_OUT_SIZE(enum mdp5_pipe i0) { return 0x0000000c + __offset_PIP…  in REG_MDP5_PIPE_OUT_SIZE()
749 static inline uint32_t MDP5_PIPE_OUT_SIZE_HEIGHT(uint32_t val)  in MDP5_PIPE_OUT_SIZE_HEIGHT()
755 static inline uint32_t MDP5_PIPE_OUT_SIZE_WIDTH(uint32_t val)  in MDP5_PIPE_OUT_SIZE_WIDTH()
760 static inline uint32_t REG_MDP5_PIPE_OUT_XY(enum mdp5_pipe i0) { return 0x00000010 + __offset_PIPE(…  in REG_MDP5_PIPE_OUT_XY()
763 static inline uint32_t MDP5_PIPE_OUT_XY_Y(uint32_t val)  in MDP5_PIPE_OUT_XY_Y()
769 static inline uint32_t MDP5_PIPE_OUT_XY_X(uint32_t val)  in MDP5_PIPE_OUT_XY_X()
774 static inline uint32_t REG_MDP5_PIPE_SRC0_ADDR(enum mdp5_pipe i0) { return 0x00000014 + __offset_PI…  in REG_MDP5_PIPE_SRC0_ADDR()
776 static inline uint32_t REG_MDP5_PIPE_SRC1_ADDR(enum mdp5_pipe i0) { return 0x00000018 + __offset_PI…  in REG_MDP5_PIPE_SRC1_ADDR()
778 static inline uint32_t REG_MDP5_PIPE_SRC2_ADDR(enum mdp5_pipe i0) { return 0x0000001c + __offset_PI…  in REG_MDP5_PIPE_SRC2_ADDR()
780 static inline uint32_t REG_MDP5_PIPE_SRC3_ADDR(enum mdp5_pipe i0) { return 0x00000020 + __offset_PI…  in REG_MDP5_PIPE_SRC3_ADDR()
782 static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_A(enum mdp5_pipe i0) { return 0x00000024 + __offset…  in REG_MDP5_PIPE_SRC_STRIDE_A()
785 static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P0(uint32_t val)  in MDP5_PIPE_SRC_STRIDE_A_P0()
791 static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P1(uint32_t val)  in MDP5_PIPE_SRC_STRIDE_A_P1()
796 static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_B(enum mdp5_pipe i0) { return 0x00000028 + __offset…  in REG_MDP5_PIPE_SRC_STRIDE_B()
799 static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P2(uint32_t val)  in MDP5_PIPE_SRC_STRIDE_B_P2()
805 static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P3(uint32_t val)  in MDP5_PIPE_SRC_STRIDE_B_P3()
810 static inline uint32_t REG_MDP5_PIPE_STILE_FRAME_SIZE(enum mdp5_pipe i0) { return 0x0000002c + __of…  in REG_MDP5_PIPE_STILE_FRAME_SIZE()
812 static inline uint32_t REG_MDP5_PIPE_SRC_FORMAT(enum mdp5_pipe i0) { return 0x00000030 + __offset_P…  in REG_MDP5_PIPE_SRC_FORMAT()
815 static inline uint32_t MDP5_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val)  in MDP5_PIPE_SRC_FORMAT_G_BPC()
821 static inline uint32_t MDP5_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val)  in MDP5_PIPE_SRC_FORMAT_B_BPC()
827 static inline uint32_t MDP5_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val)  in MDP5_PIPE_SRC_FORMAT_R_BPC()
833 static inline uint32_t MDP5_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val)  in MDP5_PIPE_SRC_FORMAT_A_BPC()
840 static inline uint32_t MDP5_PIPE_SRC_FORMAT_CPP(uint32_t val)  in MDP5_PIPE_SRC_FORMAT_CPP()
847 static inline uint32_t MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)  in MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT()
855 static inline uint32_t MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(enum mdp_fetch_type val)  in MDP5_PIPE_SRC_FORMAT_FETCH_TYPE()
861 static inline uint32_t MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val)  in MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP()
866 static inline uint32_t REG_MDP5_PIPE_SRC_UNPACK(enum mdp5_pipe i0) { return 0x00000034 + __offset_P…  in REG_MDP5_PIPE_SRC_UNPACK()
869 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM0(uint32_t val)  in MDP5_PIPE_SRC_UNPACK_ELEM0()
875 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM1(uint32_t val)  in MDP5_PIPE_SRC_UNPACK_ELEM1()
881 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM2(uint32_t val)  in MDP5_PIPE_SRC_UNPACK_ELEM2()
887 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM3(uint32_t val)  in MDP5_PIPE_SRC_UNPACK_ELEM3()
892 static inline uint32_t REG_MDP5_PIPE_SRC_OP_MODE(enum mdp5_pipe i0) { return 0x00000038 + __offset_…  in REG_MDP5_PIPE_SRC_OP_MODE()
896 static inline uint32_t MDP5_PIPE_SRC_OP_MODE_BWC(enum mdp5_pipe_bwc val)  in MDP5_PIPE_SRC_OP_MODE_BWC()
909 static inline uint32_t REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0) { return 0x0000003c + __…  in REG_MDP5_PIPE_SRC_CONSTANT_COLOR()
911 static inline uint32_t REG_MDP5_PIPE_FETCH_CONFIG(enum mdp5_pipe i0) { return 0x00000048 + __offset…  in REG_MDP5_PIPE_FETCH_CONFIG()
913 static inline uint32_t REG_MDP5_PIPE_VC1_RANGE(enum mdp5_pipe i0) { return 0x0000004c + __offset_PI…  in REG_MDP5_PIPE_VC1_RANGE()
915 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(enum mdp5_pipe i0) { return 0x00000050 + __o…  in REG_MDP5_PIPE_REQPRIO_FIFO_WM_0()
917 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(enum mdp5_pipe i0) { return 0x00000054 + __o…  in REG_MDP5_PIPE_REQPRIO_FIFO_WM_1()
919 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(enum mdp5_pipe i0) { return 0x00000058 + __o…  in REG_MDP5_PIPE_REQPRIO_FIFO_WM_2()
921 static inline uint32_t REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(enum mdp5_pipe i0) { return 0x00000070 + __…  in REG_MDP5_PIPE_SRC_ADDR_SW_STATUS()
923 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC0_ADDR(enum mdp5_pipe i0) { return 0x000000a4 + __o…  in REG_MDP5_PIPE_CURRENT_SRC0_ADDR()
925 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC1_ADDR(enum mdp5_pipe i0) { return 0x000000a8 + __o…  in REG_MDP5_PIPE_CURRENT_SRC1_ADDR()
927 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC2_ADDR(enum mdp5_pipe i0) { return 0x000000ac + __o…  in REG_MDP5_PIPE_CURRENT_SRC2_ADDR()
929 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC3_ADDR(enum mdp5_pipe i0) { return 0x000000b0 + __o…  in REG_MDP5_PIPE_CURRENT_SRC3_ADDR()
931 static inline uint32_t REG_MDP5_PIPE_DECIMATION(enum mdp5_pipe i0) { return 0x000000b4 + __offset_P…  in REG_MDP5_PIPE_DECIMATION()
934 static inline uint32_t MDP5_PIPE_DECIMATION_VERT(uint32_t val)  in MDP5_PIPE_DECIMATION_VERT()
940 static inline uint32_t MDP5_PIPE_DECIMATION_HORZ(uint32_t val)  in MDP5_PIPE_DECIMATION_HORZ()
945 static inline uint32_t __offset_SW_PIX_EXT(enum mdp_component_type idx)  in __offset_SW_PIX_EXT()
954 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT(enum mdp5_pipe i0, enum mdp_component_type i1) { re…  in REG_MDP5_PIPE_SW_PIX_EXT()
956 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_LR(enum mdp5_pipe i0, enum mdp_component_type i1) {…  in REG_MDP5_PIPE_SW_PIX_EXT_LR()
959 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(uint32_t val)  in MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT()
965 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(int32_t val)  in MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF()
971 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(uint32_t val)  in MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT()
977 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(int32_t val)  in MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF()
982 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_TB(enum mdp5_pipe i0, enum mdp_component_type i1) {…  in REG_MDP5_PIPE_SW_PIX_EXT_TB()
985 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(uint32_t val)  in MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT()
991 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(int32_t val)  in MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF()
997 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(uint32_t val)  in MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT()
1003 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(int32_t val)  in MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF()
1008 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(enum mdp5_pipe i0, enum mdp_component_ty…  in REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS()
1011 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(uint32_t val)  in MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT()
1017 static inline uint32_t MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(uint32_t val)  in MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM()
1022 static inline uint32_t REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) { return 0x00000204 + __offset…  in REG_MDP5_PIPE_SCALE_CONFIG()
1027 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(enum mdp5_scale_filter val)  in MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0()
1033 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(enum mdp5_scale_filter val)  in MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0()
1039 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(enum mdp5_scale_filter val)  in MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2()
1045 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(enum mdp5_scale_filter val)  in MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2()
1051 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(enum mdp5_scale_filter val)  in MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3()
1057 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(enum mdp5_scale_filter val)  in MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3()
1062 static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000210 + __…  in REG_MDP5_PIPE_SCALE_PHASE_STEP_X()
1064 static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x00000214 + __…  in REG_MDP5_PIPE_SCALE_PHASE_STEP_Y()
1066 static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000218 +…  in REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X()
1068 static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x0000021c +…  in REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y()
1070 static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_X(enum mdp5_pipe i0) { return 0x00000220 + __…  in REG_MDP5_PIPE_SCALE_INIT_PHASE_X()
1072 static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_Y(enum mdp5_pipe i0) { return 0x00000224 + __…  in REG_MDP5_PIPE_SCALE_INIT_PHASE_Y()
1074 static inline uint32_t __offset_LM(uint32_t idx)  in __offset_LM()
1086 static inline uint32_t REG_MDP5_LM(uint32_t i0) { return 0x00000000 + __offset_LM(i0); }  in REG_MDP5_LM()
1088 static inline uint32_t REG_MDP5_LM_BLEND_COLOR_OUT(uint32_t i0) { return 0x00000000 + __offset_LM(i…  in REG_MDP5_LM_BLEND_COLOR_OUT()
1098 static inline uint32_t REG_MDP5_LM_OUT_SIZE(uint32_t i0) { return 0x00000004 + __offset_LM(i0); }  in REG_MDP5_LM_OUT_SIZE()
1101 static inline uint32_t MDP5_LM_OUT_SIZE_HEIGHT(uint32_t val)  in MDP5_LM_OUT_SIZE_HEIGHT()
1107 static inline uint32_t MDP5_LM_OUT_SIZE_WIDTH(uint32_t val)  in MDP5_LM_OUT_SIZE_WIDTH()
1112 static inline uint32_t REG_MDP5_LM_BORDER_COLOR_0(uint32_t i0) { return 0x00000008 + __offset_LM(i0…  in REG_MDP5_LM_BORDER_COLOR_0()
1114 static inline uint32_t REG_MDP5_LM_BORDER_COLOR_1(uint32_t i0) { return 0x00000010 + __offset_LM(i0…  in REG_MDP5_LM_BORDER_COLOR_1()
1116 static inline uint32_t __offset_BLEND(uint32_t idx)  in __offset_BLEND()
1129 static inline uint32_t REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_L…  in REG_MDP5_LM_BLEND()
1131 static inline uint32_t REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) { return 0x00000000 + __…  in REG_MDP5_LM_BLEND_OP_MODE()
1134 static inline uint32_t MDP5_LM_BLEND_OP_MODE_FG_ALPHA(enum mdp_alpha_type val)  in MDP5_LM_BLEND_OP_MODE_FG_ALPHA()
1144 static inline uint32_t MDP5_LM_BLEND_OP_MODE_BG_ALPHA(enum mdp_alpha_type val)  in MDP5_LM_BLEND_OP_MODE_BG_ALPHA()
1153 static inline uint32_t REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + _…  in REG_MDP5_LM_BLEND_FG_ALPHA()
1155 static inline uint32_t REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + _…  in REG_MDP5_LM_BLEND_BG_ALPHA()
1157 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x000000…  in REG_MDP5_LM_BLEND_FG_TRANSP_LOW0()
1159 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x000000…  in REG_MDP5_LM_BLEND_FG_TRANSP_LOW1()
1161 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000…  in REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0()
1163 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000…  in REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1()
1165 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x000000…  in REG_MDP5_LM_BLEND_BG_TRANSP_LOW0()
1167 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x000000…  in REG_MDP5_LM_BLEND_BG_TRANSP_LOW1()
1169 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000…  in REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0()
1171 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000…  in REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1()
1173 static inline uint32_t REG_MDP5_LM_CURSOR_IMG_SIZE(uint32_t i0) { return 0x000000e0 + __offset_LM(i…  in REG_MDP5_LM_CURSOR_IMG_SIZE()
1176 static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_W(uint32_t val)  in MDP5_LM_CURSOR_IMG_SIZE_SRC_W()
1182 static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_H(uint32_t val)  in MDP5_LM_CURSOR_IMG_SIZE_SRC_H()
1187 static inline uint32_t REG_MDP5_LM_CURSOR_SIZE(uint32_t i0) { return 0x000000e4 + __offset_LM(i0); }  in REG_MDP5_LM_CURSOR_SIZE()
1190 static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_W(uint32_t val)  in MDP5_LM_CURSOR_SIZE_ROI_W()
1196 static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_H(uint32_t val)  in MDP5_LM_CURSOR_SIZE_ROI_H()
1201 static inline uint32_t REG_MDP5_LM_CURSOR_XY(uint32_t i0) { return 0x000000e8 + __offset_LM(i0); }  in REG_MDP5_LM_CURSOR_XY()
1204 static inline uint32_t MDP5_LM_CURSOR_XY_SRC_X(uint32_t val)  in MDP5_LM_CURSOR_XY_SRC_X()
1210 static inline uint32_t MDP5_LM_CURSOR_XY_SRC_Y(uint32_t val)  in MDP5_LM_CURSOR_XY_SRC_Y()
1215 static inline uint32_t REG_MDP5_LM_CURSOR_STRIDE(uint32_t i0) { return 0x000000dc + __offset_LM(i0)…  in REG_MDP5_LM_CURSOR_STRIDE()
1218 static inline uint32_t MDP5_LM_CURSOR_STRIDE_STRIDE(uint32_t val)  in MDP5_LM_CURSOR_STRIDE_STRIDE()
1223 static inline uint32_t REG_MDP5_LM_CURSOR_FORMAT(uint32_t i0) { return 0x000000ec + __offset_LM(i0)…  in REG_MDP5_LM_CURSOR_FORMAT()
1226 static inline uint32_t MDP5_LM_CURSOR_FORMAT_FORMAT(enum mdp5_cursor_format val)  in MDP5_LM_CURSOR_FORMAT_FORMAT()
1231 static inline uint32_t REG_MDP5_LM_CURSOR_BASE_ADDR(uint32_t i0) { return 0x000000f0 + __offset_LM(…  in REG_MDP5_LM_CURSOR_BASE_ADDR()
1233 static inline uint32_t REG_MDP5_LM_CURSOR_START_XY(uint32_t i0) { return 0x000000f4 + __offset_LM(i…  in REG_MDP5_LM_CURSOR_START_XY()
1236 static inline uint32_t MDP5_LM_CURSOR_START_XY_X_START(uint32_t val)  in MDP5_LM_CURSOR_START_XY_X_START()
1242 static inline uint32_t MDP5_LM_CURSOR_START_XY_Y_START(uint32_t val)  in MDP5_LM_CURSOR_START_XY_Y_START()
1247 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_CONFIG(uint32_t i0) { return 0x000000f8 + __offset_…  in REG_MDP5_LM_CURSOR_BLEND_CONFIG()
1251 static inline uint32_t MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(enum mdp5_cursor_alpha val)  in MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL()
1257 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_PARAM(uint32_t i0) { return 0x000000fc + __offset_L…  in REG_MDP5_LM_CURSOR_BLEND_PARAM()
1259 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0(uint32_t i0) { return 0x00000100 + __of…  in REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0()
1261 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1(uint32_t i0) { return 0x00000104 + __of…  in REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1()
1263 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0(uint32_t i0) { return 0x00000108 + __o…  in REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0()
1265 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1(uint32_t i0) { return 0x0000010c + __o…  in REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1()
1267 static inline uint32_t REG_MDP5_LM_GC_LUT_BASE(uint32_t i0) { return 0x00000110 + __offset_LM(i0); }  in REG_MDP5_LM_GC_LUT_BASE()
1269 static inline uint32_t __offset_DSPP(uint32_t idx)  in __offset_DSPP()
1279 static inline uint32_t REG_MDP5_DSPP(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); }  in REG_MDP5_DSPP()
1281 static inline uint32_t REG_MDP5_DSPP_OP_MODE(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); }  in REG_MDP5_DSPP_OP_MODE()
1285 static inline uint32_t MDP5_DSPP_OP_MODE_IGC_TBL_IDX(uint32_t val)  in MDP5_DSPP_OP_MODE_IGC_TBL_IDX()
1298 static inline uint32_t REG_MDP5_DSPP_PCC_BASE(uint32_t i0) { return 0x00000030 + __offset_DSPP(i0);…  in REG_MDP5_DSPP_PCC_BASE()
1300 static inline uint32_t REG_MDP5_DSPP_DITHER_DEPTH(uint32_t i0) { return 0x00000150 + __offset_DSPP(…  in REG_MDP5_DSPP_DITHER_DEPTH()
1302 static inline uint32_t REG_MDP5_DSPP_HIST_CTL_BASE(uint32_t i0) { return 0x00000210 + __offset_DSPP…  in REG_MDP5_DSPP_HIST_CTL_BASE()
1304 static inline uint32_t REG_MDP5_DSPP_HIST_LUT_BASE(uint32_t i0) { return 0x00000230 + __offset_DSPP…  in REG_MDP5_DSPP_HIST_LUT_BASE()
1306 static inline uint32_t REG_MDP5_DSPP_HIST_LUT_SWAP(uint32_t i0) { return 0x00000234 + __offset_DSPP…  in REG_MDP5_DSPP_HIST_LUT_SWAP()
1308 static inline uint32_t REG_MDP5_DSPP_PA_BASE(uint32_t i0) { return 0x00000238 + __offset_DSPP(i0); }  in REG_MDP5_DSPP_PA_BASE()
1310 static inline uint32_t REG_MDP5_DSPP_GAMUT_BASE(uint32_t i0) { return 0x000002dc + __offset_DSPP(i0…  in REG_MDP5_DSPP_GAMUT_BASE()
1312 static inline uint32_t REG_MDP5_DSPP_GC_BASE(uint32_t i0) { return 0x000002b0 + __offset_DSPP(i0); }  in REG_MDP5_DSPP_GC_BASE()
1314 static inline uint32_t __offset_PP(uint32_t idx)  in __offset_PP()
1324 static inline uint32_t REG_MDP5_PP(uint32_t i0) { return 0x00000000 + __offset_PP(i0); }  in REG_MDP5_PP()
1326 static inline uint32_t REG_MDP5_PP_TEAR_CHECK_EN(uint32_t i0) { return 0x00000000 + __offset_PP(i0)…  in REG_MDP5_PP_TEAR_CHECK_EN()
1328 static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_VSYNC(uint32_t i0) { return 0x00000004 + __offset_PP…  in REG_MDP5_PP_SYNC_CONFIG_VSYNC()
1331 static inline uint32_t MDP5_PP_SYNC_CONFIG_VSYNC_COUNT(uint32_t val)  in MDP5_PP_SYNC_CONFIG_VSYNC_COUNT()
1338 static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_HEIGHT(uint32_t i0) { return 0x00000008 + __offset_P…  in REG_MDP5_PP_SYNC_CONFIG_HEIGHT()
1340 static inline uint32_t REG_MDP5_PP_SYNC_WRCOUNT(uint32_t i0) { return 0x0000000c + __offset_PP(i0);…  in REG_MDP5_PP_SYNC_WRCOUNT()
1343 static inline uint32_t MDP5_PP_SYNC_WRCOUNT_LINE_COUNT(uint32_t val)  in MDP5_PP_SYNC_WRCOUNT_LINE_COUNT()
1349 static inline uint32_t MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT(uint32_t val)  in MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT()
1354 static inline uint32_t REG_MDP5_PP_VSYNC_INIT_VAL(uint32_t i0) { return 0x00000010 + __offset_PP(i0…  in REG_MDP5_PP_VSYNC_INIT_VAL()
1356 static inline uint32_t REG_MDP5_PP_INT_COUNT_VAL(uint32_t i0) { return 0x00000014 + __offset_PP(i0)…  in REG_MDP5_PP_INT_COUNT_VAL()
1359 static inline uint32_t MDP5_PP_INT_COUNT_VAL_LINE_COUNT(uint32_t val)  in MDP5_PP_INT_COUNT_VAL_LINE_COUNT()
1365 static inline uint32_t MDP5_PP_INT_COUNT_VAL_FRAME_COUNT(uint32_t val)  in MDP5_PP_INT_COUNT_VAL_FRAME_COUNT()
1370 static inline uint32_t REG_MDP5_PP_SYNC_THRESH(uint32_t i0) { return 0x00000018 + __offset_PP(i0); }  in REG_MDP5_PP_SYNC_THRESH()
1373 static inline uint32_t MDP5_PP_SYNC_THRESH_START(uint32_t val)  in MDP5_PP_SYNC_THRESH_START()
1379 static inline uint32_t MDP5_PP_SYNC_THRESH_CONTINUE(uint32_t val)  in MDP5_PP_SYNC_THRESH_CONTINUE()
1384 static inline uint32_t REG_MDP5_PP_START_POS(uint32_t i0) { return 0x0000001c + __offset_PP(i0); }  in REG_MDP5_PP_START_POS()
1386 static inline uint32_t REG_MDP5_PP_RD_PTR_IRQ(uint32_t i0) { return 0x00000020 + __offset_PP(i0); }  in REG_MDP5_PP_RD_PTR_IRQ()
1388 static inline uint32_t REG_MDP5_PP_WR_PTR_IRQ(uint32_t i0) { return 0x00000024 + __offset_PP(i0); }  in REG_MDP5_PP_WR_PTR_IRQ()
1390 static inline uint32_t REG_MDP5_PP_OUT_LINE_COUNT(uint32_t i0) { return 0x00000028 + __offset_PP(i0…  in REG_MDP5_PP_OUT_LINE_COUNT()
1392 static inline uint32_t REG_MDP5_PP_PP_LINE_COUNT(uint32_t i0) { return 0x0000002c + __offset_PP(i0)…  in REG_MDP5_PP_PP_LINE_COUNT()
1394 static inline uint32_t REG_MDP5_PP_AUTOREFRESH_CONFIG(uint32_t i0) { return 0x00000030 + __offset_P…  in REG_MDP5_PP_AUTOREFRESH_CONFIG()
1396 static inline uint32_t REG_MDP5_PP_FBC_MODE(uint32_t i0) { return 0x00000034 + __offset_PP(i0); }  in REG_MDP5_PP_FBC_MODE()
1398 static inline uint32_t REG_MDP5_PP_FBC_BUDGET_CTL(uint32_t i0) { return 0x00000038 + __offset_PP(i0…  in REG_MDP5_PP_FBC_BUDGET_CTL()
1400 static inline uint32_t REG_MDP5_PP_FBC_LOSSY_MODE(uint32_t i0) { return 0x0000003c + __offset_PP(i0…  in REG_MDP5_PP_FBC_LOSSY_MODE()
1402 static inline uint32_t __offset_WB(uint32_t idx)  in __offset_WB()
1415 static inline uint32_t REG_MDP5_WB(uint32_t i0) { return 0x00000000 + __offset_WB(i0); }  in REG_MDP5_WB()
1417 static inline uint32_t REG_MDP5_WB_DST_FORMAT(uint32_t i0) { return 0x00000000 + __offset_WB(i0); }  in REG_MDP5_WB_DST_FORMAT()
1420 static inline uint32_t MDP5_WB_DST_FORMAT_DSTC0_OUT(uint32_t val)  in MDP5_WB_DST_FORMAT_DSTC0_OUT()
1426 static inline uint32_t MDP5_WB_DST_FORMAT_DSTC1_OUT(uint32_t val)  in MDP5_WB_DST_FORMAT_DSTC1_OUT()
1432 static inline uint32_t MDP5_WB_DST_FORMAT_DSTC2_OUT(uint32_t val)  in MDP5_WB_DST_FORMAT_DSTC2_OUT()
1438 static inline uint32_t MDP5_WB_DST_FORMAT_DSTC3_OUT(uint32_t val)  in MDP5_WB_DST_FORMAT_DSTC3_OUT()
1445 static inline uint32_t MDP5_WB_DST_FORMAT_DST_BPP(uint32_t val)  in MDP5_WB_DST_FORMAT_DST_BPP()
1451 static inline uint32_t MDP5_WB_DST_FORMAT_PACK_COUNT(uint32_t val)  in MDP5_WB_DST_FORMAT_PACK_COUNT()
1460 static inline uint32_t MDP5_WB_DST_FORMAT_WRITE_PLANES(uint32_t val)  in MDP5_WB_DST_FORMAT_WRITE_PLANES()
1467 static inline uint32_t MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP(uint32_t val)  in MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP()
1473 static inline uint32_t MDP5_WB_DST_FORMAT_DST_CHROMA_SITE(uint32_t val)  in MDP5_WB_DST_FORMAT_DST_CHROMA_SITE()
1479 static inline uint32_t MDP5_WB_DST_FORMAT_FRAME_FORMAT(uint32_t val)  in MDP5_WB_DST_FORMAT_FRAME_FORMAT()
1484 static inline uint32_t REG_MDP5_WB_DST_OP_MODE(uint32_t i0) { return 0x00000004 + __offset_WB(i0); }  in REG_MDP5_WB_DST_OP_MODE()
1488 static inline uint32_t MDP5_WB_DST_OP_MODE_BWC_ENC_OP(uint32_t val)  in MDP5_WB_DST_OP_MODE_BWC_ENC_OP()
1494 static inline uint32_t MDP5_WB_DST_OP_MODE_BLOCK_SIZE(uint32_t val)  in MDP5_WB_DST_OP_MODE_BLOCK_SIZE()
1500 static inline uint32_t MDP5_WB_DST_OP_MODE_ROT_MODE(uint32_t val)  in MDP5_WB_DST_OP_MODE_ROT_MODE()
1508 static inline uint32_t MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT(uint32_t val)  in MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT()
1514 static inline uint32_t MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT(uint32_t val)  in MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT()
1521 static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT(uint32_t val)  in MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT()
1527 static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD(uint32_t val)  in MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD()
1533 static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD(uint32_t val)  in MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD()
1538 static inline uint32_t REG_MDP5_WB_DST_PACK_PATTERN(uint32_t i0) { return 0x00000008 + __offset_WB(…  in REG_MDP5_WB_DST_PACK_PATTERN()
1541 static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT0(uint32_t val)  in MDP5_WB_DST_PACK_PATTERN_ELEMENT0()
1547 static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT1(uint32_t val)  in MDP5_WB_DST_PACK_PATTERN_ELEMENT1()
1553 static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT2(uint32_t val)  in MDP5_WB_DST_PACK_PATTERN_ELEMENT2()
1559 static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT3(uint32_t val)  in MDP5_WB_DST_PACK_PATTERN_ELEMENT3()
1564 static inline uint32_t REG_MDP5_WB_DST0_ADDR(uint32_t i0) { return 0x0000000c + __offset_WB(i0); }  in REG_MDP5_WB_DST0_ADDR()
1566 static inline uint32_t REG_MDP5_WB_DST1_ADDR(uint32_t i0) { return 0x00000010 + __offset_WB(i0); }  in REG_MDP5_WB_DST1_ADDR()
1568 static inline uint32_t REG_MDP5_WB_DST2_ADDR(uint32_t i0) { return 0x00000014 + __offset_WB(i0); }  in REG_MDP5_WB_DST2_ADDR()
1570 static inline uint32_t REG_MDP5_WB_DST3_ADDR(uint32_t i0) { return 0x00000018 + __offset_WB(i0); }  in REG_MDP5_WB_DST3_ADDR()
1572 static inline uint32_t REG_MDP5_WB_DST_YSTRIDE0(uint32_t i0) { return 0x0000001c + __offset_WB(i0);…  in REG_MDP5_WB_DST_YSTRIDE0()
1575 static inline uint32_t MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE(uint32_t val)  in MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE()
1581 static inline uint32_t MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE(uint32_t val)  in MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE()
1586 static inline uint32_t REG_MDP5_WB_DST_YSTRIDE1(uint32_t i0) { return 0x00000020 + __offset_WB(i0);…  in REG_MDP5_WB_DST_YSTRIDE1()
1589 static inline uint32_t MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE(uint32_t val)  in MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE()
1595 static inline uint32_t MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE(uint32_t val)  in MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE()
1600 static inline uint32_t REG_MDP5_WB_DST_DITHER_BITDEPTH(uint32_t i0) { return 0x00000024 + __offset_…  in REG_MDP5_WB_DST_DITHER_BITDEPTH()
1602 static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW0(uint32_t i0) { return 0x00000030 + __offset_W…  in REG_MDP5_WB_DITHER_MATRIX_ROW0()
1604 static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW1(uint32_t i0) { return 0x00000034 + __offset_W…  in REG_MDP5_WB_DITHER_MATRIX_ROW1()
1606 static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW2(uint32_t i0) { return 0x00000038 + __offset_W…  in REG_MDP5_WB_DITHER_MATRIX_ROW2()
1608 static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW3(uint32_t i0) { return 0x0000003c + __offset_W…  in REG_MDP5_WB_DITHER_MATRIX_ROW3()
1610 static inline uint32_t REG_MDP5_WB_DST_WRITE_CONFIG(uint32_t i0) { return 0x00000048 + __offset_WB(…  in REG_MDP5_WB_DST_WRITE_CONFIG()
1612 static inline uint32_t REG_MDP5_WB_ROTATION_DNSCALER(uint32_t i0) { return 0x00000050 + __offset_WB…  in REG_MDP5_WB_ROTATION_DNSCALER()
1614 static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_0_3(uint32_t i0) { return 0x00000060 + __offset…  in REG_MDP5_WB_N16_INIT_PHASE_X_0_3()
1616 static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_1_2(uint32_t i0) { return 0x00000064 + __offset…  in REG_MDP5_WB_N16_INIT_PHASE_X_1_2()
1618 static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_0_3(uint32_t i0) { return 0x00000068 + __offset…  in REG_MDP5_WB_N16_INIT_PHASE_Y_0_3()
1620 static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_1_2(uint32_t i0) { return 0x0000006c + __offset…  in REG_MDP5_WB_N16_INIT_PHASE_Y_1_2()
1622 static inline uint32_t REG_MDP5_WB_OUT_SIZE(uint32_t i0) { return 0x00000074 + __offset_WB(i0); }  in REG_MDP5_WB_OUT_SIZE()
1625 static inline uint32_t MDP5_WB_OUT_SIZE_DST_W(uint32_t val)  in MDP5_WB_OUT_SIZE_DST_W()
1631 static inline uint32_t MDP5_WB_OUT_SIZE_DST_H(uint32_t val)  in MDP5_WB_OUT_SIZE_DST_H()
1636 static inline uint32_t REG_MDP5_WB_ALPHA_X_VALUE(uint32_t i0) { return 0x00000078 + __offset_WB(i0)…  in REG_MDP5_WB_ALPHA_X_VALUE()
1638 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_0(uint32_t i0) { return 0x00000260 + __offset_W…  in REG_MDP5_WB_CSC_MATRIX_COEFF_0()
1641 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11(uint32_t val)  in MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11()
1647 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12(uint32_t val)  in MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12()
1652 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_1(uint32_t i0) { return 0x00000264 + __offset_W…  in REG_MDP5_WB_CSC_MATRIX_COEFF_1()
1655 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13(uint32_t val)  in MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13()
1661 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21(uint32_t val)  in MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21()
1666 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_2(uint32_t i0) { return 0x00000268 + __offset_W…  in REG_MDP5_WB_CSC_MATRIX_COEFF_2()
1669 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22(uint32_t val)  in MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22()
1675 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23(uint32_t val)  in MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23()
1680 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_3(uint32_t i0) { return 0x0000026c + __offset_W…  in REG_MDP5_WB_CSC_MATRIX_COEFF_3()
1683 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31(uint32_t val)  in MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31()
1689 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32(uint32_t val)  in MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32()
1694 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_4(uint32_t i0) { return 0x00000270 + __offset_W…  in REG_MDP5_WB_CSC_MATRIX_COEFF_4()
1697 static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33(uint32_t val)  in MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33()
1702 static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP(uint32_t i0, uint32_t i1) { return 0x00000274 …  in REG_MDP5_WB_CSC_COMP_PRECLAMP()
1704 static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000…  in REG_MDP5_WB_CSC_COMP_PRECLAMP_REG()
1707 static inline uint32_t MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH(uint32_t val)  in MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH()
1713 static inline uint32_t MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW(uint32_t val)  in MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW()
1718 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP(uint32_t i0, uint32_t i1) { return 0x00000280…  in REG_MDP5_WB_CSC_COMP_POSTCLAMP()
1720 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG(uint32_t i0, uint32_t i1) { return 0x0000…  in REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG()
1723 static inline uint32_t MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH(uint32_t val)  in MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH()
1729 static inline uint32_t MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW(uint32_t val)  in MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW()
1734 static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS(uint32_t i0, uint32_t i1) { return 0x0000028c +…  in REG_MDP5_WB_CSC_COMP_PREBIAS()
1736 static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS_REG(uint32_t i0, uint32_t i1) { return 0x000002…  in REG_MDP5_WB_CSC_COMP_PREBIAS_REG()
1739 static inline uint32_t MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE(uint32_t val)  in MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE()
1744 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS(uint32_t i0, uint32_t i1) { return 0x00000298 …  in REG_MDP5_WB_CSC_COMP_POSTBIAS()
1746 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS_REG(uint32_t i0, uint32_t i1) { return 0x00000…  in REG_MDP5_WB_CSC_COMP_POSTBIAS_REG()
1749 static inline uint32_t MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE(uint32_t val)  in MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE()
1754 static inline uint32_t __offset_INTF(uint32_t idx)  in __offset_INTF()
1765 static inline uint32_t REG_MDP5_INTF(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); }  in REG_MDP5_INTF()
1767 static inline uint32_t REG_MDP5_INTF_TIMING_ENGINE_EN(uint32_t i0) { return 0x00000000 + __offset_I…  in REG_MDP5_INTF_TIMING_ENGINE_EN()
1769 static inline uint32_t REG_MDP5_INTF_CONFIG(uint32_t i0) { return 0x00000004 + __offset_INTF(i0); }  in REG_MDP5_INTF_CONFIG()
1771 static inline uint32_t REG_MDP5_INTF_HSYNC_CTL(uint32_t i0) { return 0x00000008 + __offset_INTF(i0)…  in REG_MDP5_INTF_HSYNC_CTL()
1774 static inline uint32_t MDP5_INTF_HSYNC_CTL_PULSEW(uint32_t val)  in MDP5_INTF_HSYNC_CTL_PULSEW()
1780 static inline uint32_t MDP5_INTF_HSYNC_CTL_PERIOD(uint32_t val)  in MDP5_INTF_HSYNC_CTL_PERIOD()
1785 static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F0(uint32_t i0) { return 0x0000000c + __offset_IN…  in REG_MDP5_INTF_VSYNC_PERIOD_F0()
1787 static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F1(uint32_t i0) { return 0x00000010 + __offset_IN…  in REG_MDP5_INTF_VSYNC_PERIOD_F1()
1789 static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F0(uint32_t i0) { return 0x00000014 + __offset_INTF(…  in REG_MDP5_INTF_VSYNC_LEN_F0()
1791 static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F1(uint32_t i0) { return 0x00000018 + __offset_INTF(…  in REG_MDP5_INTF_VSYNC_LEN_F1()
1793 static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F0(uint32_t i0) { return 0x0000001c + __offset_…  in REG_MDP5_INTF_DISPLAY_VSTART_F0()
1795 static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F1(uint32_t i0) { return 0x00000020 + __offset_…  in REG_MDP5_INTF_DISPLAY_VSTART_F1()
1797 static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F0(uint32_t i0) { return 0x00000024 + __offset_IN…  in REG_MDP5_INTF_DISPLAY_VEND_F0()
1799 static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F1(uint32_t i0) { return 0x00000028 + __offset_IN…  in REG_MDP5_INTF_DISPLAY_VEND_F1()
1801 static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F0(uint32_t i0) { return 0x0000002c + __offset_I…  in REG_MDP5_INTF_ACTIVE_VSTART_F0()
1804 static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F0_VAL(uint32_t val)  in MDP5_INTF_ACTIVE_VSTART_F0_VAL()
1810 static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F1(uint32_t i0) { return 0x00000030 + __offset_I…  in REG_MDP5_INTF_ACTIVE_VSTART_F1()
1813 static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F1_VAL(uint32_t val)  in MDP5_INTF_ACTIVE_VSTART_F1_VAL()
1818 static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F0(uint32_t i0) { return 0x00000034 + __offset_INT…  in REG_MDP5_INTF_ACTIVE_VEND_F0()
1820 static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F1(uint32_t i0) { return 0x00000038 + __offset_INT…  in REG_MDP5_INTF_ACTIVE_VEND_F1()
1822 static inline uint32_t REG_MDP5_INTF_DISPLAY_HCTL(uint32_t i0) { return 0x0000003c + __offset_INTF(…  in REG_MDP5_INTF_DISPLAY_HCTL()
1825 static inline uint32_t MDP5_INTF_DISPLAY_HCTL_START(uint32_t val)  in MDP5_INTF_DISPLAY_HCTL_START()
1831 static inline uint32_t MDP5_INTF_DISPLAY_HCTL_END(uint32_t val)  in MDP5_INTF_DISPLAY_HCTL_END()
1836 static inline uint32_t REG_MDP5_INTF_ACTIVE_HCTL(uint32_t i0) { return 0x00000040 + __offset_INTF(i…  in REG_MDP5_INTF_ACTIVE_HCTL()
1839 static inline uint32_t MDP5_INTF_ACTIVE_HCTL_START(uint32_t val)  in MDP5_INTF_ACTIVE_HCTL_START()
1845 static inline uint32_t MDP5_INTF_ACTIVE_HCTL_END(uint32_t val)  in MDP5_INTF_ACTIVE_HCTL_END()
1851 static inline uint32_t REG_MDP5_INTF_BORDER_COLOR(uint32_t i0) { return 0x00000044 + __offset_INTF(…  in REG_MDP5_INTF_BORDER_COLOR()
1853 static inline uint32_t REG_MDP5_INTF_UNDERFLOW_COLOR(uint32_t i0) { return 0x00000048 + __offset_IN…  in REG_MDP5_INTF_UNDERFLOW_COLOR()
1855 static inline uint32_t REG_MDP5_INTF_HSYNC_SKEW(uint32_t i0) { return 0x0000004c + __offset_INTF(i0…  in REG_MDP5_INTF_HSYNC_SKEW()
1857 static inline uint32_t REG_MDP5_INTF_POLARITY_CTL(uint32_t i0) { return 0x00000050 + __offset_INTF(…  in REG_MDP5_INTF_POLARITY_CTL()
1862 static inline uint32_t REG_MDP5_INTF_TEST_CTL(uint32_t i0) { return 0x00000054 + __offset_INTF(i0);…  in REG_MDP5_INTF_TEST_CTL()
1864 static inline uint32_t REG_MDP5_INTF_TP_COLOR0(uint32_t i0) { return 0x00000058 + __offset_INTF(i0)…  in REG_MDP5_INTF_TP_COLOR0()
1866 static inline uint32_t REG_MDP5_INTF_TP_COLOR1(uint32_t i0) { return 0x0000005c + __offset_INTF(i0)…  in REG_MDP5_INTF_TP_COLOR1()
1868 static inline uint32_t REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN(uint32_t i0) { return 0x00000084 + __o…  in REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN()
1870 static inline uint32_t REG_MDP5_INTF_PANEL_FORMAT(uint32_t i0) { return 0x00000090 + __offset_INTF(…  in REG_MDP5_INTF_PANEL_FORMAT()
1872 static inline uint32_t REG_MDP5_INTF_FRAME_LINE_COUNT_EN(uint32_t i0) { return 0x000000a8 + __offse…  in REG_MDP5_INTF_FRAME_LINE_COUNT_EN()
1874 static inline uint32_t REG_MDP5_INTF_FRAME_COUNT(uint32_t i0) { return 0x000000ac + __offset_INTF(i…  in REG_MDP5_INTF_FRAME_COUNT()
1876 static inline uint32_t REG_MDP5_INTF_LINE_COUNT(uint32_t i0) { return 0x000000b0 + __offset_INTF(i0…  in REG_MDP5_INTF_LINE_COUNT()
1878 static inline uint32_t REG_MDP5_INTF_DEFLICKER_CONFIG(uint32_t i0) { return 0x000000f0 + __offset_I…  in REG_MDP5_INTF_DEFLICKER_CONFIG()
1880 static inline uint32_t REG_MDP5_INTF_DEFLICKER_STRNG_COEFF(uint32_t i0) { return 0x000000f4 + __off…  in REG_MDP5_INTF_DEFLICKER_STRNG_COEFF()
1882 static inline uint32_t REG_MDP5_INTF_DEFLICKER_WEAK_COEFF(uint32_t i0) { return 0x000000f8 + __offs…  in REG_MDP5_INTF_DEFLICKER_WEAK_COEFF()
1884 static inline uint32_t REG_MDP5_INTF_TPG_ENABLE(uint32_t i0) { return 0x00000100 + __offset_INTF(i0…  in REG_MDP5_INTF_TPG_ENABLE()
1886 static inline uint32_t REG_MDP5_INTF_TPG_MAIN_CONTROL(uint32_t i0) { return 0x00000104 + __offset_I…  in REG_MDP5_INTF_TPG_MAIN_CONTROL()
1888 static inline uint32_t REG_MDP5_INTF_TPG_VIDEO_CONFIG(uint32_t i0) { return 0x00000108 + __offset_I…  in REG_MDP5_INTF_TPG_VIDEO_CONFIG()
1890 static inline uint32_t REG_MDP5_INTF_TPG_COMPONENT_LIMITS(uint32_t i0) { return 0x0000010c + __offs…  in REG_MDP5_INTF_TPG_COMPONENT_LIMITS()
1892 static inline uint32_t REG_MDP5_INTF_TPG_RECTANGLE(uint32_t i0) { return 0x00000110 + __offset_INTF…  in REG_MDP5_INTF_TPG_RECTANGLE()
1894 static inline uint32_t REG_MDP5_INTF_TPG_INITIAL_VALUE(uint32_t i0) { return 0x00000114 + __offset_…  in REG_MDP5_INTF_TPG_INITIAL_VALUE()
1896 static inline uint32_t REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME(uint32_t i0) { return 0x00000118 +…  in REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME()
1898 static inline uint32_t REG_MDP5_INTF_TPG_RGB_MAPPING(uint32_t i0) { return 0x0000011c + __offset_IN…  in REG_MDP5_INTF_TPG_RGB_MAPPING()
1900 static inline uint32_t __offset_AD(uint32_t idx)  in __offset_AD()
1908 static inline uint32_t REG_MDP5_AD(uint32_t i0) { return 0x00000000 + __offset_AD(i0); }  in REG_MDP5_AD()
1910 static inline uint32_t REG_MDP5_AD_BYPASS(uint32_t i0) { return 0x00000000 + __offset_AD(i0); }  in REG_MDP5_AD_BYPASS()
1912 static inline uint32_t REG_MDP5_AD_CTRL_0(uint32_t i0) { return 0x00000004 + __offset_AD(i0); }  in REG_MDP5_AD_CTRL_0()
1914 static inline uint32_t REG_MDP5_AD_CTRL_1(uint32_t i0) { return 0x00000008 + __offset_AD(i0); }  in REG_MDP5_AD_CTRL_1()
1916 static inline uint32_t REG_MDP5_AD_FRAME_SIZE(uint32_t i0) { return 0x0000000c + __offset_AD(i0); }  in REG_MDP5_AD_FRAME_SIZE()
1918 static inline uint32_t REG_MDP5_AD_CON_CTRL_0(uint32_t i0) { return 0x00000010 + __offset_AD(i0); }  in REG_MDP5_AD_CON_CTRL_0()
1920 static inline uint32_t REG_MDP5_AD_CON_CTRL_1(uint32_t i0) { return 0x00000014 + __offset_AD(i0); }  in REG_MDP5_AD_CON_CTRL_1()
1922 static inline uint32_t REG_MDP5_AD_STR_MAN(uint32_t i0) { return 0x00000018 + __offset_AD(i0); }  in REG_MDP5_AD_STR_MAN()
1924 static inline uint32_t REG_MDP5_AD_VAR(uint32_t i0) { return 0x0000001c + __offset_AD(i0); }  in REG_MDP5_AD_VAR()
1926 static inline uint32_t REG_MDP5_AD_DITH(uint32_t i0) { return 0x00000020 + __offset_AD(i0); }  in REG_MDP5_AD_DITH()
1928 static inline uint32_t REG_MDP5_AD_DITH_CTRL(uint32_t i0) { return 0x00000024 + __offset_AD(i0); }  in REG_MDP5_AD_DITH_CTRL()
1930 static inline uint32_t REG_MDP5_AD_AMP_LIM(uint32_t i0) { return 0x00000028 + __offset_AD(i0); }  in REG_MDP5_AD_AMP_LIM()
1932 static inline uint32_t REG_MDP5_AD_SLOPE(uint32_t i0) { return 0x0000002c + __offset_AD(i0); }  in REG_MDP5_AD_SLOPE()
1934 static inline uint32_t REG_MDP5_AD_BW_LVL(uint32_t i0) { return 0x00000030 + __offset_AD(i0); }  in REG_MDP5_AD_BW_LVL()
1936 static inline uint32_t REG_MDP5_AD_LOGO_POS(uint32_t i0) { return 0x00000034 + __offset_AD(i0); }  in REG_MDP5_AD_LOGO_POS()
1938 static inline uint32_t REG_MDP5_AD_LUT_FI(uint32_t i0) { return 0x00000038 + __offset_AD(i0); }  in REG_MDP5_AD_LUT_FI()
1940 static inline uint32_t REG_MDP5_AD_LUT_CC(uint32_t i0) { return 0x0000007c + __offset_AD(i0); }  in REG_MDP5_AD_LUT_CC()
1942 static inline uint32_t REG_MDP5_AD_STR_LIM(uint32_t i0) { return 0x000000c8 + __offset_AD(i0); }  in REG_MDP5_AD_STR_LIM()
1944 static inline uint32_t REG_MDP5_AD_CALIB_AB(uint32_t i0) { return 0x000000cc + __offset_AD(i0); }  in REG_MDP5_AD_CALIB_AB()
1946 static inline uint32_t REG_MDP5_AD_CALIB_CD(uint32_t i0) { return 0x000000d0 + __offset_AD(i0); }  in REG_MDP5_AD_CALIB_CD()
1948 static inline uint32_t REG_MDP5_AD_MODE_SEL(uint32_t i0) { return 0x000000d4 + __offset_AD(i0); }  in REG_MDP5_AD_MODE_SEL()
1950 static inline uint32_t REG_MDP5_AD_TFILT_CTRL(uint32_t i0) { return 0x000000d8 + __offset_AD(i0); }  in REG_MDP5_AD_TFILT_CTRL()
1952 static inline uint32_t REG_MDP5_AD_BL_MINMAX(uint32_t i0) { return 0x000000dc + __offset_AD(i0); }  in REG_MDP5_AD_BL_MINMAX()
1954 static inline uint32_t REG_MDP5_AD_BL(uint32_t i0) { return 0x000000e0 + __offset_AD(i0); }  in REG_MDP5_AD_BL()
1956 static inline uint32_t REG_MDP5_AD_BL_MAX(uint32_t i0) { return 0x000000e8 + __offset_AD(i0); }  in REG_MDP5_AD_BL_MAX()
1958 static inline uint32_t REG_MDP5_AD_AL(uint32_t i0) { return 0x000000ec + __offset_AD(i0); }  in REG_MDP5_AD_AL()
1960 static inline uint32_t REG_MDP5_AD_AL_MIN(uint32_t i0) { return 0x000000f0 + __offset_AD(i0); }  in REG_MDP5_AD_AL_MIN()
1962 static inline uint32_t REG_MDP5_AD_AL_FILT(uint32_t i0) { return 0x000000f4 + __offset_AD(i0); }  in REG_MDP5_AD_AL_FILT()
1964 static inline uint32_t REG_MDP5_AD_CFG_BUF(uint32_t i0) { return 0x000000f8 + __offset_AD(i0); }  in REG_MDP5_AD_CFG_BUF()
1966 static inline uint32_t REG_MDP5_AD_LUT_AL(uint32_t i0) { return 0x00000100 + __offset_AD(i0); }  in REG_MDP5_AD_LUT_AL()
1968 static inline uint32_t REG_MDP5_AD_TARG_STR(uint32_t i0) { return 0x00000144 + __offset_AD(i0); }  in REG_MDP5_AD_TARG_STR()
1970 static inline uint32_t REG_MDP5_AD_START_CALC(uint32_t i0) { return 0x00000148 + __offset_AD(i0); }  in REG_MDP5_AD_START_CALC()
1972 static inline uint32_t REG_MDP5_AD_STR_OUT(uint32_t i0) { return 0x0000014c + __offset_AD(i0); }  in REG_MDP5_AD_STR_OUT()
1974 static inline uint32_t REG_MDP5_AD_BL_OUT(uint32_t i0) { return 0x00000154 + __offset_AD(i0); }  in REG_MDP5_AD_BL_OUT()
1976 static inline uint32_t REG_MDP5_AD_CALC_DONE(uint32_t i0) { return 0x00000158 + __offset_AD(i0); }  in REG_MDP5_AD_CALC_DONE()