57 	INTF_DISABLED = 0,
67 	NO_INTF = 0,
75 	SSPP_NONE = 0,
91 	DUMMY = 0,
95 	MODE_NONE = 0,
104 	PACK_3D_FRAME_INT = 0,
111 	SCALE_FILTER_NEAREST = 0,
118 	BWC_LOSSLESS = 0,
124 	CURSOR_FMT_ARGB8888 = 0,
130 	CURSOR_ALPHA_CONST = 0,
135 	IGC_VIG = 0,
142 	DATA_FORMAT_RGB = 0,
147 	BLOCK_SIZE_64 = 0,
152 	ROTATE_0 = 0,
157 	DS_MTHD_NO_PIXEL_DROP = 0,
161 #define MDP5_IRQ_WB_0_DONE					0x00000001
162 #define MDP5_IRQ_WB_1_DONE					0x00000002
163 #define MDP5_IRQ_WB_2_DONE					0x00000010
164 #define MDP5_IRQ_PING_PONG_0_DONE				0x00000100
165 #define MDP5_IRQ_PING_PONG_1_DONE				0x00000200
166 #define MDP5_IRQ_PING_PONG_2_DONE				0x00000400
167 #define MDP5_IRQ_PING_PONG_3_DONE				0x00000800
168 #define MDP5_IRQ_PING_PONG_0_RD_PTR				0x00001000
169 #define MDP5_IRQ_PING_PONG_1_RD_PTR				0x00002000
170 #define MDP5_IRQ_PING_PONG_2_RD_PTR				0x00004000
171 #define MDP5_IRQ_PING_PONG_3_RD_PTR				0x00008000
172 #define MDP5_IRQ_PING_PONG_0_WR_PTR				0x00010000
173 #define MDP5_IRQ_PING_PONG_1_WR_PTR				0x00020000
174 #define MDP5_IRQ_PING_PONG_2_WR_PTR				0x00040000
175 #define MDP5_IRQ_PING_PONG_3_WR_PTR				0x00080000
176 #define MDP5_IRQ_PING_PONG_0_AUTO_REF				0x00100000
177 #define MDP5_IRQ_PING_PONG_1_AUTO_REF				0x00200000
178 #define MDP5_IRQ_PING_PONG_2_AUTO_REF				0x00400000
179 #define MDP5_IRQ_PING_PONG_3_AUTO_REF				0x00800000
180 #define MDP5_IRQ_INTF0_UNDER_RUN				0x01000000
181 #define MDP5_IRQ_INTF0_VSYNC					0x02000000
182 #define MDP5_IRQ_INTF1_UNDER_RUN				0x04000000
183 #define MDP5_IRQ_INTF1_VSYNC					0x08000000
184 #define MDP5_IRQ_INTF2_UNDER_RUN				0x10000000
185 #define MDP5_IRQ_INTF2_VSYNC					0x20000000
186 #define MDP5_IRQ_INTF3_UNDER_RUN				0x40000000
187 #define MDP5_IRQ_INTF3_VSYNC					0x80000000
188 #define REG_MDSS_HW_VERSION					0x00000000
189 #define MDSS_HW_VERSION_STEP__MASK				0x0000ffff
190 #define MDSS_HW_VERSION_STEP__SHIFT				0
195 #define MDSS_HW_VERSION_MINOR__MASK				0x0fff0000
201 #define MDSS_HW_VERSION_MAJOR__MASK				0xf0000000
208 #define REG_MDSS_HW_INTR_STATUS					0x00000010
209 #define MDSS_HW_INTR_STATUS_INTR_MDP				0x00000001
210 #define MDSS_HW_INTR_STATUS_INTR_DSI0				0x00000010
211 #define MDSS_HW_INTR_STATUS_INTR_DSI1				0x00000020
212 #define MDSS_HW_INTR_STATUS_INTR_HDMI				0x00000100
213 #define MDSS_HW_INTR_STATUS_INTR_EDP				0x00001000
215 #define REG_MDP5_HW_VERSION					0x00000000
216 #define MDP5_HW_VERSION_STEP__MASK				0x0000ffff
217 #define MDP5_HW_VERSION_STEP__SHIFT				0
222 #define MDP5_HW_VERSION_MINOR__MASK				0x0fff0000
228 #define MDP5_HW_VERSION_MAJOR__MASK				0xf0000000
235 #define REG_MDP5_DISP_INTF_SEL					0x00000004
236 #define MDP5_DISP_INTF_SEL_INTF0__MASK				0x000000ff
237 #define MDP5_DISP_INTF_SEL_INTF0__SHIFT				0
242 #define MDP5_DISP_INTF_SEL_INTF1__MASK				0x0000ff00
248 #define MDP5_DISP_INTF_SEL_INTF2__MASK				0x00ff0000
254 #define MDP5_DISP_INTF_SEL_INTF3__MASK				0xff000000
261 #define REG_MDP5_INTR_EN					0x00000010
263 #define REG_MDP5_INTR_STATUS					0x00000014
265 #define REG_MDP5_INTR_CLEAR					0x00000018
267 #define REG_MDP5_HIST_INTR_EN					0x0000001c
269 #define REG_MDP5_HIST_INTR_STATUS				0x00000020
271 #define REG_MDP5_HIST_INTR_CLEAR				0x00000024
273 #define REG_MDP5_SPARE_0					0x00000028
274 #define MDP5_SPARE_0_SPLIT_DPL_SINGLE_FLUSH_EN			0x00000001
276 static inline uint32_t REG_MDP5_SMP_ALLOC_W(uint32_t i0) { return 0x00000080 + 0x4*i0; }  in REG_MDP5_SMP_ALLOC_W()
278 static inline uint32_t REG_MDP5_SMP_ALLOC_W_REG(uint32_t i0) { return 0x00000080 + 0x4*i0; }  in REG_MDP5_SMP_ALLOC_W_REG()
279 #define MDP5_SMP_ALLOC_W_REG_CLIENT0__MASK			0x000000ff
280 #define MDP5_SMP_ALLOC_W_REG_CLIENT0__SHIFT			0
285 #define MDP5_SMP_ALLOC_W_REG_CLIENT1__MASK			0x0000ff00
291 #define MDP5_SMP_ALLOC_W_REG_CLIENT2__MASK			0x00ff0000
298 static inline uint32_t REG_MDP5_SMP_ALLOC_R(uint32_t i0) { return 0x00000130 + 0x4*i0; }  in REG_MDP5_SMP_ALLOC_R()
300 static inline uint32_t REG_MDP5_SMP_ALLOC_R_REG(uint32_t i0) { return 0x00000130 + 0x4*i0; }  in REG_MDP5_SMP_ALLOC_R_REG()
301 #define MDP5_SMP_ALLOC_R_REG_CLIENT0__MASK			0x000000ff
302 #define MDP5_SMP_ALLOC_R_REG_CLIENT0__SHIFT			0
307 #define MDP5_SMP_ALLOC_R_REG_CLIENT1__MASK			0x0000ff00
313 #define MDP5_SMP_ALLOC_R_REG_CLIENT2__MASK			0x00ff0000
323 		case IGC_VIG: return 0x00000200;  in __offset_IGC()
324 		case IGC_RGB: return 0x00000210;  in __offset_IGC()
325 		case IGC_DMA: return 0x00000220;  in __offset_IGC()
326 		case IGC_DSPP: return 0x00000300;  in __offset_IGC()
330 static inline uint32_t REG_MDP5_IGC(enum mdp5_igc_type i0) { return 0x00000000 + __offset_IGC(i0); }  in REG_MDP5_IGC()
332 …G_MDP5_IGC_LUT(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1…  in REG_MDP5_IGC_LUT()
334 …P5_IGC_LUT_REG(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1…  in REG_MDP5_IGC_LUT_REG()
335 #define MDP5_IGC_LUT_REG_VAL__MASK				0x00000fff
336 #define MDP5_IGC_LUT_REG_VAL__SHIFT				0
341 #define MDP5_IGC_LUT_REG_INDEX_UPDATE				0x02000000
342 #define MDP5_IGC_LUT_REG_DISABLE_PIPE_0				0x10000000
343 #define MDP5_IGC_LUT_REG_DISABLE_PIPE_1				0x20000000
344 #define MDP5_IGC_LUT_REG_DISABLE_PIPE_2				0x40000000
346 #define REG_MDP5_SPLIT_DPL_EN					0x000002f4
348 #define REG_MDP5_SPLIT_DPL_UPPER				0x000002f8
349 #define MDP5_SPLIT_DPL_UPPER_SMART_PANEL			0x00000002
350 #define MDP5_SPLIT_DPL_UPPER_SMART_PANEL_FREE_RUN		0x00000004
351 #define MDP5_SPLIT_DPL_UPPER_INTF1_SW_TRG_MUX			0x00000010
352 #define MDP5_SPLIT_DPL_UPPER_INTF2_SW_TRG_MUX			0x00000100
354 #define REG_MDP5_SPLIT_DPL_LOWER				0x000003f0
355 #define MDP5_SPLIT_DPL_LOWER_SMART_PANEL			0x00000002
356 #define MDP5_SPLIT_DPL_LOWER_SMART_PANEL_FREE_RUN		0x00000004
357 #define MDP5_SPLIT_DPL_LOWER_INTF1_TG_SYNC			0x00000010
358 #define MDP5_SPLIT_DPL_LOWER_INTF2_TG_SYNC			0x00000100
363 		case 0: return (mdp5_cfg->ctl.base[0]);  in __offset_CTL()
371 static inline uint32_t REG_MDP5_CTL(uint32_t i0) { return 0x00000000 + __offset_CTL(i0); }  in REG_MDP5_CTL()
376 		case 0: return 0x00000000;  in __offset_LAYER()
377 		case 1: return 0x00000004;  in __offset_LAYER()
378 		case 2: return 0x00000008;  in __offset_LAYER()
379 		case 3: return 0x0000000c;  in __offset_LAYER()
380 		case 4: return 0x00000010;  in __offset_LAYER()
381 		case 5: return 0x00000024;  in __offset_LAYER()
385 static inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_…  in REG_MDP5_CTL_LAYER()
387 static inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __off…  in REG_MDP5_CTL_LAYER_REG()
388 #define MDP5_CTL_LAYER_REG_VIG0__MASK				0x00000007
389 #define MDP5_CTL_LAYER_REG_VIG0__SHIFT				0
394 #define MDP5_CTL_LAYER_REG_VIG1__MASK				0x00000038
400 #define MDP5_CTL_LAYER_REG_VIG2__MASK				0x000001c0
406 #define MDP5_CTL_LAYER_REG_RGB0__MASK				0x00000e00
412 #define MDP5_CTL_LAYER_REG_RGB1__MASK				0x00007000
418 #define MDP5_CTL_LAYER_REG_RGB2__MASK				0x00038000
424 #define MDP5_CTL_LAYER_REG_DMA0__MASK				0x001c0000
430 #define MDP5_CTL_LAYER_REG_DMA1__MASK				0x00e00000
436 #define MDP5_CTL_LAYER_REG_BORDER_COLOR				0x01000000
437 #define MDP5_CTL_LAYER_REG_CURSOR_OUT				0x02000000
438 #define MDP5_CTL_LAYER_REG_VIG3__MASK				0x1c000000
444 #define MDP5_CTL_LAYER_REG_RGB3__MASK				0xe0000000
451 static inline uint32_t REG_MDP5_CTL_OP(uint32_t i0) { return 0x00000014 + __offset_CTL(i0); }  in REG_MDP5_CTL_OP()
452 #define MDP5_CTL_OP_MODE__MASK					0x0000000f
453 #define MDP5_CTL_OP_MODE__SHIFT					0
458 #define MDP5_CTL_OP_INTF_NUM__MASK				0x00000070
464 #define MDP5_CTL_OP_CMD_MODE					0x00020000
465 #define MDP5_CTL_OP_PACK_3D_ENABLE				0x00080000
466 #define MDP5_CTL_OP_PACK_3D__MASK				0x00300000
473 static inline uint32_t REG_MDP5_CTL_FLUSH(uint32_t i0) { return 0x00000018 + __offset_CTL(i0); }  in REG_MDP5_CTL_FLUSH()
474 #define MDP5_CTL_FLUSH_VIG0					0x00000001
475 #define MDP5_CTL_FLUSH_VIG1					0x00000002
476 #define MDP5_CTL_FLUSH_VIG2					0x00000004
477 #define MDP5_CTL_FLUSH_RGB0					0x00000008
478 #define MDP5_CTL_FLUSH_RGB1					0x00000010
479 #define MDP5_CTL_FLUSH_RGB2					0x00000020
480 #define MDP5_CTL_FLUSH_LM0					0x00000040
481 #define MDP5_CTL_FLUSH_LM1					0x00000080
482 #define MDP5_CTL_FLUSH_LM2					0x00000100
483 #define MDP5_CTL_FLUSH_LM3					0x00000200
484 #define MDP5_CTL_FLUSH_LM4					0x00000400
485 #define MDP5_CTL_FLUSH_DMA0					0x00000800
486 #define MDP5_CTL_FLUSH_DMA1					0x00001000
487 #define MDP5_CTL_FLUSH_DSPP0					0x00002000
488 #define MDP5_CTL_FLUSH_DSPP1					0x00004000
489 #define MDP5_CTL_FLUSH_DSPP2					0x00008000
490 #define MDP5_CTL_FLUSH_WB					0x00010000
491 #define MDP5_CTL_FLUSH_CTL					0x00020000
492 #define MDP5_CTL_FLUSH_VIG3					0x00040000
493 #define MDP5_CTL_FLUSH_RGB3					0x00080000
494 #define MDP5_CTL_FLUSH_LM5					0x00100000
495 #define MDP5_CTL_FLUSH_DSPP3					0x00200000
496 #define MDP5_CTL_FLUSH_CURSOR_0					0x00400000
497 #define MDP5_CTL_FLUSH_CURSOR_1					0x00800000
498 #define MDP5_CTL_FLUSH_CHROMADOWN_0				0x04000000
499 #define MDP5_CTL_FLUSH_TIMING_3					0x10000000
500 #define MDP5_CTL_FLUSH_TIMING_2					0x20000000
501 #define MDP5_CTL_FLUSH_TIMING_1					0x40000000
502 #define MDP5_CTL_FLUSH_TIMING_0					0x80000000
504 static inline uint32_t REG_MDP5_CTL_START(uint32_t i0) { return 0x0000001c + __offset_CTL(i0); }  in REG_MDP5_CTL_START()
506 static inline uint32_t REG_MDP5_CTL_PACK_3D(uint32_t i0) { return 0x00000020 + __offset_CTL(i0); }  in REG_MDP5_CTL_PACK_3D()
511 		case 0: return 0x00000040;  in __offset_LAYER_EXT()
512 		case 1: return 0x00000044;  in __offset_LAYER_EXT()
513 		case 2: return 0x00000048;  in __offset_LAYER_EXT()
514 		case 3: return 0x0000004c;  in __offset_LAYER_EXT()
515 		case 4: return 0x00000050;  in __offset_LAYER_EXT()
516 		case 5: return 0x00000054;  in __offset_LAYER_EXT()
520 static inline uint32_t REG_MDP5_CTL_LAYER_EXT(uint32_t i0, uint32_t i1) { return 0x00000000 + __off…  in REG_MDP5_CTL_LAYER_EXT()
522 static inline uint32_t REG_MDP5_CTL_LAYER_EXT_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + _…  in REG_MDP5_CTL_LAYER_EXT_REG()
523 #define MDP5_CTL_LAYER_EXT_REG_VIG0_BIT3			0x00000001
524 #define MDP5_CTL_LAYER_EXT_REG_VIG1_BIT3			0x00000004
525 #define MDP5_CTL_LAYER_EXT_REG_VIG2_BIT3			0x00000010
526 #define MDP5_CTL_LAYER_EXT_REG_VIG3_BIT3			0x00000040
527 #define MDP5_CTL_LAYER_EXT_REG_RGB0_BIT3			0x00000100
528 #define MDP5_CTL_LAYER_EXT_REG_RGB1_BIT3			0x00000400
529 #define MDP5_CTL_LAYER_EXT_REG_RGB2_BIT3			0x00001000
530 #define MDP5_CTL_LAYER_EXT_REG_RGB3_BIT3			0x00004000
531 #define MDP5_CTL_LAYER_EXT_REG_DMA0_BIT3			0x00010000
532 #define MDP5_CTL_LAYER_EXT_REG_DMA1_BIT3			0x00040000
533 #define MDP5_CTL_LAYER_EXT_REG_CURSOR0__MASK			0x00f00000
539 #define MDP5_CTL_LAYER_EXT_REG_CURSOR1__MASK			0x3c000000
550 		case SSPP_VIG0: return (mdp5_cfg->pipe_vig.base[0]);  in __offset_PIPE()
553 		case SSPP_RGB0: return (mdp5_cfg->pipe_rgb.base[0]);  in __offset_PIPE()
556 		case SSPP_DMA0: return (mdp5_cfg->pipe_dma.base[0]);  in __offset_PIPE()
560 		case SSPP_CURSOR0: return (mdp5_cfg->pipe_cursor.base[0]);  in __offset_PIPE()
565 static inline uint32_t REG_MDP5_PIPE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); }  in REG_MDP5_PIPE()
567 static inline uint32_t REG_MDP5_PIPE_OP_MODE(enum mdp5_pipe i0) { return 0x00000200 + __offset_PIPE…  in REG_MDP5_PIPE_OP_MODE()
568 #define MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__MASK		0x00080000
574 #define MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__MASK		0x00040000
580 #define MDP5_PIPE_OP_MODE_CSC_1_EN				0x00020000
582 static inline uint32_t REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0) { return 0x000002c4 + __offse…  in REG_MDP5_PIPE_HIST_CTL_BASE()
584 static inline uint32_t REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0) { return 0x000002f0 + __offse…  in REG_MDP5_PIPE_HIST_LUT_BASE()
586 static inline uint32_t REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0) { return 0x00000300 + __offse…  in REG_MDP5_PIPE_HIST_LUT_SWAP()
588 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(enum mdp5_pipe i0) { return 0x00000320 + …  in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0()
589 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__MASK		0x00001fff
590 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__SHIFT		0
595 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__MASK		0x1fff0000
602 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(enum mdp5_pipe i0) { return 0x00000324 + …  in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1()
603 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__MASK		0x00001fff
604 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__SHIFT		0
609 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__MASK		0x1fff0000
616 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(enum mdp5_pipe i0) { return 0x00000328 + …  in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2()
617 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__MASK		0x00001fff
618 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__SHIFT		0
623 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__MASK		0x1fff0000
630 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(enum mdp5_pipe i0) { return 0x0000032c + …  in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3()
631 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__MASK		0x00001fff
632 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__SHIFT		0
637 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__MASK		0x1fff0000
644 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(enum mdp5_pipe i0) { return 0x00000330 + …  in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4()
645 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__MASK		0x00001fff
646 #define MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__SHIFT		0
652 …E_CSC_1_PRE_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1…  in REG_MDP5_PIPE_CSC_1_PRE_CLAMP()
654 …C_1_PRE_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1…  in REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG()
655 #define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__MASK		0x000000ff
656 #define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__SHIFT		0
661 #define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__MASK			0x0000ff00
668 …_CSC_1_POST_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1…  in REG_MDP5_PIPE_CSC_1_POST_CLAMP()
670 …_1_POST_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1…  in REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG()
671 #define MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__MASK		0x000000ff
672 #define MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__SHIFT		0
677 #define MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__MASK		0x0000ff00
684 …PE_CSC_1_PRE_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1…  in REG_MDP5_PIPE_CSC_1_PRE_BIAS()
686 …SC_1_PRE_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1…  in REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG()
687 #define MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__MASK		0x000001ff
688 #define MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__SHIFT		0
694 …E_CSC_1_POST_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1…  in REG_MDP5_PIPE_CSC_1_POST_BIAS()
696 …C_1_POST_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1…  in REG_MDP5_PIPE_CSC_1_POST_BIAS_REG()
697 #define MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__MASK		0x000001ff
698 #define MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__SHIFT		0
704 static inline uint32_t REG_MDP5_PIPE_SRC_SIZE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIP…  in REG_MDP5_PIPE_SRC_SIZE()
705 #define MDP5_PIPE_SRC_SIZE_HEIGHT__MASK				0xffff0000
711 #define MDP5_PIPE_SRC_SIZE_WIDTH__MASK				0x0000ffff
712 #define MDP5_PIPE_SRC_SIZE_WIDTH__SHIFT				0
718 static inline uint32_t REG_MDP5_PIPE_SRC_IMG_SIZE(enum mdp5_pipe i0) { return 0x00000004 + __offset…  in REG_MDP5_PIPE_SRC_IMG_SIZE()
719 #define MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__MASK			0xffff0000
725 #define MDP5_PIPE_SRC_IMG_SIZE_WIDTH__MASK			0x0000ffff
726 #define MDP5_PIPE_SRC_IMG_SIZE_WIDTH__SHIFT			0
732 static inline uint32_t REG_MDP5_PIPE_SRC_XY(enum mdp5_pipe i0) { return 0x00000008 + __offset_PIPE(…  in REG_MDP5_PIPE_SRC_XY()
733 #define MDP5_PIPE_SRC_XY_Y__MASK				0xffff0000
739 #define MDP5_PIPE_SRC_XY_X__MASK				0x0000ffff
740 #define MDP5_PIPE_SRC_XY_X__SHIFT				0
746 static inline uint32_t REG_MDP5_PIPE_OUT_SIZE(enum mdp5_pipe i0) { return 0x0000000c + __offset_PIP…  in REG_MDP5_PIPE_OUT_SIZE()
747 #define MDP5_PIPE_OUT_SIZE_HEIGHT__MASK				0xffff0000
753 #define MDP5_PIPE_OUT_SIZE_WIDTH__MASK				0x0000ffff
754 #define MDP5_PIPE_OUT_SIZE_WIDTH__SHIFT				0
760 static inline uint32_t REG_MDP5_PIPE_OUT_XY(enum mdp5_pipe i0) { return 0x00000010 + __offset_PIPE(…  in REG_MDP5_PIPE_OUT_XY()
761 #define MDP5_PIPE_OUT_XY_Y__MASK				0xffff0000
767 #define MDP5_PIPE_OUT_XY_X__MASK				0x0000ffff
768 #define MDP5_PIPE_OUT_XY_X__SHIFT				0
774 static inline uint32_t REG_MDP5_PIPE_SRC0_ADDR(enum mdp5_pipe i0) { return 0x00000014 + __offset_PI…  in REG_MDP5_PIPE_SRC0_ADDR()
776 static inline uint32_t REG_MDP5_PIPE_SRC1_ADDR(enum mdp5_pipe i0) { return 0x00000018 + __offset_PI…  in REG_MDP5_PIPE_SRC1_ADDR()
778 static inline uint32_t REG_MDP5_PIPE_SRC2_ADDR(enum mdp5_pipe i0) { return 0x0000001c + __offset_PI…  in REG_MDP5_PIPE_SRC2_ADDR()
780 static inline uint32_t REG_MDP5_PIPE_SRC3_ADDR(enum mdp5_pipe i0) { return 0x00000020 + __offset_PI…  in REG_MDP5_PIPE_SRC3_ADDR()
782 static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_A(enum mdp5_pipe i0) { return 0x00000024 + __offset…  in REG_MDP5_PIPE_SRC_STRIDE_A()
783 #define MDP5_PIPE_SRC_STRIDE_A_P0__MASK				0x0000ffff
784 #define MDP5_PIPE_SRC_STRIDE_A_P0__SHIFT			0
789 #define MDP5_PIPE_SRC_STRIDE_A_P1__MASK				0xffff0000
796 static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_B(enum mdp5_pipe i0) { return 0x00000028 + __offset…  in REG_MDP5_PIPE_SRC_STRIDE_B()
797 #define MDP5_PIPE_SRC_STRIDE_B_P2__MASK				0x0000ffff
798 #define MDP5_PIPE_SRC_STRIDE_B_P2__SHIFT			0
803 #define MDP5_PIPE_SRC_STRIDE_B_P3__MASK				0xffff0000
810 static inline uint32_t REG_MDP5_PIPE_STILE_FRAME_SIZE(enum mdp5_pipe i0) { return 0x0000002c + __of…  in REG_MDP5_PIPE_STILE_FRAME_SIZE()
812 static inline uint32_t REG_MDP5_PIPE_SRC_FORMAT(enum mdp5_pipe i0) { return 0x00000030 + __offset_P…  in REG_MDP5_PIPE_SRC_FORMAT()
813 #define MDP5_PIPE_SRC_FORMAT_G_BPC__MASK			0x00000003
814 #define MDP5_PIPE_SRC_FORMAT_G_BPC__SHIFT			0
819 #define MDP5_PIPE_SRC_FORMAT_B_BPC__MASK			0x0000000c
825 #define MDP5_PIPE_SRC_FORMAT_R_BPC__MASK			0x00000030
831 #define MDP5_PIPE_SRC_FORMAT_A_BPC__MASK			0x000000c0
837 #define MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE			0x00000100
838 #define MDP5_PIPE_SRC_FORMAT_CPP__MASK				0x00000600
844 #define MDP5_PIPE_SRC_FORMAT_ROT90				0x00000800
845 #define MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK			0x00003000
851 #define MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT			0x00020000
852 #define MDP5_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB			0x00040000
853 #define MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__MASK			0x00180000
859 #define MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK			0x01800000
866 static inline uint32_t REG_MDP5_PIPE_SRC_UNPACK(enum mdp5_pipe i0) { return 0x00000034 + __offset_P…  in REG_MDP5_PIPE_SRC_UNPACK()
867 #define MDP5_PIPE_SRC_UNPACK_ELEM0__MASK			0x000000ff
868 #define MDP5_PIPE_SRC_UNPACK_ELEM0__SHIFT			0
873 #define MDP5_PIPE_SRC_UNPACK_ELEM1__MASK			0x0000ff00
879 #define MDP5_PIPE_SRC_UNPACK_ELEM2__MASK			0x00ff0000
885 #define MDP5_PIPE_SRC_UNPACK_ELEM3__MASK			0xff000000
892 static inline uint32_t REG_MDP5_PIPE_SRC_OP_MODE(enum mdp5_pipe i0) { return 0x00000038 + __offset_…  in REG_MDP5_PIPE_SRC_OP_MODE()
893 #define MDP5_PIPE_SRC_OP_MODE_BWC_EN				0x00000001
894 #define MDP5_PIPE_SRC_OP_MODE_BWC__MASK				0x00000006
900 #define MDP5_PIPE_SRC_OP_MODE_FLIP_LR				0x00002000
901 #define MDP5_PIPE_SRC_OP_MODE_FLIP_UD				0x00004000
902 #define MDP5_PIPE_SRC_OP_MODE_IGC_EN				0x00010000
903 #define MDP5_PIPE_SRC_OP_MODE_IGC_ROM_0				0x00020000
904 #define MDP5_PIPE_SRC_OP_MODE_IGC_ROM_1				0x00040000
905 #define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE			0x00400000
906 #define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE_ODD			0x00800000
907 #define MDP5_PIPE_SRC_OP_MODE_SW_PIX_EXT_OVERRIDE		0x80000000
909 static inline uint32_t REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0) { return 0x0000003c + __…  in REG_MDP5_PIPE_SRC_CONSTANT_COLOR()
911 static inline uint32_t REG_MDP5_PIPE_FETCH_CONFIG(enum mdp5_pipe i0) { return 0x00000048 + __offset…  in REG_MDP5_PIPE_FETCH_CONFIG()
913 static inline uint32_t REG_MDP5_PIPE_VC1_RANGE(enum mdp5_pipe i0) { return 0x0000004c + __offset_PI…  in REG_MDP5_PIPE_VC1_RANGE()
915 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(enum mdp5_pipe i0) { return 0x00000050 + __o…  in REG_MDP5_PIPE_REQPRIO_FIFO_WM_0()
917 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(enum mdp5_pipe i0) { return 0x00000054 + __o…  in REG_MDP5_PIPE_REQPRIO_FIFO_WM_1()
919 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(enum mdp5_pipe i0) { return 0x00000058 + __o…  in REG_MDP5_PIPE_REQPRIO_FIFO_WM_2()
921 static inline uint32_t REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(enum mdp5_pipe i0) { return 0x00000070 + __…  in REG_MDP5_PIPE_SRC_ADDR_SW_STATUS()
923 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC0_ADDR(enum mdp5_pipe i0) { return 0x000000a4 + __o…  in REG_MDP5_PIPE_CURRENT_SRC0_ADDR()
925 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC1_ADDR(enum mdp5_pipe i0) { return 0x000000a8 + __o…  in REG_MDP5_PIPE_CURRENT_SRC1_ADDR()
927 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC2_ADDR(enum mdp5_pipe i0) { return 0x000000ac + __o…  in REG_MDP5_PIPE_CURRENT_SRC2_ADDR()
929 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC3_ADDR(enum mdp5_pipe i0) { return 0x000000b0 + __o…  in REG_MDP5_PIPE_CURRENT_SRC3_ADDR()
931 static inline uint32_t REG_MDP5_PIPE_DECIMATION(enum mdp5_pipe i0) { return 0x000000b4 + __offset_P…  in REG_MDP5_PIPE_DECIMATION()
932 #define MDP5_PIPE_DECIMATION_VERT__MASK				0x000000ff
933 #define MDP5_PIPE_DECIMATION_VERT__SHIFT			0
938 #define MDP5_PIPE_DECIMATION_HORZ__MASK				0x0000ff00
948 		case COMP_0: return 0x00000100;  in __offset_SW_PIX_EXT()
949 		case COMP_1_2: return 0x00000110;  in __offset_SW_PIX_EXT()
950 		case COMP_3: return 0x00000120;  in __offset_SW_PIX_EXT()
954 …DP5_PIPE_SW_PIX_EXT(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __offset_…  in REG_MDP5_PIPE_SW_PIX_EXT()
956 …_PIPE_SW_PIX_EXT_LR(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __offset_…  in REG_MDP5_PIPE_SW_PIX_EXT_LR()
957 #define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__MASK			0x000000ff
958 #define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__SHIFT			0
963 #define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__MASK			0x0000ff00
969 #define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__MASK			0x00ff0000
975 #define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__MASK			0xff000000
982 …_PIPE_SW_PIX_EXT_TB(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000004 + __offset_…  in REG_MDP5_PIPE_SW_PIX_EXT_TB()
983 #define MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__MASK			0x000000ff
984 #define MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__SHIFT			0
989 #define MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__MASK			0x0000ff00
995 #define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__MASK		0x00ff0000
1001 #define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__MASK		0xff000000
1008 …_PIX_EXT_REQ_PIXELS(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000008 + __offset_…  in REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS()
1009 #define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__MASK	0x0000ffff
1010 #define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__SHIFT	0
1015 #define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__MASK	0xffff0000
1022 static inline uint32_t REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) { return 0x00000204 + __offset…  in REG_MDP5_PIPE_SCALE_CONFIG()
1023 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_EN			0x00000001
1024 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_EN			0x00000002
1025 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__MASK	0x00000300
1031 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__MASK	0x00000c00
1037 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__MASK	0x00003000
1043 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__MASK	0x0000c000
1049 #define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__MASK	0x00030000
1055 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__MASK	0x000c0000
1062 static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000210 + __…  in REG_MDP5_PIPE_SCALE_PHASE_STEP_X()
1064 static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x00000214 + __…  in REG_MDP5_PIPE_SCALE_PHASE_STEP_Y()
1066 static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000218 +…  in REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X()
1068 static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x0000021c +…  in REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y()
1070 static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_X(enum mdp5_pipe i0) { return 0x00000220 + __…  in REG_MDP5_PIPE_SCALE_INIT_PHASE_X()
1072 static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_Y(enum mdp5_pipe i0) { return 0x00000224 + __…  in REG_MDP5_PIPE_SCALE_INIT_PHASE_Y()
1077 		case 0: return (mdp5_cfg->lm.base[0]);  in __offset_LM()
1086 static inline uint32_t REG_MDP5_LM(uint32_t i0) { return 0x00000000 + __offset_LM(i0); }  in REG_MDP5_LM()
1088 static inline uint32_t REG_MDP5_LM_BLEND_COLOR_OUT(uint32_t i0) { return 0x00000000 + __offset_LM(i…  in REG_MDP5_LM_BLEND_COLOR_OUT()
1089 #define MDP5_LM_BLEND_COLOR_OUT_STAGE0_FG_ALPHA			0x00000002
1090 #define MDP5_LM_BLEND_COLOR_OUT_STAGE1_FG_ALPHA			0x00000004
1091 #define MDP5_LM_BLEND_COLOR_OUT_STAGE2_FG_ALPHA			0x00000008
1092 #define MDP5_LM_BLEND_COLOR_OUT_STAGE3_FG_ALPHA			0x00000010
1093 #define MDP5_LM_BLEND_COLOR_OUT_STAGE4_FG_ALPHA			0x00000020
1094 #define MDP5_LM_BLEND_COLOR_OUT_STAGE5_FG_ALPHA			0x00000040
1095 #define MDP5_LM_BLEND_COLOR_OUT_STAGE6_FG_ALPHA			0x00000080
1096 #define MDP5_LM_BLEND_COLOR_OUT_SPLIT_LEFT_RIGHT		0x80000000
1098 static inline uint32_t REG_MDP5_LM_OUT_SIZE(uint32_t i0) { return 0x00000004 + __offset_LM(i0); }  in REG_MDP5_LM_OUT_SIZE()
1099 #define MDP5_LM_OUT_SIZE_HEIGHT__MASK				0xffff0000
1105 #define MDP5_LM_OUT_SIZE_WIDTH__MASK				0x0000ffff
1106 #define MDP5_LM_OUT_SIZE_WIDTH__SHIFT				0
1112 static inline uint32_t REG_MDP5_LM_BORDER_COLOR_0(uint32_t i0) { return 0x00000008 + __offset_LM(i0…  in REG_MDP5_LM_BORDER_COLOR_0()
1114 static inline uint32_t REG_MDP5_LM_BORDER_COLOR_1(uint32_t i0) { return 0x00000010 + __offset_LM(i0…  in REG_MDP5_LM_BORDER_COLOR_1()
1119 		case 0: return 0x00000020;  in __offset_BLEND()
1120 		case 1: return 0x00000050;  in __offset_BLEND()
1121 		case 2: return 0x00000080;  in __offset_BLEND()
1122 		case 3: return 0x000000b0;  in __offset_BLEND()
1123 		case 4: return 0x00000230;  in __offset_BLEND()
1124 		case 5: return 0x00000260;  in __offset_BLEND()
1125 		case 6: return 0x00000290;  in __offset_BLEND()
1129 static inline uint32_t REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_L…  in REG_MDP5_LM_BLEND()
1131 static inline uint32_t REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) { return 0x00000000 + __…  in REG_MDP5_LM_BLEND_OP_MODE()
1132 #define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__MASK			0x00000003
1133 #define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__SHIFT			0
1138 #define MDP5_LM_BLEND_OP_MODE_FG_INV_ALPHA			0x00000004
1139 #define MDP5_LM_BLEND_OP_MODE_FG_MOD_ALPHA			0x00000008
1140 #define MDP5_LM_BLEND_OP_MODE_FG_INV_MOD_ALPHA			0x00000010
1141 #define MDP5_LM_BLEND_OP_MODE_FG_TRANSP_EN			0x00000020
1142 #define MDP5_LM_BLEND_OP_MODE_BG_ALPHA__MASK			0x00000300
1148 #define MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA			0x00000400
1149 #define MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA			0x00000800
1150 #define MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA			0x00001000
1151 #define MDP5_LM_BLEND_OP_MODE_BG_TRANSP_EN			0x00002000
1153 static inline uint32_t REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + _…  in REG_MDP5_LM_BLEND_FG_ALPHA()
1155 static inline uint32_t REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + _…  in REG_MDP5_LM_BLEND_BG_ALPHA()
1157 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x000000…  in REG_MDP5_LM_BLEND_FG_TRANSP_LOW0()
1159 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x000000…  in REG_MDP5_LM_BLEND_FG_TRANSP_LOW1()
1161 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000…  in REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0()
1163 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000…  in REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1()
1165 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x000000…  in REG_MDP5_LM_BLEND_BG_TRANSP_LOW0()
1167 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x000000…  in REG_MDP5_LM_BLEND_BG_TRANSP_LOW1()
1169 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000…  in REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0()
1171 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000…  in REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1()
1173 static inline uint32_t REG_MDP5_LM_CURSOR_IMG_SIZE(uint32_t i0) { return 0x000000e0 + __offset_LM(i…  in REG_MDP5_LM_CURSOR_IMG_SIZE()
1174 #define MDP5_LM_CURSOR_IMG_SIZE_SRC_W__MASK			0x0000ffff
1175 #define MDP5_LM_CURSOR_IMG_SIZE_SRC_W__SHIFT			0
1180 #define MDP5_LM_CURSOR_IMG_SIZE_SRC_H__MASK			0xffff0000
1187 static inline uint32_t REG_MDP5_LM_CURSOR_SIZE(uint32_t i0) { return 0x000000e4 + __offset_LM(i0); }  in REG_MDP5_LM_CURSOR_SIZE()
1188 #define MDP5_LM_CURSOR_SIZE_ROI_W__MASK				0x0000ffff
1189 #define MDP5_LM_CURSOR_SIZE_ROI_W__SHIFT			0
1194 #define MDP5_LM_CURSOR_SIZE_ROI_H__MASK				0xffff0000
1201 static inline uint32_t REG_MDP5_LM_CURSOR_XY(uint32_t i0) { return 0x000000e8 + __offset_LM(i0); }  in REG_MDP5_LM_CURSOR_XY()
1202 #define MDP5_LM_CURSOR_XY_SRC_X__MASK				0x0000ffff
1203 #define MDP5_LM_CURSOR_XY_SRC_X__SHIFT				0
1208 #define MDP5_LM_CURSOR_XY_SRC_Y__MASK				0xffff0000
1215 static inline uint32_t REG_MDP5_LM_CURSOR_STRIDE(uint32_t i0) { return 0x000000dc + __offset_LM(i0)…  in REG_MDP5_LM_CURSOR_STRIDE()
1216 #define MDP5_LM_CURSOR_STRIDE_STRIDE__MASK			0x0000ffff
1217 #define MDP5_LM_CURSOR_STRIDE_STRIDE__SHIFT			0
1223 static inline uint32_t REG_MDP5_LM_CURSOR_FORMAT(uint32_t i0) { return 0x000000ec + __offset_LM(i0)…  in REG_MDP5_LM_CURSOR_FORMAT()
1224 #define MDP5_LM_CURSOR_FORMAT_FORMAT__MASK			0x00000007
1225 #define MDP5_LM_CURSOR_FORMAT_FORMAT__SHIFT			0
1231 static inline uint32_t REG_MDP5_LM_CURSOR_BASE_ADDR(uint32_t i0) { return 0x000000f0 + __offset_LM(…  in REG_MDP5_LM_CURSOR_BASE_ADDR()
1233 static inline uint32_t REG_MDP5_LM_CURSOR_START_XY(uint32_t i0) { return 0x000000f4 + __offset_LM(i…  in REG_MDP5_LM_CURSOR_START_XY()
1234 #define MDP5_LM_CURSOR_START_XY_X_START__MASK			0x0000ffff
1235 #define MDP5_LM_CURSOR_START_XY_X_START__SHIFT			0
1240 #define MDP5_LM_CURSOR_START_XY_Y_START__MASK			0xffff0000
1247 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_CONFIG(uint32_t i0) { return 0x000000f8 + __offset_…  in REG_MDP5_LM_CURSOR_BLEND_CONFIG()
1248 #define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_EN			0x00000001
1249 #define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__MASK	0x00000006
1255 #define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_TRANSP_EN		0x00000008
1257 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_PARAM(uint32_t i0) { return 0x000000fc + __offset_L…  in REG_MDP5_LM_CURSOR_BLEND_PARAM()
1259 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0(uint32_t i0) { return 0x00000100 + __of…  in REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0()
1261 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1(uint32_t i0) { return 0x00000104 + __of…  in REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1()
1263 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0(uint32_t i0) { return 0x00000108 + __o…  in REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0()
1265 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1(uint32_t i0) { return 0x0000010c + __o…  in REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1()
1267 static inline uint32_t REG_MDP5_LM_GC_LUT_BASE(uint32_t i0) { return 0x00000110 + __offset_LM(i0); }  in REG_MDP5_LM_GC_LUT_BASE()
1272 		case 0: return (mdp5_cfg->dspp.base[0]);  in __offset_DSPP()
1279 static inline uint32_t REG_MDP5_DSPP(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); }  in REG_MDP5_DSPP()
1281 static inline uint32_t REG_MDP5_DSPP_OP_MODE(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); }  in REG_MDP5_DSPP_OP_MODE()
1282 #define MDP5_DSPP_OP_MODE_IGC_LUT_EN				0x00000001
1283 #define MDP5_DSPP_OP_MODE_IGC_TBL_IDX__MASK			0x0000000e
1289 #define MDP5_DSPP_OP_MODE_PCC_EN				0x00000010
1290 #define MDP5_DSPP_OP_MODE_DITHER_EN				0x00000100
1291 #define MDP5_DSPP_OP_MODE_HIST_EN				0x00010000
1292 #define MDP5_DSPP_OP_MODE_AUTO_CLEAR				0x00020000
1293 #define MDP5_DSPP_OP_MODE_HIST_LUT_EN				0x00080000
1294 #define MDP5_DSPP_OP_MODE_PA_EN					0x00100000
1295 #define MDP5_DSPP_OP_MODE_GAMUT_EN				0x00800000
1296 #define MDP5_DSPP_OP_MODE_GAMUT_ORDER				0x01000000
1298 static inline uint32_t REG_MDP5_DSPP_PCC_BASE(uint32_t i0) { return 0x00000030 + __offset_DSPP(i0);…  in REG_MDP5_DSPP_PCC_BASE()
1300 static inline uint32_t REG_MDP5_DSPP_DITHER_DEPTH(uint32_t i0) { return 0x00000150 + __offset_DSPP(…  in REG_MDP5_DSPP_DITHER_DEPTH()
1302 static inline uint32_t REG_MDP5_DSPP_HIST_CTL_BASE(uint32_t i0) { return 0x00000210 + __offset_DSPP…  in REG_MDP5_DSPP_HIST_CTL_BASE()
1304 static inline uint32_t REG_MDP5_DSPP_HIST_LUT_BASE(uint32_t i0) { return 0x00000230 + __offset_DSPP…  in REG_MDP5_DSPP_HIST_LUT_BASE()
1306 static inline uint32_t REG_MDP5_DSPP_HIST_LUT_SWAP(uint32_t i0) { return 0x00000234 + __offset_DSPP…  in REG_MDP5_DSPP_HIST_LUT_SWAP()
1308 static inline uint32_t REG_MDP5_DSPP_PA_BASE(uint32_t i0) { return 0x00000238 + __offset_DSPP(i0); }  in REG_MDP5_DSPP_PA_BASE()
1310 static inline uint32_t REG_MDP5_DSPP_GAMUT_BASE(uint32_t i0) { return 0x000002dc + __offset_DSPP(i0…  in REG_MDP5_DSPP_GAMUT_BASE()
1312 static inline uint32_t REG_MDP5_DSPP_GC_BASE(uint32_t i0) { return 0x000002b0 + __offset_DSPP(i0); }  in REG_MDP5_DSPP_GC_BASE()
1317 		case 0: return (mdp5_cfg->pp.base[0]);  in __offset_PP()
1324 static inline uint32_t REG_MDP5_PP(uint32_t i0) { return 0x00000000 + __offset_PP(i0); }  in REG_MDP5_PP()
1326 static inline uint32_t REG_MDP5_PP_TEAR_CHECK_EN(uint32_t i0) { return 0x00000000 + __offset_PP(i0)…  in REG_MDP5_PP_TEAR_CHECK_EN()
1328 static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_VSYNC(uint32_t i0) { return 0x00000004 + __offset_PP…  in REG_MDP5_PP_SYNC_CONFIG_VSYNC()
1329 #define MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__MASK			0x0007ffff
1330 #define MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__SHIFT			0
1335 #define MDP5_PP_SYNC_CONFIG_VSYNC_COUNTER_EN			0x00080000
1336 #define MDP5_PP_SYNC_CONFIG_VSYNC_IN_EN				0x00100000
1338 static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_HEIGHT(uint32_t i0) { return 0x00000008 + __offset_P…  in REG_MDP5_PP_SYNC_CONFIG_HEIGHT()
1340 static inline uint32_t REG_MDP5_PP_SYNC_WRCOUNT(uint32_t i0) { return 0x0000000c + __offset_PP(i0);…  in REG_MDP5_PP_SYNC_WRCOUNT()
1341 #define MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__MASK			0x0000ffff
1342 #define MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__SHIFT			0
1347 #define MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__MASK			0xffff0000
1354 static inline uint32_t REG_MDP5_PP_VSYNC_INIT_VAL(uint32_t i0) { return 0x00000010 + __offset_PP(i0…  in REG_MDP5_PP_VSYNC_INIT_VAL()
1356 static inline uint32_t REG_MDP5_PP_INT_COUNT_VAL(uint32_t i0) { return 0x00000014 + __offset_PP(i0)…  in REG_MDP5_PP_INT_COUNT_VAL()
1357 #define MDP5_PP_INT_COUNT_VAL_LINE_COUNT__MASK			0x0000ffff
1358 #define MDP5_PP_INT_COUNT_VAL_LINE_COUNT__SHIFT			0
1363 #define MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__MASK			0xffff0000
1370 static inline uint32_t REG_MDP5_PP_SYNC_THRESH(uint32_t i0) { return 0x00000018 + __offset_PP(i0); }  in REG_MDP5_PP_SYNC_THRESH()
1371 #define MDP5_PP_SYNC_THRESH_START__MASK				0x0000ffff
1372 #define MDP5_PP_SYNC_THRESH_START__SHIFT			0
1377 #define MDP5_PP_SYNC_THRESH_CONTINUE__MASK			0xffff0000
1384 static inline uint32_t REG_MDP5_PP_START_POS(uint32_t i0) { return 0x0000001c + __offset_PP(i0); }  in REG_MDP5_PP_START_POS()
1386 static inline uint32_t REG_MDP5_PP_RD_PTR_IRQ(uint32_t i0) { return 0x00000020 + __offset_PP(i0); }  in REG_MDP5_PP_RD_PTR_IRQ()
1388 static inline uint32_t REG_MDP5_PP_WR_PTR_IRQ(uint32_t i0) { return 0x00000024 + __offset_PP(i0); }  in REG_MDP5_PP_WR_PTR_IRQ()
1390 static inline uint32_t REG_MDP5_PP_OUT_LINE_COUNT(uint32_t i0) { return 0x00000028 + __offset_PP(i0…  in REG_MDP5_PP_OUT_LINE_COUNT()
1392 static inline uint32_t REG_MDP5_PP_PP_LINE_COUNT(uint32_t i0) { return 0x0000002c + __offset_PP(i0)…  in REG_MDP5_PP_PP_LINE_COUNT()
1394 static inline uint32_t REG_MDP5_PP_AUTOREFRESH_CONFIG(uint32_t i0) { return 0x00000030 + __offset_P…  in REG_MDP5_PP_AUTOREFRESH_CONFIG()
1396 static inline uint32_t REG_MDP5_PP_FBC_MODE(uint32_t i0) { return 0x00000034 + __offset_PP(i0); }  in REG_MDP5_PP_FBC_MODE()
1398 static inline uint32_t REG_MDP5_PP_FBC_BUDGET_CTL(uint32_t i0) { return 0x00000038 + __offset_PP(i0…  in REG_MDP5_PP_FBC_BUDGET_CTL()
1400 static inline uint32_t REG_MDP5_PP_FBC_LOSSY_MODE(uint32_t i0) { return 0x0000003c + __offset_PP(i0…  in REG_MDP5_PP_FBC_LOSSY_MODE()
1405 #if 0  /* TEMPORARY until patch that adds wb.base[] is merged */  in __offset_WB()
1406 		case 0: return (mdp5_cfg->wb.base[0]);  in __offset_WB()
1415 static inline uint32_t REG_MDP5_WB(uint32_t i0) { return 0x00000000 + __offset_WB(i0); }  in REG_MDP5_WB()
1417 static inline uint32_t REG_MDP5_WB_DST_FORMAT(uint32_t i0) { return 0x00000000 + __offset_WB(i0); }  in REG_MDP5_WB_DST_FORMAT()
1418 #define MDP5_WB_DST_FORMAT_DSTC0_OUT__MASK			0x00000003
1419 #define MDP5_WB_DST_FORMAT_DSTC0_OUT__SHIFT			0
1424 #define MDP5_WB_DST_FORMAT_DSTC1_OUT__MASK			0x0000000c
1430 #define MDP5_WB_DST_FORMAT_DSTC2_OUT__MASK			0x00000030
1436 #define MDP5_WB_DST_FORMAT_DSTC3_OUT__MASK			0x000000c0
1442 #define MDP5_WB_DST_FORMAT_DSTC3_EN				0x00000100
1443 #define MDP5_WB_DST_FORMAT_DST_BPP__MASK			0x00000600
1449 #define MDP5_WB_DST_FORMAT_PACK_COUNT__MASK			0x00003000
1455 #define MDP5_WB_DST_FORMAT_DST_ALPHA_X				0x00004000
1456 #define MDP5_WB_DST_FORMAT_PACK_TIGHT				0x00020000
1457 #define MDP5_WB_DST_FORMAT_PACK_ALIGN_MSB			0x00040000
1458 #define MDP5_WB_DST_FORMAT_WRITE_PLANES__MASK			0x00180000
1464 #define MDP5_WB_DST_FORMAT_DST_DITHER_EN			0x00400000
1465 #define MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__MASK		0x03800000
1471 #define MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__MASK		0x3c000000
1477 #define MDP5_WB_DST_FORMAT_FRAME_FORMAT__MASK			0xc0000000
1484 static inline uint32_t REG_MDP5_WB_DST_OP_MODE(uint32_t i0) { return 0x00000004 + __offset_WB(i0); }  in REG_MDP5_WB_DST_OP_MODE()
1485 #define MDP5_WB_DST_OP_MODE_BWC_ENC_EN				0x00000001
1486 #define MDP5_WB_DST_OP_MODE_BWC_ENC_OP__MASK			0x00000006
1492 #define MDP5_WB_DST_OP_MODE_BLOCK_SIZE__MASK			0x00000010
1498 #define MDP5_WB_DST_OP_MODE_ROT_MODE__MASK			0x00000020
1504 #define MDP5_WB_DST_OP_MODE_ROT_EN				0x00000040
1505 #define MDP5_WB_DST_OP_MODE_CSC_EN				0x00000100
1506 #define MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__MASK		0x00000200
1512 #define MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__MASK		0x00000400
1518 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_EN		0x00000800
1519 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__MASK	0x00001000
1525 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__MASK	0x00002000
1531 #define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__MASK	0x00004000
1538 static inline uint32_t REG_MDP5_WB_DST_PACK_PATTERN(uint32_t i0) { return 0x00000008 + __offset_WB(…  in REG_MDP5_WB_DST_PACK_PATTERN()
1539 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT0__MASK			0x00000003
1540 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT0__SHIFT		0
1545 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT1__MASK			0x00000300
1551 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT2__MASK			0x00030000
1557 #define MDP5_WB_DST_PACK_PATTERN_ELEMENT3__MASK			0x03000000
1564 static inline uint32_t REG_MDP5_WB_DST0_ADDR(uint32_t i0) { return 0x0000000c + __offset_WB(i0); }  in REG_MDP5_WB_DST0_ADDR()
1566 static inline uint32_t REG_MDP5_WB_DST1_ADDR(uint32_t i0) { return 0x00000010 + __offset_WB(i0); }  in REG_MDP5_WB_DST1_ADDR()
1568 static inline uint32_t REG_MDP5_WB_DST2_ADDR(uint32_t i0) { return 0x00000014 + __offset_WB(i0); }  in REG_MDP5_WB_DST2_ADDR()
1570 static inline uint32_t REG_MDP5_WB_DST3_ADDR(uint32_t i0) { return 0x00000018 + __offset_WB(i0); }  in REG_MDP5_WB_DST3_ADDR()
1572 static inline uint32_t REG_MDP5_WB_DST_YSTRIDE0(uint32_t i0) { return 0x0000001c + __offset_WB(i0);…  in REG_MDP5_WB_DST_YSTRIDE0()
1573 #define MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__MASK			0x0000ffff
1574 #define MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__SHIFT		0
1579 #define MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__MASK			0xffff0000
1586 static inline uint32_t REG_MDP5_WB_DST_YSTRIDE1(uint32_t i0) { return 0x00000020 + __offset_WB(i0);…  in REG_MDP5_WB_DST_YSTRIDE1()
1587 #define MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__MASK			0x0000ffff
1588 #define MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__SHIFT		0
1593 #define MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__MASK			0xffff0000
1600 static inline uint32_t REG_MDP5_WB_DST_DITHER_BITDEPTH(uint32_t i0) { return 0x00000024 + __offset_…  in REG_MDP5_WB_DST_DITHER_BITDEPTH()
1602 static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW0(uint32_t i0) { return 0x00000030 + __offset_W…  in REG_MDP5_WB_DITHER_MATRIX_ROW0()
1604 static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW1(uint32_t i0) { return 0x00000034 + __offset_W…  in REG_MDP5_WB_DITHER_MATRIX_ROW1()
1606 static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW2(uint32_t i0) { return 0x00000038 + __offset_W…  in REG_MDP5_WB_DITHER_MATRIX_ROW2()
1608 static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW3(uint32_t i0) { return 0x0000003c + __offset_W…  in REG_MDP5_WB_DITHER_MATRIX_ROW3()
1610 static inline uint32_t REG_MDP5_WB_DST_WRITE_CONFIG(uint32_t i0) { return 0x00000048 + __offset_WB(…  in REG_MDP5_WB_DST_WRITE_CONFIG()
1612 static inline uint32_t REG_MDP5_WB_ROTATION_DNSCALER(uint32_t i0) { return 0x00000050 + __offset_WB…  in REG_MDP5_WB_ROTATION_DNSCALER()
1614 static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_0_3(uint32_t i0) { return 0x00000060 + __offset…  in REG_MDP5_WB_N16_INIT_PHASE_X_0_3()
1616 static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_1_2(uint32_t i0) { return 0x00000064 + __offset…  in REG_MDP5_WB_N16_INIT_PHASE_X_1_2()
1618 static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_0_3(uint32_t i0) { return 0x00000068 + __offset…  in REG_MDP5_WB_N16_INIT_PHASE_Y_0_3()
1620 static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_1_2(uint32_t i0) { return 0x0000006c + __offset…  in REG_MDP5_WB_N16_INIT_PHASE_Y_1_2()
1622 static inline uint32_t REG_MDP5_WB_OUT_SIZE(uint32_t i0) { return 0x00000074 + __offset_WB(i0); }  in REG_MDP5_WB_OUT_SIZE()
1623 #define MDP5_WB_OUT_SIZE_DST_W__MASK				0x0000ffff
1624 #define MDP5_WB_OUT_SIZE_DST_W__SHIFT				0
1629 #define MDP5_WB_OUT_SIZE_DST_H__MASK				0xffff0000
1636 static inline uint32_t REG_MDP5_WB_ALPHA_X_VALUE(uint32_t i0) { return 0x00000078 + __offset_WB(i0)…  in REG_MDP5_WB_ALPHA_X_VALUE()
1638 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_0(uint32_t i0) { return 0x00000260 + __offset_W…  in REG_MDP5_WB_CSC_MATRIX_COEFF_0()
1639 #define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__MASK		0x00001fff
1640 #define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__SHIFT		0
1645 #define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__MASK		0x1fff0000
1652 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_1(uint32_t i0) { return 0x00000264 + __offset_W…  in REG_MDP5_WB_CSC_MATRIX_COEFF_1()
1653 #define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__MASK		0x00001fff
1654 #define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__SHIFT		0
1659 #define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__MASK		0x1fff0000
1666 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_2(uint32_t i0) { return 0x00000268 + __offset_W…  in REG_MDP5_WB_CSC_MATRIX_COEFF_2()
1667 #define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__MASK		0x00001fff
1668 #define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__SHIFT		0
1673 #define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__MASK		0x1fff0000
1680 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_3(uint32_t i0) { return 0x0000026c + __offset_W…  in REG_MDP5_WB_CSC_MATRIX_COEFF_3()
1681 #define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__MASK		0x00001fff
1682 #define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__SHIFT		0
1687 #define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__MASK		0x1fff0000
1694 static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_4(uint32_t i0) { return 0x00000270 + __offset_W…  in REG_MDP5_WB_CSC_MATRIX_COEFF_4()
1695 #define MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__MASK		0x00001fff
1696 #define MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__SHIFT		0
1702 …DP5_WB_CSC_COMP_PRECLAMP(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1;…  in REG_MDP5_WB_CSC_COMP_PRECLAMP()
1704 …WB_CSC_COMP_PRECLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1;…  in REG_MDP5_WB_CSC_COMP_PRECLAMP_REG()
1705 #define MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__MASK		0x000000ff
1706 #define MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__SHIFT		0
1711 #define MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__MASK			0x0000ff00
1718 …P5_WB_CSC_COMP_POSTCLAMP(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1;…  in REG_MDP5_WB_CSC_COMP_POSTCLAMP()
1720 …B_CSC_COMP_POSTCLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1;…  in REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG()
1721 #define MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__MASK		0x000000ff
1722 #define MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__SHIFT		0
1727 #define MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__MASK		0x0000ff00
1734 …MDP5_WB_CSC_COMP_PREBIAS(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1;…  in REG_MDP5_WB_CSC_COMP_PREBIAS()
1736 …_WB_CSC_COMP_PREBIAS_REG(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1;…  in REG_MDP5_WB_CSC_COMP_PREBIAS_REG()
1737 #define MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__MASK		0x000001ff
1738 #define MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__SHIFT		0
1744 …DP5_WB_CSC_COMP_POSTBIAS(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1;…  in REG_MDP5_WB_CSC_COMP_POSTBIAS()
1746 …WB_CSC_COMP_POSTBIAS_REG(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1;…  in REG_MDP5_WB_CSC_COMP_POSTBIAS_REG()
1747 #define MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__MASK		0x000001ff
1748 #define MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__SHIFT		0
1757 		case 0: return (mdp5_cfg->intf.base[0]);  in __offset_INTF()
1765 static inline uint32_t REG_MDP5_INTF(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); }  in REG_MDP5_INTF()
1767 static inline uint32_t REG_MDP5_INTF_TIMING_ENGINE_EN(uint32_t i0) { return 0x00000000 + __offset_I…  in REG_MDP5_INTF_TIMING_ENGINE_EN()
1769 static inline uint32_t REG_MDP5_INTF_CONFIG(uint32_t i0) { return 0x00000004 + __offset_INTF(i0); }  in REG_MDP5_INTF_CONFIG()
1771 static inline uint32_t REG_MDP5_INTF_HSYNC_CTL(uint32_t i0) { return 0x00000008 + __offset_INTF(i0)…  in REG_MDP5_INTF_HSYNC_CTL()
1772 #define MDP5_INTF_HSYNC_CTL_PULSEW__MASK			0x0000ffff
1773 #define MDP5_INTF_HSYNC_CTL_PULSEW__SHIFT			0
1778 #define MDP5_INTF_HSYNC_CTL_PERIOD__MASK			0xffff0000
1785 static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F0(uint32_t i0) { return 0x0000000c + __offset_IN…  in REG_MDP5_INTF_VSYNC_PERIOD_F0()
1787 static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F1(uint32_t i0) { return 0x00000010 + __offset_IN…  in REG_MDP5_INTF_VSYNC_PERIOD_F1()
1789 static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F0(uint32_t i0) { return 0x00000014 + __offset_INTF(…  in REG_MDP5_INTF_VSYNC_LEN_F0()
1791 static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F1(uint32_t i0) { return 0x00000018 + __offset_INTF(…  in REG_MDP5_INTF_VSYNC_LEN_F1()
1793 static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F0(uint32_t i0) { return 0x0000001c + __offset_…  in REG_MDP5_INTF_DISPLAY_VSTART_F0()
1795 static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F1(uint32_t i0) { return 0x00000020 + __offset_…  in REG_MDP5_INTF_DISPLAY_VSTART_F1()
1797 static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F0(uint32_t i0) { return 0x00000024 + __offset_IN…  in REG_MDP5_INTF_DISPLAY_VEND_F0()
1799 static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F1(uint32_t i0) { return 0x00000028 + __offset_IN…  in REG_MDP5_INTF_DISPLAY_VEND_F1()
1801 static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F0(uint32_t i0) { return 0x0000002c + __offset_I…  in REG_MDP5_INTF_ACTIVE_VSTART_F0()
1802 #define MDP5_INTF_ACTIVE_VSTART_F0_VAL__MASK			0x7fffffff
1803 #define MDP5_INTF_ACTIVE_VSTART_F0_VAL__SHIFT			0
1808 #define MDP5_INTF_ACTIVE_VSTART_F0_ACTIVE_V_ENABLE		0x80000000
1810 static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F1(uint32_t i0) { return 0x00000030 + __offset_I…  in REG_MDP5_INTF_ACTIVE_VSTART_F1()
1811 #define MDP5_INTF_ACTIVE_VSTART_F1_VAL__MASK			0x7fffffff
1812 #define MDP5_INTF_ACTIVE_VSTART_F1_VAL__SHIFT			0
1818 static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F0(uint32_t i0) { return 0x00000034 + __offset_INT…  in REG_MDP5_INTF_ACTIVE_VEND_F0()
1820 static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F1(uint32_t i0) { return 0x00000038 + __offset_INT…  in REG_MDP5_INTF_ACTIVE_VEND_F1()
1822 static inline uint32_t REG_MDP5_INTF_DISPLAY_HCTL(uint32_t i0) { return 0x0000003c + __offset_INTF(…  in REG_MDP5_INTF_DISPLAY_HCTL()
1823 #define MDP5_INTF_DISPLAY_HCTL_START__MASK			0x0000ffff
1824 #define MDP5_INTF_DISPLAY_HCTL_START__SHIFT			0
1829 #define MDP5_INTF_DISPLAY_HCTL_END__MASK			0xffff0000
1836 static inline uint32_t REG_MDP5_INTF_ACTIVE_HCTL(uint32_t i0) { return 0x00000040 + __offset_INTF(i…  in REG_MDP5_INTF_ACTIVE_HCTL()
1837 #define MDP5_INTF_ACTIVE_HCTL_START__MASK			0x00007fff
1838 #define MDP5_INTF_ACTIVE_HCTL_START__SHIFT			0
1843 #define MDP5_INTF_ACTIVE_HCTL_END__MASK				0x7fff0000
1849 #define MDP5_INTF_ACTIVE_HCTL_ACTIVE_H_ENABLE			0x80000000
1851 static inline uint32_t REG_MDP5_INTF_BORDER_COLOR(uint32_t i0) { return 0x00000044 + __offset_INTF(…  in REG_MDP5_INTF_BORDER_COLOR()
1853 static inline uint32_t REG_MDP5_INTF_UNDERFLOW_COLOR(uint32_t i0) { return 0x00000048 + __offset_IN…  in REG_MDP5_INTF_UNDERFLOW_COLOR()
1855 static inline uint32_t REG_MDP5_INTF_HSYNC_SKEW(uint32_t i0) { return 0x0000004c + __offset_INTF(i0…  in REG_MDP5_INTF_HSYNC_SKEW()
1857 static inline uint32_t REG_MDP5_INTF_POLARITY_CTL(uint32_t i0) { return 0x00000050 + __offset_INTF(…  in REG_MDP5_INTF_POLARITY_CTL()
1858 #define MDP5_INTF_POLARITY_CTL_HSYNC_LOW			0x00000001
1859 #define MDP5_INTF_POLARITY_CTL_VSYNC_LOW			0x00000002
1860 #define MDP5_INTF_POLARITY_CTL_DATA_EN_LOW			0x00000004
1862 static inline uint32_t REG_MDP5_INTF_TEST_CTL(uint32_t i0) { return 0x00000054 + __offset_INTF(i0);…  in REG_MDP5_INTF_TEST_CTL()
1864 static inline uint32_t REG_MDP5_INTF_TP_COLOR0(uint32_t i0) { return 0x00000058 + __offset_INTF(i0)…  in REG_MDP5_INTF_TP_COLOR0()
1866 static inline uint32_t REG_MDP5_INTF_TP_COLOR1(uint32_t i0) { return 0x0000005c + __offset_INTF(i0)…  in REG_MDP5_INTF_TP_COLOR1()
1868 static inline uint32_t REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN(uint32_t i0) { return 0x00000084 + __o…  in REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN()
1870 static inline uint32_t REG_MDP5_INTF_PANEL_FORMAT(uint32_t i0) { return 0x00000090 + __offset_INTF(…  in REG_MDP5_INTF_PANEL_FORMAT()
1872 static inline uint32_t REG_MDP5_INTF_FRAME_LINE_COUNT_EN(uint32_t i0) { return 0x000000a8 + __offse…  in REG_MDP5_INTF_FRAME_LINE_COUNT_EN()
1874 static inline uint32_t REG_MDP5_INTF_FRAME_COUNT(uint32_t i0) { return 0x000000ac + __offset_INTF(i…  in REG_MDP5_INTF_FRAME_COUNT()
1876 static inline uint32_t REG_MDP5_INTF_LINE_COUNT(uint32_t i0) { return 0x000000b0 + __offset_INTF(i0…  in REG_MDP5_INTF_LINE_COUNT()
1878 static inline uint32_t REG_MDP5_INTF_DEFLICKER_CONFIG(uint32_t i0) { return 0x000000f0 + __offset_I…  in REG_MDP5_INTF_DEFLICKER_CONFIG()
1880 static inline uint32_t REG_MDP5_INTF_DEFLICKER_STRNG_COEFF(uint32_t i0) { return 0x000000f4 + __off…  in REG_MDP5_INTF_DEFLICKER_STRNG_COEFF()
1882 static inline uint32_t REG_MDP5_INTF_DEFLICKER_WEAK_COEFF(uint32_t i0) { return 0x000000f8 + __offs…  in REG_MDP5_INTF_DEFLICKER_WEAK_COEFF()
1884 static inline uint32_t REG_MDP5_INTF_TPG_ENABLE(uint32_t i0) { return 0x00000100 + __offset_INTF(i0…  in REG_MDP5_INTF_TPG_ENABLE()
1886 static inline uint32_t REG_MDP5_INTF_TPG_MAIN_CONTROL(uint32_t i0) { return 0x00000104 + __offset_I…  in REG_MDP5_INTF_TPG_MAIN_CONTROL()
1888 static inline uint32_t REG_MDP5_INTF_TPG_VIDEO_CONFIG(uint32_t i0) { return 0x00000108 + __offset_I…  in REG_MDP5_INTF_TPG_VIDEO_CONFIG()
1890 static inline uint32_t REG_MDP5_INTF_TPG_COMPONENT_LIMITS(uint32_t i0) { return 0x0000010c + __offs…  in REG_MDP5_INTF_TPG_COMPONENT_LIMITS()
1892 static inline uint32_t REG_MDP5_INTF_TPG_RECTANGLE(uint32_t i0) { return 0x00000110 + __offset_INTF…  in REG_MDP5_INTF_TPG_RECTANGLE()
1894 static inline uint32_t REG_MDP5_INTF_TPG_INITIAL_VALUE(uint32_t i0) { return 0x00000114 + __offset_…  in REG_MDP5_INTF_TPG_INITIAL_VALUE()
1896 static inline uint32_t REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME(uint32_t i0) { return 0x00000118 +…  in REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME()
1898 static inline uint32_t REG_MDP5_INTF_TPG_RGB_MAPPING(uint32_t i0) { return 0x0000011c + __offset_IN…  in REG_MDP5_INTF_TPG_RGB_MAPPING()
1903 		case 0: return (mdp5_cfg->ad.base[0]);  in __offset_AD()
1908 static inline uint32_t REG_MDP5_AD(uint32_t i0) { return 0x00000000 + __offset_AD(i0); }  in REG_MDP5_AD()
1910 static inline uint32_t REG_MDP5_AD_BYPASS(uint32_t i0) { return 0x00000000 + __offset_AD(i0); }  in REG_MDP5_AD_BYPASS()
1912 static inline uint32_t REG_MDP5_AD_CTRL_0(uint32_t i0) { return 0x00000004 + __offset_AD(i0); }  in REG_MDP5_AD_CTRL_0()
1914 static inline uint32_t REG_MDP5_AD_CTRL_1(uint32_t i0) { return 0x00000008 + __offset_AD(i0); }  in REG_MDP5_AD_CTRL_1()
1916 static inline uint32_t REG_MDP5_AD_FRAME_SIZE(uint32_t i0) { return 0x0000000c + __offset_AD(i0); }  in REG_MDP5_AD_FRAME_SIZE()
1918 static inline uint32_t REG_MDP5_AD_CON_CTRL_0(uint32_t i0) { return 0x00000010 + __offset_AD(i0); }  in REG_MDP5_AD_CON_CTRL_0()
1920 static inline uint32_t REG_MDP5_AD_CON_CTRL_1(uint32_t i0) { return 0x00000014 + __offset_AD(i0); }  in REG_MDP5_AD_CON_CTRL_1()
1922 static inline uint32_t REG_MDP5_AD_STR_MAN(uint32_t i0) { return 0x00000018 + __offset_AD(i0); }  in REG_MDP5_AD_STR_MAN()
1924 static inline uint32_t REG_MDP5_AD_VAR(uint32_t i0) { return 0x0000001c + __offset_AD(i0); }  in REG_MDP5_AD_VAR()
1926 static inline uint32_t REG_MDP5_AD_DITH(uint32_t i0) { return 0x00000020 + __offset_AD(i0); }  in REG_MDP5_AD_DITH()
1928 static inline uint32_t REG_MDP5_AD_DITH_CTRL(uint32_t i0) { return 0x00000024 + __offset_AD(i0); }  in REG_MDP5_AD_DITH_CTRL()
1930 static inline uint32_t REG_MDP5_AD_AMP_LIM(uint32_t i0) { return 0x00000028 + __offset_AD(i0); }  in REG_MDP5_AD_AMP_LIM()
1932 static inline uint32_t REG_MDP5_AD_SLOPE(uint32_t i0) { return 0x0000002c + __offset_AD(i0); }  in REG_MDP5_AD_SLOPE()
1934 static inline uint32_t REG_MDP5_AD_BW_LVL(uint32_t i0) { return 0x00000030 + __offset_AD(i0); }  in REG_MDP5_AD_BW_LVL()
1936 static inline uint32_t REG_MDP5_AD_LOGO_POS(uint32_t i0) { return 0x00000034 + __offset_AD(i0); }  in REG_MDP5_AD_LOGO_POS()
1938 static inline uint32_t REG_MDP5_AD_LUT_FI(uint32_t i0) { return 0x00000038 + __offset_AD(i0); }  in REG_MDP5_AD_LUT_FI()
1940 static inline uint32_t REG_MDP5_AD_LUT_CC(uint32_t i0) { return 0x0000007c + __offset_AD(i0); }  in REG_MDP5_AD_LUT_CC()
1942 static inline uint32_t REG_MDP5_AD_STR_LIM(uint32_t i0) { return 0x000000c8 + __offset_AD(i0); }  in REG_MDP5_AD_STR_LIM()
1944 static inline uint32_t REG_MDP5_AD_CALIB_AB(uint32_t i0) { return 0x000000cc + __offset_AD(i0); }  in REG_MDP5_AD_CALIB_AB()
1946 static inline uint32_t REG_MDP5_AD_CALIB_CD(uint32_t i0) { return 0x000000d0 + __offset_AD(i0); }  in REG_MDP5_AD_CALIB_CD()
1948 static inline uint32_t REG_MDP5_AD_MODE_SEL(uint32_t i0) { return 0x000000d4 + __offset_AD(i0); }  in REG_MDP5_AD_MODE_SEL()
1950 static inline uint32_t REG_MDP5_AD_TFILT_CTRL(uint32_t i0) { return 0x000000d8 + __offset_AD(i0); }  in REG_MDP5_AD_TFILT_CTRL()
1952 static inline uint32_t REG_MDP5_AD_BL_MINMAX(uint32_t i0) { return 0x000000dc + __offset_AD(i0); }  in REG_MDP5_AD_BL_MINMAX()
1954 static inline uint32_t REG_MDP5_AD_BL(uint32_t i0) { return 0x000000e0 + __offset_AD(i0); }  in REG_MDP5_AD_BL()
1956 static inline uint32_t REG_MDP5_AD_BL_MAX(uint32_t i0) { return 0x000000e8 + __offset_AD(i0); }  in REG_MDP5_AD_BL_MAX()
1958 static inline uint32_t REG_MDP5_AD_AL(uint32_t i0) { return 0x000000ec + __offset_AD(i0); }  in REG_MDP5_AD_AL()
1960 static inline uint32_t REG_MDP5_AD_AL_MIN(uint32_t i0) { return 0x000000f0 + __offset_AD(i0); }  in REG_MDP5_AD_AL_MIN()
1962 static inline uint32_t REG_MDP5_AD_AL_FILT(uint32_t i0) { return 0x000000f4 + __offset_AD(i0); }  in REG_MDP5_AD_AL_FILT()
1964 static inline uint32_t REG_MDP5_AD_CFG_BUF(uint32_t i0) { return 0x000000f8 + __offset_AD(i0); }  in REG_MDP5_AD_CFG_BUF()
1966 static inline uint32_t REG_MDP5_AD_LUT_AL(uint32_t i0) { return 0x00000100 + __offset_AD(i0); }  in REG_MDP5_AD_LUT_AL()
1968 static inline uint32_t REG_MDP5_AD_TARG_STR(uint32_t i0) { return 0x00000144 + __offset_AD(i0); }  in REG_MDP5_AD_TARG_STR()
1970 static inline uint32_t REG_MDP5_AD_START_CALC(uint32_t i0) { return 0x00000148 + __offset_AD(i0); }  in REG_MDP5_AD_START_CALC()
1972 static inline uint32_t REG_MDP5_AD_STR_OUT(uint32_t i0) { return 0x0000014c + __offset_AD(i0); }  in REG_MDP5_AD_STR_OUT()
1974 static inline uint32_t REG_MDP5_AD_BL_OUT(uint32_t i0) { return 0x00000154 + __offset_AD(i0); }  in REG_MDP5_AD_BL_OUT()
1976 static inline uint32_t REG_MDP5_AD_CALC_DONE(uint32_t i0) { return 0x00000158 + __offset_AD(i0); }  in REG_MDP5_AD_CALC_DONE()