120 static inline uint32_t MDP4_VERSION_MINOR(uint32_t val)  in MDP4_VERSION_MINOR()  argument
122 	return ((val) << MDP4_VERSION_MINOR__SHIFT) & MDP4_VERSION_MINOR__MASK;  in MDP4_VERSION_MINOR()
126 static inline uint32_t MDP4_VERSION_MAJOR(uint32_t val)  in MDP4_VERSION_MAJOR()  argument
128 	return ((val) << MDP4_VERSION_MAJOR__SHIFT) & MDP4_VERSION_MAJOR__MASK;  in MDP4_VERSION_MAJOR()
148 static inline uint32_t MDP4_DISP_INTF_SEL_PRIM(enum mdp4_intf val)  in MDP4_DISP_INTF_SEL_PRIM()  argument
150 	return ((val) << MDP4_DISP_INTF_SEL_PRIM__SHIFT) & MDP4_DISP_INTF_SEL_PRIM__MASK;  in MDP4_DISP_INTF_SEL_PRIM()
154 static inline uint32_t MDP4_DISP_INTF_SEL_SEC(enum mdp4_intf val)  in MDP4_DISP_INTF_SEL_SEC()  argument
156 	return ((val) << MDP4_DISP_INTF_SEL_SEC__SHIFT) & MDP4_DISP_INTF_SEL_SEC__MASK;  in MDP4_DISP_INTF_SEL_SEC()
160 static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val)  in MDP4_DISP_INTF_SEL_EXT()  argument
162 	return ((val) << MDP4_DISP_INTF_SEL_EXT__SHIFT) & MDP4_DISP_INTF_SEL_EXT__MASK;  in MDP4_DISP_INTF_SEL_EXT()
190 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE0()  argument
192 	return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK;  in MDP4_LAYERMIXER2_IN_CFG_PIPE0()
197 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE1()  argument
199 	return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK;  in MDP4_LAYERMIXER2_IN_CFG_PIPE1()
204 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE2()  argument
206 	return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK;  in MDP4_LAYERMIXER2_IN_CFG_PIPE2()
211 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE3()  argument
213 	return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK;  in MDP4_LAYERMIXER2_IN_CFG_PIPE3()
218 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE4()  argument
220 	return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK;  in MDP4_LAYERMIXER2_IN_CFG_PIPE4()
225 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE5(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE5()  argument
227 	return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK;  in MDP4_LAYERMIXER2_IN_CFG_PIPE5()
232 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE6(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE6()  argument
234 	return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK;  in MDP4_LAYERMIXER2_IN_CFG_PIPE6()
239 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE7()  argument
241 	return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK;  in MDP4_LAYERMIXER2_IN_CFG_PIPE7()
250 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE0(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE0()  argument
252 	return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK;  in MDP4_LAYERMIXER_IN_CFG_PIPE0()
257 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE1(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE1()  argument
259 	return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK;  in MDP4_LAYERMIXER_IN_CFG_PIPE1()
264 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE2(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE2()  argument
266 	return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK;  in MDP4_LAYERMIXER_IN_CFG_PIPE2()
271 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE3(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE3()  argument
273 	return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK;  in MDP4_LAYERMIXER_IN_CFG_PIPE3()
278 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE4(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE4()  argument
280 	return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK;  in MDP4_LAYERMIXER_IN_CFG_PIPE4()
285 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE5(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE5()  argument
287 	return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK;  in MDP4_LAYERMIXER_IN_CFG_PIPE5()
292 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE6(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE6()  argument
294 	return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK;  in MDP4_LAYERMIXER_IN_CFG_PIPE6()
299 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE7(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE7()  argument
301 	return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK;  in MDP4_LAYERMIXER_IN_CFG_PIPE7()
333 static inline uint32_t MDP4_OVLP_SIZE_HEIGHT(uint32_t val)  in MDP4_OVLP_SIZE_HEIGHT()  argument
335 	return ((val) << MDP4_OVLP_SIZE_HEIGHT__SHIFT) & MDP4_OVLP_SIZE_HEIGHT__MASK;  in MDP4_OVLP_SIZE_HEIGHT()
339 static inline uint32_t MDP4_OVLP_SIZE_WIDTH(uint32_t val)  in MDP4_OVLP_SIZE_WIDTH()  argument
341 	return ((val) << MDP4_OVLP_SIZE_WIDTH__SHIFT) & MDP4_OVLP_SIZE_WIDTH__MASK;  in MDP4_OVLP_SIZE_WIDTH()
365 static inline uint32_t MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mdp_alpha_type val)  in MDP4_OVLP_STAGE_OP_FG_ALPHA()  argument
367 	return ((val) << MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK;  in MDP4_OVLP_STAGE_OP_FG_ALPHA()
373 static inline uint32_t MDP4_OVLP_STAGE_OP_BG_ALPHA(enum mdp_alpha_type val)  in MDP4_OVLP_STAGE_OP_BG_ALPHA()  argument
375 	return ((val) << MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK;  in MDP4_OVLP_STAGE_OP_BG_ALPHA()
468 static inline uint32_t MDP4_DMA_CONFIG_G_BPC(enum mdp_bpc val)  in MDP4_DMA_CONFIG_G_BPC()  argument
470 	return ((val) << MDP4_DMA_CONFIG_G_BPC__SHIFT) & MDP4_DMA_CONFIG_G_BPC__MASK;  in MDP4_DMA_CONFIG_G_BPC()
474 static inline uint32_t MDP4_DMA_CONFIG_B_BPC(enum mdp_bpc val)  in MDP4_DMA_CONFIG_B_BPC()  argument
476 	return ((val) << MDP4_DMA_CONFIG_B_BPC__SHIFT) & MDP4_DMA_CONFIG_B_BPC__MASK;  in MDP4_DMA_CONFIG_B_BPC()
480 static inline uint32_t MDP4_DMA_CONFIG_R_BPC(enum mdp_bpc val)  in MDP4_DMA_CONFIG_R_BPC()  argument
482 	return ((val) << MDP4_DMA_CONFIG_R_BPC__SHIFT) & MDP4_DMA_CONFIG_R_BPC__MASK;  in MDP4_DMA_CONFIG_R_BPC()
487 static inline uint32_t MDP4_DMA_CONFIG_PACK(uint32_t val)  in MDP4_DMA_CONFIG_PACK()  argument
489 	return ((val) << MDP4_DMA_CONFIG_PACK__SHIFT) & MDP4_DMA_CONFIG_PACK__MASK;  in MDP4_DMA_CONFIG_PACK()
497 static inline uint32_t MDP4_DMA_SRC_SIZE_HEIGHT(uint32_t val)  in MDP4_DMA_SRC_SIZE_HEIGHT()  argument
499 	return ((val) << MDP4_DMA_SRC_SIZE_HEIGHT__SHIFT) & MDP4_DMA_SRC_SIZE_HEIGHT__MASK;  in MDP4_DMA_SRC_SIZE_HEIGHT()
503 static inline uint32_t MDP4_DMA_SRC_SIZE_WIDTH(uint32_t val)  in MDP4_DMA_SRC_SIZE_WIDTH()  argument
505 	return ((val) << MDP4_DMA_SRC_SIZE_WIDTH__SHIFT) & MDP4_DMA_SRC_SIZE_WIDTH__MASK;  in MDP4_DMA_SRC_SIZE_WIDTH()
515 static inline uint32_t MDP4_DMA_DST_SIZE_HEIGHT(uint32_t val)  in MDP4_DMA_DST_SIZE_HEIGHT()  argument
517 	return ((val) << MDP4_DMA_DST_SIZE_HEIGHT__SHIFT) & MDP4_DMA_DST_SIZE_HEIGHT__MASK;  in MDP4_DMA_DST_SIZE_HEIGHT()
521 static inline uint32_t MDP4_DMA_DST_SIZE_WIDTH(uint32_t val)  in MDP4_DMA_DST_SIZE_WIDTH()  argument
523 	return ((val) << MDP4_DMA_DST_SIZE_WIDTH__SHIFT) & MDP4_DMA_DST_SIZE_WIDTH__MASK;  in MDP4_DMA_DST_SIZE_WIDTH()
529 static inline uint32_t MDP4_DMA_CURSOR_SIZE_WIDTH(uint32_t val)  in MDP4_DMA_CURSOR_SIZE_WIDTH()  argument
531 	return ((val) << MDP4_DMA_CURSOR_SIZE_WIDTH__SHIFT) & MDP4_DMA_CURSOR_SIZE_WIDTH__MASK;  in MDP4_DMA_CURSOR_SIZE_WIDTH()
535 static inline uint32_t MDP4_DMA_CURSOR_SIZE_HEIGHT(uint32_t val)  in MDP4_DMA_CURSOR_SIZE_HEIGHT()  argument
537 	return ((val) << MDP4_DMA_CURSOR_SIZE_HEIGHT__SHIFT) & MDP4_DMA_CURSOR_SIZE_HEIGHT__MASK;  in MDP4_DMA_CURSOR_SIZE_HEIGHT()
545 static inline uint32_t MDP4_DMA_CURSOR_POS_X(uint32_t val)  in MDP4_DMA_CURSOR_POS_X()  argument
547 	return ((val) << MDP4_DMA_CURSOR_POS_X__SHIFT) & MDP4_DMA_CURSOR_POS_X__MASK;  in MDP4_DMA_CURSOR_POS_X()
551 static inline uint32_t MDP4_DMA_CURSOR_POS_Y(uint32_t val)  in MDP4_DMA_CURSOR_POS_Y()  argument
553 	return ((val) << MDP4_DMA_CURSOR_POS_Y__SHIFT) & MDP4_DMA_CURSOR_POS_Y__MASK;  in MDP4_DMA_CURSOR_POS_Y()
560 static inline uint32_t MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(enum mdp4_cursor_format val)  in MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT()  argument
562 …return ((val) << MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__SHIFT) & MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT…  in MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT()
602 static inline uint32_t MDP4_PIPE_SRC_SIZE_HEIGHT(uint32_t val)  in MDP4_PIPE_SRC_SIZE_HEIGHT()  argument
604 	return ((val) << MDP4_PIPE_SRC_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_SRC_SIZE_HEIGHT__MASK;  in MDP4_PIPE_SRC_SIZE_HEIGHT()
608 static inline uint32_t MDP4_PIPE_SRC_SIZE_WIDTH(uint32_t val)  in MDP4_PIPE_SRC_SIZE_WIDTH()  argument
610 	return ((val) << MDP4_PIPE_SRC_SIZE_WIDTH__SHIFT) & MDP4_PIPE_SRC_SIZE_WIDTH__MASK;  in MDP4_PIPE_SRC_SIZE_WIDTH()
616 static inline uint32_t MDP4_PIPE_SRC_XY_Y(uint32_t val)  in MDP4_PIPE_SRC_XY_Y()  argument
618 	return ((val) << MDP4_PIPE_SRC_XY_Y__SHIFT) & MDP4_PIPE_SRC_XY_Y__MASK;  in MDP4_PIPE_SRC_XY_Y()
622 static inline uint32_t MDP4_PIPE_SRC_XY_X(uint32_t val)  in MDP4_PIPE_SRC_XY_X()  argument
624 	return ((val) << MDP4_PIPE_SRC_XY_X__SHIFT) & MDP4_PIPE_SRC_XY_X__MASK;  in MDP4_PIPE_SRC_XY_X()
630 static inline uint32_t MDP4_PIPE_DST_SIZE_HEIGHT(uint32_t val)  in MDP4_PIPE_DST_SIZE_HEIGHT()  argument
632 	return ((val) << MDP4_PIPE_DST_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_DST_SIZE_HEIGHT__MASK;  in MDP4_PIPE_DST_SIZE_HEIGHT()
636 static inline uint32_t MDP4_PIPE_DST_SIZE_WIDTH(uint32_t val)  in MDP4_PIPE_DST_SIZE_WIDTH()  argument
638 	return ((val) << MDP4_PIPE_DST_SIZE_WIDTH__SHIFT) & MDP4_PIPE_DST_SIZE_WIDTH__MASK;  in MDP4_PIPE_DST_SIZE_WIDTH()
644 static inline uint32_t MDP4_PIPE_DST_XY_Y(uint32_t val)  in MDP4_PIPE_DST_XY_Y()  argument
646 	return ((val) << MDP4_PIPE_DST_XY_Y__SHIFT) & MDP4_PIPE_DST_XY_Y__MASK;  in MDP4_PIPE_DST_XY_Y()
650 static inline uint32_t MDP4_PIPE_DST_XY_X(uint32_t val)  in MDP4_PIPE_DST_XY_X()  argument
652 	return ((val) << MDP4_PIPE_DST_XY_X__SHIFT) & MDP4_PIPE_DST_XY_X__MASK;  in MDP4_PIPE_DST_XY_X()
666 static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P0(uint32_t val)  in MDP4_PIPE_SRC_STRIDE_A_P0()  argument
668 	return ((val) << MDP4_PIPE_SRC_STRIDE_A_P0__SHIFT) & MDP4_PIPE_SRC_STRIDE_A_P0__MASK;  in MDP4_PIPE_SRC_STRIDE_A_P0()
672 static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P1(uint32_t val)  in MDP4_PIPE_SRC_STRIDE_A_P1()  argument
674 	return ((val) << MDP4_PIPE_SRC_STRIDE_A_P1__SHIFT) & MDP4_PIPE_SRC_STRIDE_A_P1__MASK;  in MDP4_PIPE_SRC_STRIDE_A_P1()
680 static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P2(uint32_t val)  in MDP4_PIPE_SRC_STRIDE_B_P2()  argument
682 	return ((val) << MDP4_PIPE_SRC_STRIDE_B_P2__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P2__MASK;  in MDP4_PIPE_SRC_STRIDE_B_P2()
686 static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P3(uint32_t val)  in MDP4_PIPE_SRC_STRIDE_B_P3()  argument
688 	return ((val) << MDP4_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P3__MASK;  in MDP4_PIPE_SRC_STRIDE_B_P3()
694 static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT(uint32_t val)  in MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT()  argument
696 …return ((val) << MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__…  in MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT()
700 static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH(uint32_t val)  in MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH()  argument
702 …return ((val) << MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__SHIFT) & MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__MA…  in MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH()
708 static inline uint32_t MDP4_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val)  in MDP4_PIPE_SRC_FORMAT_G_BPC()  argument
710 	return ((val) << MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_G_BPC__MASK;  in MDP4_PIPE_SRC_FORMAT_G_BPC()
714 static inline uint32_t MDP4_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val)  in MDP4_PIPE_SRC_FORMAT_B_BPC()  argument
716 	return ((val) << MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_B_BPC__MASK;  in MDP4_PIPE_SRC_FORMAT_B_BPC()
720 static inline uint32_t MDP4_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val)  in MDP4_PIPE_SRC_FORMAT_R_BPC()  argument
722 	return ((val) << MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_R_BPC__MASK;  in MDP4_PIPE_SRC_FORMAT_R_BPC()
726 static inline uint32_t MDP4_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val)  in MDP4_PIPE_SRC_FORMAT_A_BPC()  argument
728 	return ((val) << MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_A_BPC__MASK;  in MDP4_PIPE_SRC_FORMAT_A_BPC()
733 static inline uint32_t MDP4_PIPE_SRC_FORMAT_CPP(uint32_t val)  in MDP4_PIPE_SRC_FORMAT_CPP()  argument
735 	return ((val) << MDP4_PIPE_SRC_FORMAT_CPP__SHIFT) & MDP4_PIPE_SRC_FORMAT_CPP__MASK;  in MDP4_PIPE_SRC_FORMAT_CPP()
740 static inline uint32_t MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)  in MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT()  argument
742 …return ((val) << MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT) & MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__MA…  in MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT()
748 static inline uint32_t MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(uint32_t val)  in MDP4_PIPE_SRC_FORMAT_FETCH_PLANES()  argument
750 …return ((val) << MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__SHIFT) & MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__MA…  in MDP4_PIPE_SRC_FORMAT_FETCH_PLANES()
755 static inline uint32_t MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val)  in MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP()  argument
757 	return ((val) << MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT) & MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK;  in MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP()
761 static inline uint32_t MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT(enum mdp4_frame_format val)  in MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT()  argument
763 …return ((val) << MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__SHIFT) & MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__MA…  in MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT()
769 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM0(uint32_t val)  in MDP4_PIPE_SRC_UNPACK_ELEM0()  argument
771 	return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM0__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM0__MASK;  in MDP4_PIPE_SRC_UNPACK_ELEM0()
775 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM1(uint32_t val)  in MDP4_PIPE_SRC_UNPACK_ELEM1()  argument
777 	return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM1__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM1__MASK;  in MDP4_PIPE_SRC_UNPACK_ELEM1()
781 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM2(uint32_t val)  in MDP4_PIPE_SRC_UNPACK_ELEM2()  argument
783 	return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM2__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM2__MASK;  in MDP4_PIPE_SRC_UNPACK_ELEM2()
787 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM3(uint32_t val)  in MDP4_PIPE_SRC_UNPACK_ELEM3()  argument
789 	return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM3__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM3__MASK;  in MDP4_PIPE_SRC_UNPACK_ELEM3()
797 static inline uint32_t MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL(enum mdp4_scale_unit val)  in MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL()  argument
799 …return ((val) << MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__SHIFT) & MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__MA…  in MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL()
803 static inline uint32_t MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL(enum mdp4_scale_unit val)  in MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL()  argument
805 …return ((val) << MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__SHIFT) & MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__MA…  in MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL()
855 static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PULSEW(uint32_t val)  in MDP4_LCDC_HSYNC_CTRL_PULSEW()  argument
857 	return ((val) << MDP4_LCDC_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_LCDC_HSYNC_CTRL_PULSEW__MASK;  in MDP4_LCDC_HSYNC_CTRL_PULSEW()
861 static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PERIOD(uint32_t val)  in MDP4_LCDC_HSYNC_CTRL_PERIOD()  argument
863 	return ((val) << MDP4_LCDC_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_LCDC_HSYNC_CTRL_PERIOD__MASK;  in MDP4_LCDC_HSYNC_CTRL_PERIOD()
873 static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_START(uint32_t val)  in MDP4_LCDC_DISPLAY_HCTRL_START()  argument
875 	return ((val) << MDP4_LCDC_DISPLAY_HCTRL_START__SHIFT) & MDP4_LCDC_DISPLAY_HCTRL_START__MASK;  in MDP4_LCDC_DISPLAY_HCTRL_START()
879 static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_END(uint32_t val)  in MDP4_LCDC_DISPLAY_HCTRL_END()  argument
881 	return ((val) << MDP4_LCDC_DISPLAY_HCTRL_END__SHIFT) & MDP4_LCDC_DISPLAY_HCTRL_END__MASK;  in MDP4_LCDC_DISPLAY_HCTRL_END()
891 static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_START(uint32_t val)  in MDP4_LCDC_ACTIVE_HCTL_START()  argument
893 	return ((val) << MDP4_LCDC_ACTIVE_HCTL_START__SHIFT) & MDP4_LCDC_ACTIVE_HCTL_START__MASK;  in MDP4_LCDC_ACTIVE_HCTL_START()
897 static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_END(uint32_t val)  in MDP4_LCDC_ACTIVE_HCTL_END()  argument
899 	return ((val) << MDP4_LCDC_ACTIVE_HCTL_END__SHIFT) & MDP4_LCDC_ACTIVE_HCTL_END__MASK;  in MDP4_LCDC_ACTIVE_HCTL_END()
912 static inline uint32_t MDP4_LCDC_UNDERFLOW_CLR_COLOR(uint32_t val)  in MDP4_LCDC_UNDERFLOW_CLR_COLOR()  argument
914 	return ((val) << MDP4_LCDC_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_LCDC_UNDERFLOW_CLR_COLOR__MASK;  in MDP4_LCDC_UNDERFLOW_CLR_COLOR()
950 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(uint32_t val)  in MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0()  argument
952 …return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__…  in MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0()
956 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(uint32_t val)  in MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1()  argument
958 …return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__…  in MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1()
962 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(uint32_t val)  in MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2()  argument
964 …return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__…  in MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2()
968 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(uint32_t val)  in MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3()  argument
970 …return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__…  in MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3()
976 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(uint32_t val)  in MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4()  argument
978 …return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__…  in MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4()
982 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(uint32_t val)  in MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5()  argument
984 …return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__…  in MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5()
988 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(uint32_t val)  in MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6()  argument
990 …return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__…  in MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6()
1029 static inline uint32_t MDP4_DTV_HSYNC_CTRL_PULSEW(uint32_t val)  in MDP4_DTV_HSYNC_CTRL_PULSEW()  argument
1031 	return ((val) << MDP4_DTV_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_DTV_HSYNC_CTRL_PULSEW__MASK;  in MDP4_DTV_HSYNC_CTRL_PULSEW()
1035 static inline uint32_t MDP4_DTV_HSYNC_CTRL_PERIOD(uint32_t val)  in MDP4_DTV_HSYNC_CTRL_PERIOD()  argument
1037 	return ((val) << MDP4_DTV_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_DTV_HSYNC_CTRL_PERIOD__MASK;  in MDP4_DTV_HSYNC_CTRL_PERIOD()
1047 static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_START(uint32_t val)  in MDP4_DTV_DISPLAY_HCTRL_START()  argument
1049 	return ((val) << MDP4_DTV_DISPLAY_HCTRL_START__SHIFT) & MDP4_DTV_DISPLAY_HCTRL_START__MASK;  in MDP4_DTV_DISPLAY_HCTRL_START()
1053 static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_END(uint32_t val)  in MDP4_DTV_DISPLAY_HCTRL_END()  argument
1055 	return ((val) << MDP4_DTV_DISPLAY_HCTRL_END__SHIFT) & MDP4_DTV_DISPLAY_HCTRL_END__MASK;  in MDP4_DTV_DISPLAY_HCTRL_END()
1065 static inline uint32_t MDP4_DTV_ACTIVE_HCTL_START(uint32_t val)  in MDP4_DTV_ACTIVE_HCTL_START()  argument
1067 	return ((val) << MDP4_DTV_ACTIVE_HCTL_START__SHIFT) & MDP4_DTV_ACTIVE_HCTL_START__MASK;  in MDP4_DTV_ACTIVE_HCTL_START()
1071 static inline uint32_t MDP4_DTV_ACTIVE_HCTL_END(uint32_t val)  in MDP4_DTV_ACTIVE_HCTL_END()  argument
1073 	return ((val) << MDP4_DTV_ACTIVE_HCTL_END__SHIFT) & MDP4_DTV_ACTIVE_HCTL_END__MASK;  in MDP4_DTV_ACTIVE_HCTL_END()
1086 static inline uint32_t MDP4_DTV_UNDERFLOW_CLR_COLOR(uint32_t val)  in MDP4_DTV_UNDERFLOW_CLR_COLOR()  argument
1088 	return ((val) << MDP4_DTV_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_DTV_UNDERFLOW_CLR_COLOR__MASK;  in MDP4_DTV_UNDERFLOW_CLR_COLOR()
1108 static inline uint32_t MDP4_DSI_HSYNC_CTRL_PULSEW(uint32_t val)  in MDP4_DSI_HSYNC_CTRL_PULSEW()  argument
1110 	return ((val) << MDP4_DSI_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_DSI_HSYNC_CTRL_PULSEW__MASK;  in MDP4_DSI_HSYNC_CTRL_PULSEW()
1114 static inline uint32_t MDP4_DSI_HSYNC_CTRL_PERIOD(uint32_t val)  in MDP4_DSI_HSYNC_CTRL_PERIOD()  argument
1116 	return ((val) << MDP4_DSI_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_DSI_HSYNC_CTRL_PERIOD__MASK;  in MDP4_DSI_HSYNC_CTRL_PERIOD()
1126 static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_START(uint32_t val)  in MDP4_DSI_DISPLAY_HCTRL_START()  argument
1128 	return ((val) << MDP4_DSI_DISPLAY_HCTRL_START__SHIFT) & MDP4_DSI_DISPLAY_HCTRL_START__MASK;  in MDP4_DSI_DISPLAY_HCTRL_START()
1132 static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_END(uint32_t val)  in MDP4_DSI_DISPLAY_HCTRL_END()  argument
1134 	return ((val) << MDP4_DSI_DISPLAY_HCTRL_END__SHIFT) & MDP4_DSI_DISPLAY_HCTRL_END__MASK;  in MDP4_DSI_DISPLAY_HCTRL_END()
1144 static inline uint32_t MDP4_DSI_ACTIVE_HCTL_START(uint32_t val)  in MDP4_DSI_ACTIVE_HCTL_START()  argument
1146 	return ((val) << MDP4_DSI_ACTIVE_HCTL_START__SHIFT) & MDP4_DSI_ACTIVE_HCTL_START__MASK;  in MDP4_DSI_ACTIVE_HCTL_START()
1150 static inline uint32_t MDP4_DSI_ACTIVE_HCTL_END(uint32_t val)  in MDP4_DSI_ACTIVE_HCTL_END()  argument
1152 	return ((val) << MDP4_DSI_ACTIVE_HCTL_END__SHIFT) & MDP4_DSI_ACTIVE_HCTL_END__MASK;  in MDP4_DSI_ACTIVE_HCTL_END()
1165 static inline uint32_t MDP4_DSI_UNDERFLOW_CLR_COLOR(uint32_t val)  in MDP4_DSI_UNDERFLOW_CLR_COLOR()  argument
1167 	return ((val) << MDP4_DSI_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_DSI_UNDERFLOW_CLR_COLOR__MASK;  in MDP4_DSI_UNDERFLOW_CLR_COLOR()