Lines Matching +full:0 +full:x0000ffff
57 VG1 = 0,
67 MIXER0 = 0,
73 INTF_LCDC_DTV = 0,
85 FRAME_LINEAR = 0,
91 SCALE_FIR = 0,
97 DMA_P = 0,
102 #define MDP4_IRQ_OVERLAY0_DONE 0x00000001
103 #define MDP4_IRQ_OVERLAY1_DONE 0x00000002
104 #define MDP4_IRQ_DMA_S_DONE 0x00000004
105 #define MDP4_IRQ_DMA_E_DONE 0x00000008
106 #define MDP4_IRQ_DMA_P_DONE 0x00000010
107 #define MDP4_IRQ_VG1_HISTOGRAM 0x00000020
108 #define MDP4_IRQ_VG2_HISTOGRAM 0x00000040
109 #define MDP4_IRQ_PRIMARY_VSYNC 0x00000080
110 #define MDP4_IRQ_PRIMARY_INTF_UDERRUN 0x00000100
111 #define MDP4_IRQ_EXTERNAL_VSYNC 0x00000200
112 #define MDP4_IRQ_EXTERNAL_INTF_UDERRUN 0x00000400
113 #define MDP4_IRQ_PRIMARY_RDPTR 0x00000800
114 #define MDP4_IRQ_DMA_P_HISTOGRAM 0x00020000
115 #define MDP4_IRQ_DMA_S_HISTOGRAM 0x04000000
116 #define MDP4_IRQ_OVERLAY2_DONE 0x40000000
117 #define REG_MDP4_VERSION 0x00000000
118 #define MDP4_VERSION_MINOR__MASK 0x00ff0000
124 #define MDP4_VERSION_MAJOR__MASK 0xff000000
131 #define REG_MDP4_OVLP0_KICK 0x00000004
133 #define REG_MDP4_OVLP1_KICK 0x00000008
135 #define REG_MDP4_OVLP2_KICK 0x000000d0
137 #define REG_MDP4_DMA_P_KICK 0x0000000c
139 #define REG_MDP4_DMA_S_KICK 0x00000010
141 #define REG_MDP4_DMA_E_KICK 0x00000014
143 #define REG_MDP4_DISP_STATUS 0x00000018
145 #define REG_MDP4_DISP_INTF_SEL 0x00000038
146 #define MDP4_DISP_INTF_SEL_PRIM__MASK 0x00000003
147 #define MDP4_DISP_INTF_SEL_PRIM__SHIFT 0
152 #define MDP4_DISP_INTF_SEL_SEC__MASK 0x0000000c
158 #define MDP4_DISP_INTF_SEL_EXT__MASK 0x00000030
164 #define MDP4_DISP_INTF_SEL_DSI_VIDEO 0x00000040
165 #define MDP4_DISP_INTF_SEL_DSI_CMD 0x00000080
167 #define REG_MDP4_RESET_STATUS 0x0000003c
169 #define REG_MDP4_READ_CNFG 0x0000004c
171 #define REG_MDP4_INTR_ENABLE 0x00000050
173 #define REG_MDP4_INTR_STATUS 0x00000054
175 #define REG_MDP4_INTR_CLEAR 0x00000058
177 #define REG_MDP4_EBI2_LCD0 0x00000060
179 #define REG_MDP4_EBI2_LCD1 0x00000064
181 #define REG_MDP4_PORTMAP_MODE 0x00000070
183 #define REG_MDP4_CS_CONTROLLER0 0x000000c0
185 #define REG_MDP4_CS_CONTROLLER1 0x000000c4
187 #define REG_MDP4_LAYERMIXER2_IN_CFG 0x000100f0
188 #define MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK 0x00000007
189 #define MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT 0
194 #define MDP4_LAYERMIXER2_IN_CFG_PIPE0_MIXER1 0x00000008
195 #define MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK 0x00000070
201 #define MDP4_LAYERMIXER2_IN_CFG_PIPE1_MIXER1 0x00000080
202 #define MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK 0x00000700
208 #define MDP4_LAYERMIXER2_IN_CFG_PIPE2_MIXER1 0x00000800
209 #define MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK 0x00007000
215 #define MDP4_LAYERMIXER2_IN_CFG_PIPE3_MIXER1 0x00008000
216 #define MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK 0x00070000
222 #define MDP4_LAYERMIXER2_IN_CFG_PIPE4_MIXER1 0x00080000
223 #define MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK 0x00700000
229 #define MDP4_LAYERMIXER2_IN_CFG_PIPE5_MIXER1 0x00800000
230 #define MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK 0x07000000
236 #define MDP4_LAYERMIXER2_IN_CFG_PIPE6_MIXER1 0x08000000
237 #define MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK 0x70000000
243 #define MDP4_LAYERMIXER2_IN_CFG_PIPE7_MIXER1 0x80000000
245 #define REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD 0x000100fc
247 #define REG_MDP4_LAYERMIXER_IN_CFG 0x00010100
248 #define MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK 0x00000007
249 #define MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT 0
254 #define MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1 0x00000008
255 #define MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK 0x00000070
261 #define MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1 0x00000080
262 #define MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK 0x00000700
268 #define MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1 0x00000800
269 #define MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK 0x00007000
275 #define MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1 0x00008000
276 #define MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK 0x00070000
282 #define MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1 0x00080000
283 #define MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK 0x00700000
289 #define MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1 0x00800000
290 #define MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK 0x07000000
296 #define MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1 0x08000000
297 #define MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK 0x70000000
303 #define MDP4_LAYERMIXER_IN_CFG_PIPE7_MIXER1 0x80000000
305 #define REG_MDP4_VG2_SRC_FORMAT 0x00030050
307 #define REG_MDP4_VG2_CONST_COLOR 0x00031008
309 #define REG_MDP4_OVERLAY_FLUSH 0x00018000
310 #define MDP4_OVERLAY_FLUSH_OVLP0 0x00000001
311 #define MDP4_OVERLAY_FLUSH_OVLP1 0x00000002
312 #define MDP4_OVERLAY_FLUSH_VG1 0x00000004
313 #define MDP4_OVERLAY_FLUSH_VG2 0x00000008
314 #define MDP4_OVERLAY_FLUSH_RGB1 0x00000010
315 #define MDP4_OVERLAY_FLUSH_RGB2 0x00000020
320 case 0: return 0x00010000; in __offset_OVLP()
321 case 1: return 0x00018000; in __offset_OVLP()
322 case 2: return 0x00088000; in __offset_OVLP()
326 static inline uint32_t REG_MDP4_OVLP(uint32_t i0) { return 0x00000000 + __offset_OVLP(i0); } in REG_MDP4_OVLP()
328 static inline uint32_t REG_MDP4_OVLP_CFG(uint32_t i0) { return 0x00000004 + __offset_OVLP(i0); } in REG_MDP4_OVLP_CFG()
330 static inline uint32_t REG_MDP4_OVLP_SIZE(uint32_t i0) { return 0x00000008 + __offset_OVLP(i0); } in REG_MDP4_OVLP_SIZE()
331 #define MDP4_OVLP_SIZE_HEIGHT__MASK 0xffff0000
337 #define MDP4_OVLP_SIZE_WIDTH__MASK 0x0000ffff
338 #define MDP4_OVLP_SIZE_WIDTH__SHIFT 0
344 static inline uint32_t REG_MDP4_OVLP_BASE(uint32_t i0) { return 0x0000000c + __offset_OVLP(i0); } in REG_MDP4_OVLP_BASE()
346 static inline uint32_t REG_MDP4_OVLP_STRIDE(uint32_t i0) { return 0x00000010 + __offset_OVLP(i0); } in REG_MDP4_OVLP_STRIDE()
348 static inline uint32_t REG_MDP4_OVLP_OPMODE(uint32_t i0) { return 0x00000014 + __offset_OVLP(i0); } in REG_MDP4_OVLP_OPMODE()
353 case 0: return 0x00000104; in __offset_STAGE()
354 case 1: return 0x00000124; in __offset_STAGE()
355 case 2: return 0x00000144; in __offset_STAGE()
356 case 3: return 0x00000160; in __offset_STAGE()
360 static inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset… in REG_MDP4_OVLP_STAGE()
362 static inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __off… in REG_MDP4_OVLP_STAGE_OP()
363 #define MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK 0x00000003
364 #define MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT 0
369 #define MDP4_OVLP_STAGE_OP_FG_INV_ALPHA 0x00000004
370 #define MDP4_OVLP_STAGE_OP_FG_MOD_ALPHA 0x00000008
371 #define MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK 0x00000030
377 #define MDP4_OVLP_STAGE_OP_BG_INV_ALPHA 0x00000040
378 #define MDP4_OVLP_STAGE_OP_BG_MOD_ALPHA 0x00000080
379 #define MDP4_OVLP_STAGE_OP_FG_TRANSP 0x00000100
380 #define MDP4_OVLP_STAGE_OP_BG_TRANSP 0x00000200
382 static inline uint32_t REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 +… in REG_MDP4_OVLP_STAGE_FG_ALPHA()
384 static inline uint32_t REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 +… in REG_MDP4_OVLP_STAGE_BG_ALPHA()
386 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000… in REG_MDP4_OVLP_STAGE_TRANSP_LOW0()
388 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x0000001… in REG_MDP4_OVLP_STAGE_TRANSP_LOW1()
390 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x000000… in REG_MDP4_OVLP_STAGE_TRANSP_HIGH0()
392 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x000000… in REG_MDP4_OVLP_STAGE_TRANSP_HIGH1()
397 case 0: return 0x00001004; in __offset_STAGE_CO3()
398 case 1: return 0x00001404; in __offset_STAGE_CO3()
399 case 2: return 0x00001804; in __offset_STAGE_CO3()
400 case 3: return 0x00001b84; in __offset_STAGE_CO3()
404 static inline uint32_t REG_MDP4_OVLP_STAGE_CO3(uint32_t i0, uint32_t i1) { return 0x00000000 + __of… in REG_MDP4_OVLP_STAGE_CO3()
406 static inline uint32_t REG_MDP4_OVLP_STAGE_CO3_SEL(uint32_t i0, uint32_t i1) { return 0x00000000 + … in REG_MDP4_OVLP_STAGE_CO3_SEL()
407 #define MDP4_OVLP_STAGE_CO3_SEL_FG_ALPHA 0x00000001
409 static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW0(uint32_t i0) { return 0x00000180 + __offset_OVLP(i… in REG_MDP4_OVLP_TRANSP_LOW0()
411 static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW1(uint32_t i0) { return 0x00000184 + __offset_OVLP(i… in REG_MDP4_OVLP_TRANSP_LOW1()
413 static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH0(uint32_t i0) { return 0x00000188 + __offset_OVLP(… in REG_MDP4_OVLP_TRANSP_HIGH0()
415 static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH1(uint32_t i0) { return 0x0000018c + __offset_OVLP(… in REG_MDP4_OVLP_TRANSP_HIGH1()
417 static inline uint32_t REG_MDP4_OVLP_CSC_CONFIG(uint32_t i0) { return 0x00000200 + __offset_OVLP(i0… in REG_MDP4_OVLP_CSC_CONFIG()
419 static inline uint32_t REG_MDP4_OVLP_CSC(uint32_t i0) { return 0x00002000 + __offset_OVLP(i0); } in REG_MDP4_OVLP_CSC()
422 …_t REG_MDP4_OVLP_CSC_MV(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1… in REG_MDP4_OVLP_CSC_MV()
424 …EG_MDP4_OVLP_CSC_MV_VAL(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1… in REG_MDP4_OVLP_CSC_MV_VAL()
426 …EG_MDP4_OVLP_CSC_PRE_BV(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1… in REG_MDP4_OVLP_CSC_PRE_BV()
428 …DP4_OVLP_CSC_PRE_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1… in REG_MDP4_OVLP_CSC_PRE_BV_VAL()
430 …G_MDP4_OVLP_CSC_POST_BV(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1… in REG_MDP4_OVLP_CSC_POST_BV()
432 …P4_OVLP_CSC_POST_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1… in REG_MDP4_OVLP_CSC_POST_BV_VAL()
434 …EG_MDP4_OVLP_CSC_PRE_LV(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1… in REG_MDP4_OVLP_CSC_PRE_LV()
436 …DP4_OVLP_CSC_PRE_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1… in REG_MDP4_OVLP_CSC_PRE_LV_VAL()
438 …G_MDP4_OVLP_CSC_POST_LV(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1… in REG_MDP4_OVLP_CSC_POST_LV()
440 …P4_OVLP_CSC_POST_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1… in REG_MDP4_OVLP_CSC_POST_LV_VAL()
442 #define REG_MDP4_DMA_P_OP_MODE 0x00090070
444 static inline uint32_t REG_MDP4_LUTN(uint32_t i0) { return 0x00094800 + 0x400*i0; } in REG_MDP4_LUTN()
446 …ine uint32_t REG_MDP4_LUTN_LUT(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; } in REG_MDP4_LUTN_LUT()
448 …uint32_t REG_MDP4_LUTN_LUT_VAL(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; } in REG_MDP4_LUTN_LUT_VAL()
450 #define REG_MDP4_DMA_S_OP_MODE 0x000a0028
452 static inline uint32_t REG_MDP4_DMA_E_QUANT(uint32_t i0) { return 0x000b0070 + 0x4*i0; } in REG_MDP4_DMA_E_QUANT()
457 case DMA_P: return 0x00090000; in __offset_DMA()
458 case DMA_S: return 0x000a0000; in __offset_DMA()
459 case DMA_E: return 0x000b0000; in __offset_DMA()
463 static inline uint32_t REG_MDP4_DMA(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); } in REG_MDP4_DMA()
465 static inline uint32_t REG_MDP4_DMA_CONFIG(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0)… in REG_MDP4_DMA_CONFIG()
466 #define MDP4_DMA_CONFIG_G_BPC__MASK 0x00000003
467 #define MDP4_DMA_CONFIG_G_BPC__SHIFT 0
472 #define MDP4_DMA_CONFIG_B_BPC__MASK 0x0000000c
478 #define MDP4_DMA_CONFIG_R_BPC__MASK 0x00000030
484 #define MDP4_DMA_CONFIG_PACK_ALIGN_MSB 0x00000080
485 #define MDP4_DMA_CONFIG_PACK__MASK 0x0000ff00
491 #define MDP4_DMA_CONFIG_DEFLKR_EN 0x01000000
492 #define MDP4_DMA_CONFIG_DITHER_EN 0x01000000
494 static inline uint32_t REG_MDP4_DMA_SRC_SIZE(enum mdp4_dma i0) { return 0x00000004 + __offset_DMA(i… in REG_MDP4_DMA_SRC_SIZE()
495 #define MDP4_DMA_SRC_SIZE_HEIGHT__MASK 0xffff0000
501 #define MDP4_DMA_SRC_SIZE_WIDTH__MASK 0x0000ffff
502 #define MDP4_DMA_SRC_SIZE_WIDTH__SHIFT 0
508 static inline uint32_t REG_MDP4_DMA_SRC_BASE(enum mdp4_dma i0) { return 0x00000008 + __offset_DMA(i… in REG_MDP4_DMA_SRC_BASE()
510 static inline uint32_t REG_MDP4_DMA_SRC_STRIDE(enum mdp4_dma i0) { return 0x0000000c + __offset_DMA… in REG_MDP4_DMA_SRC_STRIDE()
512 static inline uint32_t REG_MDP4_DMA_DST_SIZE(enum mdp4_dma i0) { return 0x00000010 + __offset_DMA(i… in REG_MDP4_DMA_DST_SIZE()
513 #define MDP4_DMA_DST_SIZE_HEIGHT__MASK 0xffff0000
519 #define MDP4_DMA_DST_SIZE_WIDTH__MASK 0x0000ffff
520 #define MDP4_DMA_DST_SIZE_WIDTH__SHIFT 0
526 static inline uint32_t REG_MDP4_DMA_CURSOR_SIZE(enum mdp4_dma i0) { return 0x00000044 + __offset_DM… in REG_MDP4_DMA_CURSOR_SIZE()
527 #define MDP4_DMA_CURSOR_SIZE_WIDTH__MASK 0x0000007f
528 #define MDP4_DMA_CURSOR_SIZE_WIDTH__SHIFT 0
533 #define MDP4_DMA_CURSOR_SIZE_HEIGHT__MASK 0x007f0000
540 static inline uint32_t REG_MDP4_DMA_CURSOR_BASE(enum mdp4_dma i0) { return 0x00000048 + __offset_DM… in REG_MDP4_DMA_CURSOR_BASE()
542 static inline uint32_t REG_MDP4_DMA_CURSOR_POS(enum mdp4_dma i0) { return 0x0000004c + __offset_DMA… in REG_MDP4_DMA_CURSOR_POS()
543 #define MDP4_DMA_CURSOR_POS_X__MASK 0x0000ffff
544 #define MDP4_DMA_CURSOR_POS_X__SHIFT 0
549 #define MDP4_DMA_CURSOR_POS_Y__MASK 0xffff0000
556 static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_CONFIG(enum mdp4_dma i0) { return 0x00000060 + __o… in REG_MDP4_DMA_CURSOR_BLEND_CONFIG()
557 #define MDP4_DMA_CURSOR_BLEND_CONFIG_CURSOR_EN 0x00000001
558 #define MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__MASK 0x00000006
564 #define MDP4_DMA_CURSOR_BLEND_CONFIG_TRANSP_EN 0x00000008
566 static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_PARAM(enum mdp4_dma i0) { return 0x00000064 + __of… in REG_MDP4_DMA_CURSOR_BLEND_PARAM()
568 static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_LOW(enum mdp4_dma i0) { return 0x00000068 + __offse… in REG_MDP4_DMA_BLEND_TRANS_LOW()
570 static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_HIGH(enum mdp4_dma i0) { return 0x0000006c + __offs… in REG_MDP4_DMA_BLEND_TRANS_HIGH()
572 static inline uint32_t REG_MDP4_DMA_FETCH_CONFIG(enum mdp4_dma i0) { return 0x00001004 + __offset_D… in REG_MDP4_DMA_FETCH_CONFIG()
574 static inline uint32_t REG_MDP4_DMA_CSC(enum mdp4_dma i0) { return 0x00003000 + __offset_DMA(i0); } in REG_MDP4_DMA_CSC()
577 …REG_MDP4_DMA_CSC_MV(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1… in REG_MDP4_DMA_CSC_MV()
579 …MDP4_DMA_CSC_MV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1… in REG_MDP4_DMA_CSC_MV_VAL()
581 …MDP4_DMA_CSC_PRE_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1… in REG_MDP4_DMA_CSC_PRE_BV()
583 …_DMA_CSC_PRE_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1… in REG_MDP4_DMA_CSC_PRE_BV_VAL()
585 …DP4_DMA_CSC_POST_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1… in REG_MDP4_DMA_CSC_POST_BV()
587 …DMA_CSC_POST_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1… in REG_MDP4_DMA_CSC_POST_BV_VAL()
589 …MDP4_DMA_CSC_PRE_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1… in REG_MDP4_DMA_CSC_PRE_LV()
591 …_DMA_CSC_PRE_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1… in REG_MDP4_DMA_CSC_PRE_LV_VAL()
593 …DP4_DMA_CSC_POST_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1… in REG_MDP4_DMA_CSC_POST_LV()
595 …DMA_CSC_POST_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1… in REG_MDP4_DMA_CSC_POST_LV_VAL()
597 static inline uint32_t REG_MDP4_PIPE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; } in REG_MDP4_PIPE()
599 static inline uint32_t REG_MDP4_PIPE_SRC_SIZE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; } in REG_MDP4_PIPE_SRC_SIZE()
600 #define MDP4_PIPE_SRC_SIZE_HEIGHT__MASK 0xffff0000
606 #define MDP4_PIPE_SRC_SIZE_WIDTH__MASK 0x0000ffff
607 #define MDP4_PIPE_SRC_SIZE_WIDTH__SHIFT 0
613 static inline uint32_t REG_MDP4_PIPE_SRC_XY(enum mdp4_pipe i0) { return 0x00020004 + 0x10000*i0; } in REG_MDP4_PIPE_SRC_XY()
614 #define MDP4_PIPE_SRC_XY_Y__MASK 0xffff0000
620 #define MDP4_PIPE_SRC_XY_X__MASK 0x0000ffff
621 #define MDP4_PIPE_SRC_XY_X__SHIFT 0
627 static inline uint32_t REG_MDP4_PIPE_DST_SIZE(enum mdp4_pipe i0) { return 0x00020008 + 0x10000*i0; } in REG_MDP4_PIPE_DST_SIZE()
628 #define MDP4_PIPE_DST_SIZE_HEIGHT__MASK 0xffff0000
634 #define MDP4_PIPE_DST_SIZE_WIDTH__MASK 0x0000ffff
635 #define MDP4_PIPE_DST_SIZE_WIDTH__SHIFT 0
641 static inline uint32_t REG_MDP4_PIPE_DST_XY(enum mdp4_pipe i0) { return 0x0002000c + 0x10000*i0; } in REG_MDP4_PIPE_DST_XY()
642 #define MDP4_PIPE_DST_XY_Y__MASK 0xffff0000
648 #define MDP4_PIPE_DST_XY_X__MASK 0x0000ffff
649 #define MDP4_PIPE_DST_XY_X__SHIFT 0
655 static inline uint32_t REG_MDP4_PIPE_SRCP0_BASE(enum mdp4_pipe i0) { return 0x00020010 + 0x10000*i0… in REG_MDP4_PIPE_SRCP0_BASE()
657 static inline uint32_t REG_MDP4_PIPE_SRCP1_BASE(enum mdp4_pipe i0) { return 0x00020014 + 0x10000*i0… in REG_MDP4_PIPE_SRCP1_BASE()
659 static inline uint32_t REG_MDP4_PIPE_SRCP2_BASE(enum mdp4_pipe i0) { return 0x00020018 + 0x10000*i0… in REG_MDP4_PIPE_SRCP2_BASE()
661 static inline uint32_t REG_MDP4_PIPE_SRCP3_BASE(enum mdp4_pipe i0) { return 0x0002001c + 0x10000*i0… in REG_MDP4_PIPE_SRCP3_BASE()
663 static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_A(enum mdp4_pipe i0) { return 0x00020040 + 0x10000*… in REG_MDP4_PIPE_SRC_STRIDE_A()
664 #define MDP4_PIPE_SRC_STRIDE_A_P0__MASK 0x0000ffff
665 #define MDP4_PIPE_SRC_STRIDE_A_P0__SHIFT 0
670 #define MDP4_PIPE_SRC_STRIDE_A_P1__MASK 0xffff0000
677 static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_B(enum mdp4_pipe i0) { return 0x00020044 + 0x10000*… in REG_MDP4_PIPE_SRC_STRIDE_B()
678 #define MDP4_PIPE_SRC_STRIDE_B_P2__MASK 0x0000ffff
679 #define MDP4_PIPE_SRC_STRIDE_B_P2__SHIFT 0
684 #define MDP4_PIPE_SRC_STRIDE_B_P3__MASK 0xffff0000
691 static inline uint32_t REG_MDP4_PIPE_SSTILE_FRAME_SIZE(enum mdp4_pipe i0) { return 0x00020048 + 0x1… in REG_MDP4_PIPE_SSTILE_FRAME_SIZE()
692 #define MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__MASK 0xffff0000
698 #define MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__MASK 0x0000ffff
699 #define MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__SHIFT 0
705 static inline uint32_t REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0) { return 0x00020050 + 0x10000*i0… in REG_MDP4_PIPE_SRC_FORMAT()
706 #define MDP4_PIPE_SRC_FORMAT_G_BPC__MASK 0x00000003
707 #define MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT 0
712 #define MDP4_PIPE_SRC_FORMAT_B_BPC__MASK 0x0000000c
718 #define MDP4_PIPE_SRC_FORMAT_R_BPC__MASK 0x00000030
724 #define MDP4_PIPE_SRC_FORMAT_A_BPC__MASK 0x000000c0
730 #define MDP4_PIPE_SRC_FORMAT_ALPHA_ENABLE 0x00000100
731 #define MDP4_PIPE_SRC_FORMAT_CPP__MASK 0x00000600
737 #define MDP4_PIPE_SRC_FORMAT_ROTATED_90 0x00001000
738 #define MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK 0x00006000
744 #define MDP4_PIPE_SRC_FORMAT_UNPACK_TIGHT 0x00020000
745 #define MDP4_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB 0x00040000
746 #define MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__MASK 0x00180000
752 #define MDP4_PIPE_SRC_FORMAT_SOLID_FILL 0x00400000
753 #define MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK 0x0c000000
759 #define MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__MASK 0x60000000
766 static inline uint32_t REG_MDP4_PIPE_SRC_UNPACK(enum mdp4_pipe i0) { return 0x00020054 + 0x10000*i0… in REG_MDP4_PIPE_SRC_UNPACK()
767 #define MDP4_PIPE_SRC_UNPACK_ELEM0__MASK 0x000000ff
768 #define MDP4_PIPE_SRC_UNPACK_ELEM0__SHIFT 0
773 #define MDP4_PIPE_SRC_UNPACK_ELEM1__MASK 0x0000ff00
779 #define MDP4_PIPE_SRC_UNPACK_ELEM2__MASK 0x00ff0000
785 #define MDP4_PIPE_SRC_UNPACK_ELEM3__MASK 0xff000000
792 static inline uint32_t REG_MDP4_PIPE_OP_MODE(enum mdp4_pipe i0) { return 0x00020058 + 0x10000*i0; } in REG_MDP4_PIPE_OP_MODE()
793 #define MDP4_PIPE_OP_MODE_SCALEX_EN 0x00000001
794 #define MDP4_PIPE_OP_MODE_SCALEY_EN 0x00000002
795 #define MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__MASK 0x0000000c
801 #define MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__MASK 0x00000030
807 #define MDP4_PIPE_OP_MODE_SRC_YCBCR 0x00000200
808 #define MDP4_PIPE_OP_MODE_DST_YCBCR 0x00000400
809 #define MDP4_PIPE_OP_MODE_CSC_EN 0x00000800
810 #define MDP4_PIPE_OP_MODE_FLIP_LR 0x00002000
811 #define MDP4_PIPE_OP_MODE_FLIP_UD 0x00004000
812 #define MDP4_PIPE_OP_MODE_DITHER_EN 0x00008000
813 #define MDP4_PIPE_OP_MODE_IGC_LUT_EN 0x00010000
814 #define MDP4_PIPE_OP_MODE_DEINT_EN 0x00040000
815 #define MDP4_PIPE_OP_MODE_DEINT_ODD_REF 0x00080000
817 static inline uint32_t REG_MDP4_PIPE_PHASEX_STEP(enum mdp4_pipe i0) { return 0x0002005c + 0x10000*i… in REG_MDP4_PIPE_PHASEX_STEP()
819 static inline uint32_t REG_MDP4_PIPE_PHASEY_STEP(enum mdp4_pipe i0) { return 0x00020060 + 0x10000*i… in REG_MDP4_PIPE_PHASEY_STEP()
821 static inline uint32_t REG_MDP4_PIPE_FETCH_CONFIG(enum mdp4_pipe i0) { return 0x00021004 + 0x10000*… in REG_MDP4_PIPE_FETCH_CONFIG()
823 static inline uint32_t REG_MDP4_PIPE_SOLID_COLOR(enum mdp4_pipe i0) { return 0x00021008 + 0x10000*i… in REG_MDP4_PIPE_SOLID_COLOR()
825 static inline uint32_t REG_MDP4_PIPE_CSC(enum mdp4_pipe i0) { return 0x00024000 + 0x10000*i0; } in REG_MDP4_PIPE_CSC()
828 …t REG_MDP4_PIPE_CSC_MV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; } in REG_MDP4_PIPE_CSC_MV()
830 …G_MDP4_PIPE_CSC_MV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; } in REG_MDP4_PIPE_CSC_MV_VAL()
832 …G_MDP4_PIPE_CSC_PRE_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; } in REG_MDP4_PIPE_CSC_PRE_BV()
834 …P4_PIPE_CSC_PRE_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; } in REG_MDP4_PIPE_CSC_PRE_BV_VAL()
836 …_MDP4_PIPE_CSC_POST_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; } in REG_MDP4_PIPE_CSC_POST_BV()
838 …4_PIPE_CSC_POST_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; } in REG_MDP4_PIPE_CSC_POST_BV_VAL()
840 …G_MDP4_PIPE_CSC_PRE_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; } in REG_MDP4_PIPE_CSC_PRE_LV()
842 …P4_PIPE_CSC_PRE_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; } in REG_MDP4_PIPE_CSC_PRE_LV_VAL()
844 …_MDP4_PIPE_CSC_POST_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; } in REG_MDP4_PIPE_CSC_POST_LV()
846 …4_PIPE_CSC_POST_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; } in REG_MDP4_PIPE_CSC_POST_LV_VAL()
848 #define REG_MDP4_LCDC 0x000c0000
850 #define REG_MDP4_LCDC_ENABLE 0x000c0000
852 #define REG_MDP4_LCDC_HSYNC_CTRL 0x000c0004
853 #define MDP4_LCDC_HSYNC_CTRL_PULSEW__MASK 0x0000ffff
854 #define MDP4_LCDC_HSYNC_CTRL_PULSEW__SHIFT 0
859 #define MDP4_LCDC_HSYNC_CTRL_PERIOD__MASK 0xffff0000
866 #define REG_MDP4_LCDC_VSYNC_PERIOD 0x000c0008
868 #define REG_MDP4_LCDC_VSYNC_LEN 0x000c000c
870 #define REG_MDP4_LCDC_DISPLAY_HCTRL 0x000c0010
871 #define MDP4_LCDC_DISPLAY_HCTRL_START__MASK 0x0000ffff
872 #define MDP4_LCDC_DISPLAY_HCTRL_START__SHIFT 0
877 #define MDP4_LCDC_DISPLAY_HCTRL_END__MASK 0xffff0000
884 #define REG_MDP4_LCDC_DISPLAY_VSTART 0x000c0014
886 #define REG_MDP4_LCDC_DISPLAY_VEND 0x000c0018
888 #define REG_MDP4_LCDC_ACTIVE_HCTL 0x000c001c
889 #define MDP4_LCDC_ACTIVE_HCTL_START__MASK 0x00007fff
890 #define MDP4_LCDC_ACTIVE_HCTL_START__SHIFT 0
895 #define MDP4_LCDC_ACTIVE_HCTL_END__MASK 0x7fff0000
901 #define MDP4_LCDC_ACTIVE_HCTL_ACTIVE_START_X 0x80000000
903 #define REG_MDP4_LCDC_ACTIVE_VSTART 0x000c0020
905 #define REG_MDP4_LCDC_ACTIVE_VEND 0x000c0024
907 #define REG_MDP4_LCDC_BORDER_CLR 0x000c0028
909 #define REG_MDP4_LCDC_UNDERFLOW_CLR 0x000c002c
910 #define MDP4_LCDC_UNDERFLOW_CLR_COLOR__MASK 0x00ffffff
911 #define MDP4_LCDC_UNDERFLOW_CLR_COLOR__SHIFT 0
916 #define MDP4_LCDC_UNDERFLOW_CLR_ENABLE_RECOVERY 0x80000000
918 #define REG_MDP4_LCDC_HSYNC_SKEW 0x000c0030
920 #define REG_MDP4_LCDC_TEST_CNTL 0x000c0034
922 #define REG_MDP4_LCDC_CTRL_POLARITY 0x000c0038
923 #define MDP4_LCDC_CTRL_POLARITY_HSYNC_LOW 0x00000001
924 #define MDP4_LCDC_CTRL_POLARITY_VSYNC_LOW 0x00000002
925 #define MDP4_LCDC_CTRL_POLARITY_DATA_EN_LOW 0x00000004
927 #define REG_MDP4_LCDC_LVDS_INTF_CTL 0x000c2000
928 #define MDP4_LCDC_LVDS_INTF_CTL_MODE_SEL 0x00000004
929 #define MDP4_LCDC_LVDS_INTF_CTL_RGB_OUT 0x00000008
930 #define MDP4_LCDC_LVDS_INTF_CTL_CH_SWAP 0x00000010
931 #define MDP4_LCDC_LVDS_INTF_CTL_CH1_RES_BIT 0x00000020
932 #define MDP4_LCDC_LVDS_INTF_CTL_CH2_RES_BIT 0x00000040
933 #define MDP4_LCDC_LVDS_INTF_CTL_ENABLE 0x00000080
934 #define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE0_EN 0x00000100
935 #define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE1_EN 0x00000200
936 #define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE2_EN 0x00000400
937 #define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE3_EN 0x00000800
938 #define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE0_EN 0x00001000
939 #define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE1_EN 0x00002000
940 #define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE2_EN 0x00004000
941 #define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE3_EN 0x00008000
942 #define MDP4_LCDC_LVDS_INTF_CTL_CH1_CLK_LANE_EN 0x00010000
943 #define MDP4_LCDC_LVDS_INTF_CTL_CH2_CLK_LANE_EN 0x00020000
945 static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL(uint32_t i0) { return 0x000c2014 + 0x8*i0; } in REG_MDP4_LCDC_LVDS_MUX_CTL()
947 static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(uint32_t i0) { return 0x000c2014 + 0x8*i0;… in REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0()
948 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__MASK 0x000000ff
949 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__SHIFT 0
954 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__MASK 0x0000ff00
960 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__MASK 0x00ff0000
966 #define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__MASK 0xff000000
973 static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(uint32_t i0) { return 0x000c2018 + 0x8*i0;… in REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4()
974 #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__MASK 0x000000ff
975 #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__SHIFT 0
980 #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__MASK 0x0000ff00
986 #define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__MASK 0x00ff0000
993 #define REG_MDP4_LCDC_LVDS_PHY_RESET 0x000c2034
995 #define REG_MDP4_LVDS_PHY_PLL_CTRL_0 0x000c3000
997 #define REG_MDP4_LVDS_PHY_PLL_CTRL_1 0x000c3004
999 #define REG_MDP4_LVDS_PHY_PLL_CTRL_2 0x000c3008
1001 #define REG_MDP4_LVDS_PHY_PLL_CTRL_3 0x000c300c
1003 #define REG_MDP4_LVDS_PHY_PLL_CTRL_5 0x000c3014
1005 #define REG_MDP4_LVDS_PHY_PLL_CTRL_6 0x000c3018
1007 #define REG_MDP4_LVDS_PHY_PLL_CTRL_7 0x000c301c
1009 #define REG_MDP4_LVDS_PHY_PLL_CTRL_8 0x000c3020
1011 #define REG_MDP4_LVDS_PHY_PLL_CTRL_9 0x000c3024
1013 #define REG_MDP4_LVDS_PHY_PLL_LOCKED 0x000c3080
1015 #define REG_MDP4_LVDS_PHY_CFG2 0x000c3108
1017 #define REG_MDP4_LVDS_PHY_CFG0 0x000c3100
1018 #define MDP4_LVDS_PHY_CFG0_SERIALIZATION_ENBLE 0x00000010
1019 #define MDP4_LVDS_PHY_CFG0_CHANNEL0 0x00000040
1020 #define MDP4_LVDS_PHY_CFG0_CHANNEL1 0x00000080
1022 #define REG_MDP4_DTV 0x000d0000
1024 #define REG_MDP4_DTV_ENABLE 0x000d0000
1026 #define REG_MDP4_DTV_HSYNC_CTRL 0x000d0004
1027 #define MDP4_DTV_HSYNC_CTRL_PULSEW__MASK 0x0000ffff
1028 #define MDP4_DTV_HSYNC_CTRL_PULSEW__SHIFT 0
1033 #define MDP4_DTV_HSYNC_CTRL_PERIOD__MASK 0xffff0000
1040 #define REG_MDP4_DTV_VSYNC_PERIOD 0x000d0008
1042 #define REG_MDP4_DTV_VSYNC_LEN 0x000d000c
1044 #define REG_MDP4_DTV_DISPLAY_HCTRL 0x000d0018
1045 #define MDP4_DTV_DISPLAY_HCTRL_START__MASK 0x0000ffff
1046 #define MDP4_DTV_DISPLAY_HCTRL_START__SHIFT 0
1051 #define MDP4_DTV_DISPLAY_HCTRL_END__MASK 0xffff0000
1058 #define REG_MDP4_DTV_DISPLAY_VSTART 0x000d001c
1060 #define REG_MDP4_DTV_DISPLAY_VEND 0x000d0020
1062 #define REG_MDP4_DTV_ACTIVE_HCTL 0x000d002c
1063 #define MDP4_DTV_ACTIVE_HCTL_START__MASK 0x00007fff
1064 #define MDP4_DTV_ACTIVE_HCTL_START__SHIFT 0
1069 #define MDP4_DTV_ACTIVE_HCTL_END__MASK 0x7fff0000
1075 #define MDP4_DTV_ACTIVE_HCTL_ACTIVE_START_X 0x80000000
1077 #define REG_MDP4_DTV_ACTIVE_VSTART 0x000d0030
1079 #define REG_MDP4_DTV_ACTIVE_VEND 0x000d0038
1081 #define REG_MDP4_DTV_BORDER_CLR 0x000d0040
1083 #define REG_MDP4_DTV_UNDERFLOW_CLR 0x000d0044
1084 #define MDP4_DTV_UNDERFLOW_CLR_COLOR__MASK 0x00ffffff
1085 #define MDP4_DTV_UNDERFLOW_CLR_COLOR__SHIFT 0
1090 #define MDP4_DTV_UNDERFLOW_CLR_ENABLE_RECOVERY 0x80000000
1092 #define REG_MDP4_DTV_HSYNC_SKEW 0x000d0048
1094 #define REG_MDP4_DTV_TEST_CNTL 0x000d004c
1096 #define REG_MDP4_DTV_CTRL_POLARITY 0x000d0050
1097 #define MDP4_DTV_CTRL_POLARITY_HSYNC_LOW 0x00000001
1098 #define MDP4_DTV_CTRL_POLARITY_VSYNC_LOW 0x00000002
1099 #define MDP4_DTV_CTRL_POLARITY_DATA_EN_LOW 0x00000004
1101 #define REG_MDP4_DSI 0x000e0000
1103 #define REG_MDP4_DSI_ENABLE 0x000e0000
1105 #define REG_MDP4_DSI_HSYNC_CTRL 0x000e0004
1106 #define MDP4_DSI_HSYNC_CTRL_PULSEW__MASK 0x0000ffff
1107 #define MDP4_DSI_HSYNC_CTRL_PULSEW__SHIFT 0
1112 #define MDP4_DSI_HSYNC_CTRL_PERIOD__MASK 0xffff0000
1119 #define REG_MDP4_DSI_VSYNC_PERIOD 0x000e0008
1121 #define REG_MDP4_DSI_VSYNC_LEN 0x000e000c
1123 #define REG_MDP4_DSI_DISPLAY_HCTRL 0x000e0010
1124 #define MDP4_DSI_DISPLAY_HCTRL_START__MASK 0x0000ffff
1125 #define MDP4_DSI_DISPLAY_HCTRL_START__SHIFT 0
1130 #define MDP4_DSI_DISPLAY_HCTRL_END__MASK 0xffff0000
1137 #define REG_MDP4_DSI_DISPLAY_VSTART 0x000e0014
1139 #define REG_MDP4_DSI_DISPLAY_VEND 0x000e0018
1141 #define REG_MDP4_DSI_ACTIVE_HCTL 0x000e001c
1142 #define MDP4_DSI_ACTIVE_HCTL_START__MASK 0x00007fff
1143 #define MDP4_DSI_ACTIVE_HCTL_START__SHIFT 0
1148 #define MDP4_DSI_ACTIVE_HCTL_END__MASK 0x7fff0000
1154 #define MDP4_DSI_ACTIVE_HCTL_ACTIVE_START_X 0x80000000
1156 #define REG_MDP4_DSI_ACTIVE_VSTART 0x000e0020
1158 #define REG_MDP4_DSI_ACTIVE_VEND 0x000e0024
1160 #define REG_MDP4_DSI_BORDER_CLR 0x000e0028
1162 #define REG_MDP4_DSI_UNDERFLOW_CLR 0x000e002c
1163 #define MDP4_DSI_UNDERFLOW_CLR_COLOR__MASK 0x00ffffff
1164 #define MDP4_DSI_UNDERFLOW_CLR_COLOR__SHIFT 0
1169 #define MDP4_DSI_UNDERFLOW_CLR_ENABLE_RECOVERY 0x80000000
1171 #define REG_MDP4_DSI_HSYNC_SKEW 0x000e0030
1173 #define REG_MDP4_DSI_TEST_CNTL 0x000e0034
1175 #define REG_MDP4_DSI_CTRL_POLARITY 0x000e0038
1176 #define MDP4_DSI_CTRL_POLARITY_HSYNC_LOW 0x00000001
1177 #define MDP4_DSI_CTRL_POLARITY_VSYNC_LOW 0x00000002
1178 #define MDP4_DSI_CTRL_POLARITY_DATA_EN_LOW 0x00000004