Lines Matching full:gpu
120 static int a6xx_crashdumper_init(struct msm_gpu *gpu, in a6xx_crashdumper_init() argument
123 dumper->ptr = msm_gem_kernel_new(gpu->dev, in a6xx_crashdumper_init()
124 SZ_1M, MSM_BO_WC, gpu->aspace, in a6xx_crashdumper_init()
133 static int a6xx_crashdumper_run(struct msm_gpu *gpu, in a6xx_crashdumper_run() argument
136 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_crashdumper_run()
150 gpu_write64(gpu, REG_A6XX_CP_CRASH_SCRIPT_BASE_LO, in a6xx_crashdumper_run()
153 gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 1); in a6xx_crashdumper_run()
155 ret = gpu_poll_timeout(gpu, REG_A6XX_CP_CRASH_DUMP_STATUS, val, in a6xx_crashdumper_run()
158 gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 0); in a6xx_crashdumper_run()
164 static int debugbus_read(struct msm_gpu *gpu, u32 block, u32 offset, in debugbus_read() argument
170 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_A, reg); in debugbus_read()
171 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_B, reg); in debugbus_read()
172 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_C, reg); in debugbus_read()
173 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_D, reg); in debugbus_read()
178 data[0] = gpu_read(gpu, REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2); in debugbus_read()
179 data[1] = gpu_read(gpu, REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1); in debugbus_read()
212 static int vbif_debugbus_read(struct msm_gpu *gpu, u32 ctrl0, u32 ctrl1, in vbif_debugbus_read() argument
217 gpu_write(gpu, ctrl0, reg); in vbif_debugbus_read()
220 gpu_write(gpu, ctrl1, i); in vbif_debugbus_read()
221 data[i] = gpu_read(gpu, REG_A6XX_VBIF_TEST_BUS_OUT); in vbif_debugbus_read()
236 static void a6xx_get_vbif_debugbus_block(struct msm_gpu *gpu, in a6xx_get_vbif_debugbus_block() argument
251 clk = gpu_read(gpu, REG_A6XX_VBIF_CLKON); in a6xx_get_vbif_debugbus_block()
254 gpu_write(gpu, REG_A6XX_VBIF_CLKON, in a6xx_get_vbif_debugbus_block()
258 gpu_write(gpu, REG_A6XX_VBIF_TEST_BUS1_CTRL0, 0); in a6xx_get_vbif_debugbus_block()
261 gpu_write(gpu, REG_A6XX_VBIF_TEST_BUS_OUT_CTRL, 1); in a6xx_get_vbif_debugbus_block()
266 ptr += vbif_debugbus_read(gpu, in a6xx_get_vbif_debugbus_block()
272 ptr += vbif_debugbus_read(gpu, in a6xx_get_vbif_debugbus_block()
278 gpu_write(gpu, REG_A6XX_VBIF_TEST_BUS2_CTRL0, 0); in a6xx_get_vbif_debugbus_block()
281 ptr += vbif_debugbus_read(gpu, in a6xx_get_vbif_debugbus_block()
287 gpu_write(gpu, REG_A6XX_VBIF_CLKON, clk); in a6xx_get_vbif_debugbus_block()
290 static void a6xx_get_debugbus_block(struct msm_gpu *gpu, in a6xx_get_debugbus_block() argument
305 ptr += debugbus_read(gpu, block->id, i, ptr); in a6xx_get_debugbus_block()
326 static void a6xx_get_debugbus(struct msm_gpu *gpu, in a6xx_get_debugbus() argument
335 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_CNTLT, in a6xx_get_debugbus()
338 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_CNTLM, in a6xx_get_debugbus()
341 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0, 0); in a6xx_get_debugbus()
342 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1, 0); in a6xx_get_debugbus()
343 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2, 0); in a6xx_get_debugbus()
344 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3, 0); in a6xx_get_debugbus()
346 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0, 0x76543210); in a6xx_get_debugbus()
347 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1, 0xFEDCBA98); in a6xx_get_debugbus()
349 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0, 0); in a6xx_get_debugbus()
350 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1, 0); in a6xx_get_debugbus()
351 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2, 0); in a6xx_get_debugbus()
352 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3, 0); in a6xx_get_debugbus()
357 res = platform_get_resource_byname(gpu->pdev, IORESOURCE_MEM, in a6xx_get_debugbus()
387 (a6xx_has_gbif(to_adreno_gpu(gpu)) ? 1 : 0); in a6xx_get_debugbus()
396 a6xx_get_debugbus_block(gpu, in a6xx_get_debugbus()
404 * GBIF has same debugbus as of other GPU blocks, fall back to in a6xx_get_debugbus()
405 * default path if GPU uses GBIF, also GBIF uses exactly same in a6xx_get_debugbus()
408 if (a6xx_has_gbif(to_adreno_gpu(gpu))) { in a6xx_get_debugbus()
409 a6xx_get_debugbus_block(gpu, a6xx_state, in a6xx_get_debugbus()
418 if (!a6xx_has_gbif(to_adreno_gpu(gpu))) { in a6xx_get_debugbus()
424 a6xx_get_vbif_debugbus_block(gpu, a6xx_state, in a6xx_get_debugbus()
454 static void a6xx_get_dbgahb_cluster(struct msm_gpu *gpu, in a6xx_get_dbgahb_cluster() argument
492 if (a6xx_crashdumper_run(gpu, dumper)) in a6xx_get_dbgahb_cluster()
500 static void a6xx_get_dbgahb_clusters(struct msm_gpu *gpu, in a6xx_get_dbgahb_clusters() argument
516 a6xx_get_dbgahb_cluster(gpu, a6xx_state, in a6xx_get_dbgahb_clusters()
522 static void a6xx_get_cluster(struct msm_gpu *gpu, in a6xx_get_cluster() argument
563 if (a6xx_crashdumper_run(gpu, dumper)) in a6xx_get_cluster()
571 static void a6xx_get_clusters(struct msm_gpu *gpu, in a6xx_get_clusters() argument
586 a6xx_get_cluster(gpu, a6xx_state, &a6xx_clusters[i], in a6xx_get_clusters()
591 static void a6xx_get_shader_block(struct msm_gpu *gpu, in a6xx_get_shader_block() argument
614 if (a6xx_crashdumper_run(gpu, dumper)) in a6xx_get_shader_block()
622 static void a6xx_get_shaders(struct msm_gpu *gpu, in a6xx_get_shaders() argument
637 a6xx_get_shader_block(gpu, a6xx_state, &a6xx_shader_blocks[i], in a6xx_get_shaders()
642 static void a6xx_get_crashdumper_hlsq_registers(struct msm_gpu *gpu, in a6xx_get_crashdumper_hlsq_registers() argument
671 if (a6xx_crashdumper_run(gpu, dumper)) in a6xx_get_crashdumper_hlsq_registers()
680 static void a6xx_get_crashdumper_registers(struct msm_gpu *gpu, in a6xx_get_crashdumper_registers() argument
709 if (a6xx_crashdumper_run(gpu, dumper)) in a6xx_get_crashdumper_registers()
718 static void a6xx_get_ahb_gpu_registers(struct msm_gpu *gpu, in a6xx_get_ahb_gpu_registers() argument
738 obj->data[index++] = gpu_read(gpu, in a6xx_get_ahb_gpu_registers()
744 static void _a6xx_get_gmu_registers(struct msm_gpu *gpu, in _a6xx_get_gmu_registers() argument
750 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in _a6xx_get_gmu_registers()
781 static void a6xx_get_gmu_registers(struct msm_gpu *gpu, in a6xx_get_gmu_registers() argument
784 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_get_gmu_registers()
796 _a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[0], in a6xx_get_gmu_registers()
798 _a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[1], in a6xx_get_gmu_registers()
805 gpu_write(gpu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0); in a6xx_get_gmu_registers()
807 _a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[2], in a6xx_get_gmu_registers()
834 static void a6xx_snapshot_gmu_hfi_history(struct msm_gpu *gpu, in a6xx_snapshot_gmu_hfi_history() argument
837 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_snapshot_gmu_hfi_history()
854 static void a6xx_get_registers(struct msm_gpu *gpu, in a6xx_get_registers() argument
862 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_get_registers()
873 a6xx_get_ahb_gpu_registers(gpu, in a6xx_get_registers()
878 a6xx_get_ahb_gpu_registers(gpu, in a6xx_get_registers()
882 a6xx_get_ahb_gpu_registers(gpu, in a6xx_get_registers()
888 * because the GPU has no memory access until we resume in a6xx_get_registers()
890 * we have captured as much useful GPU state as possible). in a6xx_get_registers()
894 a6xx_get_ahb_gpu_registers(gpu, in a6xx_get_registers()
901 a6xx_get_crashdumper_registers(gpu, in a6xx_get_registers()
907 a6xx_get_crashdumper_hlsq_registers(gpu, in a6xx_get_registers()
914 static void a6xx_get_indexed_regs(struct msm_gpu *gpu, in a6xx_get_indexed_regs() argument
927 gpu_write(gpu, indexed->addr, 0); in a6xx_get_indexed_regs()
931 obj->data[i] = gpu_read(gpu, indexed->data); in a6xx_get_indexed_regs()
934 static void a6xx_get_indexed_registers(struct msm_gpu *gpu, in a6xx_get_indexed_registers() argument
947 a6xx_get_indexed_regs(gpu, a6xx_state, &a6xx_indexed_reglist[i], in a6xx_get_indexed_registers()
951 mempool_size = gpu_read(gpu, REG_A6XX_CP_MEM_POOL_SIZE); in a6xx_get_indexed_registers()
952 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 0); in a6xx_get_indexed_registers()
955 a6xx_get_indexed_regs(gpu, a6xx_state, &a6xx_cp_mempool_indexed, in a6xx_get_indexed_registers()
965 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, mempool_size); in a6xx_get_indexed_registers()
970 struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu) in a6xx_gpu_state_get() argument
973 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_gpu_state_get()
977 bool stalled = !!(gpu_read(gpu, REG_A6XX_RBBM_STATUS3) & in a6xx_gpu_state_get()
986 adreno_gpu_state_get(gpu, &a6xx_state->base); in a6xx_gpu_state_get()
988 a6xx_get_gmu_registers(gpu, a6xx_state); in a6xx_gpu_state_get()
994 a6xx_snapshot_gmu_hfi_history(gpu, a6xx_state); in a6xx_gpu_state_get()
1001 a6xx_get_indexed_registers(gpu, a6xx_state); in a6xx_gpu_state_get()
1006 * write out GPU state, so we need to skip this when the SMMU is in a6xx_gpu_state_get()
1009 if (!stalled && !gpu->needs_hw_init && in a6xx_gpu_state_get()
1010 !a6xx_crashdumper_init(gpu, &_dumper)) { in a6xx_gpu_state_get()
1014 a6xx_get_registers(gpu, a6xx_state, dumper); in a6xx_gpu_state_get()
1017 a6xx_get_shaders(gpu, a6xx_state, dumper); in a6xx_gpu_state_get()
1018 a6xx_get_clusters(gpu, a6xx_state, dumper); in a6xx_gpu_state_get()
1019 a6xx_get_dbgahb_clusters(gpu, a6xx_state, dumper); in a6xx_gpu_state_get()
1021 msm_gem_kernel_put(dumper->bo, gpu->aspace); in a6xx_gpu_state_get()
1025 a6xx_get_debugbus(gpu, a6xx_state); in a6xx_gpu_state_get()
1027 a6xx_state->gpu_initialized = !gpu->needs_hw_init; in a6xx_gpu_state_get()
1252 void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state, in a6xx_show() argument
1262 drm_printf(p, "gpu-initialized: %d\n", a6xx_state->gpu_initialized); in a6xx_show()
1264 adreno_show(gpu, state, p); in a6xx_show()