88 	gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr);  in a6xx_flush()
619 		gpu_write(gpu, reg->offset, state ? reg->value : 0);  in a6xx_set_hwcg()
624 	gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0);  in a6xx_set_hwcg()
779 	gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, BIT(0) | BIT(1) | BIT(3));  in a6xx_set_cp_protect()
782 		gpu_write(gpu, REG_A6XX_CP_PROTECT(i), regs[i]);  in a6xx_set_cp_protect()
784 	gpu_write(gpu, REG_A6XX_CP_PROTECT(count_max - 1), regs[i]);  in a6xx_set_cp_protect()
817 	gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL,  in a6xx_set_ubwc_config()
819 	gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, lower_bit << 1);  in a6xx_set_ubwc_config()
820 	gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL,  in a6xx_set_ubwc_config()
822 	gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, lower_bit << 21);  in a6xx_set_ubwc_config()
993 		gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0);  in hw_init()
995 	gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0);  in hw_init()
1004 	gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000);  in hw_init()
1007 	gpu_write(gpu, REG_A6XX_CP_ADDR_MODE_CNTL, 0x1);  in hw_init()
1008 	gpu_write(gpu, REG_A6XX_VSC_ADDR_MODE_CNTL, 0x1);  in hw_init()
1009 	gpu_write(gpu, REG_A6XX_GRAS_ADDR_MODE_CNTL, 0x1);  in hw_init()
1010 	gpu_write(gpu, REG_A6XX_RB_ADDR_MODE_CNTL, 0x1);  in hw_init()
1011 	gpu_write(gpu, REG_A6XX_PC_ADDR_MODE_CNTL, 0x1);  in hw_init()
1012 	gpu_write(gpu, REG_A6XX_HLSQ_ADDR_MODE_CNTL, 0x1);  in hw_init()
1013 	gpu_write(gpu, REG_A6XX_VFD_ADDR_MODE_CNTL, 0x1);  in hw_init()
1014 	gpu_write(gpu, REG_A6XX_VPC_ADDR_MODE_CNTL, 0x1);  in hw_init()
1015 	gpu_write(gpu, REG_A6XX_UCHE_ADDR_MODE_CNTL, 0x1);  in hw_init()
1016 	gpu_write(gpu, REG_A6XX_SP_ADDR_MODE_CNTL, 0x1);  in hw_init()
1017 	gpu_write(gpu, REG_A6XX_TPL1_ADDR_MODE_CNTL, 0x1);  in hw_init()
1018 	gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1);  in hw_init()
1026 		gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620);  in hw_init()
1027 		gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620);  in hw_init()
1028 		gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620);  in hw_init()
1029 		gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620);  in hw_init()
1030 		gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620);  in hw_init()
1031 		gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x3);  in hw_init()
1033 		gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3);  in hw_init()
1037 		gpu_write(gpu, REG_A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009);  in hw_init()
1040 	gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff);  in hw_init()
1043 	gpu_write(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_LO, 0xffffffc0);  in hw_init()
1044 	gpu_write(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_HI, 0x0001ffff);  in hw_init()
1045 	gpu_write(gpu, REG_A6XX_UCHE_TRAP_BASE_LO, 0xfffff000);  in hw_init()
1046 	gpu_write(gpu, REG_A6XX_UCHE_TRAP_BASE_HI, 0x0001ffff);  in hw_init()
1047 	gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_LO, 0xfffff000);  in hw_init()
1048 	gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_HI, 0x0001ffff);  in hw_init()
1060 	gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804);  in hw_init()
1061 	gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4);  in hw_init()
1065 		gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140);  in hw_init()
1067 		gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0);  in hw_init()
1068 	gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c);  in hw_init()
1071 		gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020);  in hw_init()
1074 	gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128);  in hw_init()
1080 		gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200);  in hw_init()
1082 		gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200);  in hw_init()
1084 		gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200);  in hw_init()
1086 		gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00180000);  in hw_init()
1089 	gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1);  in hw_init()
1092 	gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_CNTL, 0x1);  in hw_init()
1095 	gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL(0), PERF_CP_ALWAYS_COUNT);  in hw_init()
1100 	gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL,  in hw_init()
1103 	gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, 1);  in hw_init()
1107 		gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0);  in hw_init()
1108 		gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1,  in hw_init()
1110 		gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2,  in hw_init()
1112 		gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3,  in hw_init()
1114 		gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4,  in hw_init()
1122 		gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, 0x1);  in hw_init()
1123 		gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x0);  in hw_init()
1128 		gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 0x66906);  in hw_init()
1132 		gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL,  in hw_init()
1137 	gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, A6XX_INT_MASK);  in hw_init()
1156 		gpu_write(gpu, REG_A6XX_CP_RB_CNTL, MSM_GPU_RB_CNTL_DEFAULT);  in hw_init()
1158 		gpu_write(gpu, REG_A6XX_CP_RB_CNTL,  in hw_init()
1191 	gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 1);  in hw_init()
1221 		gpu_write(gpu, REG_A6XX_RBBM_SECVID_TRUST_CNTL, 0x0);  in hw_init()
1281 	gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 3);  in a6xx_recover()
1440 		gpu_write(gpu, REG_A6XX_CP_SQE_STAT_ADDR, 1);  in a6xx_cp_hw_err_irq()
1518 	gpu_write(gpu, REG_A6XX_RBBM_INT_CLEAR_CMD, status);  in a6xx_irq()