28 	if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) &  in _a6xx_check_idle()
32 	return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) &  in _a6xx_check_idle()
45 			gpu_read(gpu, REG_A6XX_RBBM_STATUS),  in a6xx_idle()
46 			gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS),  in a6xx_idle()
47 			gpu_read(gpu, REG_A6XX_CP_RB_RPTR),  in a6xx_idle()
48 			gpu_read(gpu, REG_A6XX_CP_RB_WPTR));  in a6xx_idle()
609 	val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL);  in a6xx_set_hwcg()
1258 			gpu_read(gpu, REG_A6XX_RBBM_STATUS));  in a6xx_dump()
1275 			gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(i)));  in a6xx_recover()
1338 	val = gpu_read(gpu, REG_A6XX_UCHE_CLIENT_PF);  in a6xx_uche_fault_block()
1391 			gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)),  in a6xx_fault_handler()
1392 			gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)),  in a6xx_fault_handler()
1393 			gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)),  in a6xx_fault_handler()
1394 			gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7)));  in a6xx_fault_handler()
1412 			gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)),  in a6xx_fault_handler()
1413 			gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)),  in a6xx_fault_handler()
1414 			gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)),  in a6xx_fault_handler()
1415 			gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7)));  in a6xx_fault_handler()
1435 	u32 status = gpu_read(gpu, REG_A6XX_CP_INTERRUPT_STATUS);  in a6xx_cp_hw_err_irq()
1441 		val = gpu_read(gpu, REG_A6XX_CP_SQE_STAT_DATA);  in a6xx_cp_hw_err_irq()
1453 			gpu_read(gpu, REG_A6XX_CP_HW_FAULT));  in a6xx_cp_hw_err_irq()
1456 		u32 val = gpu_read(gpu, REG_A6XX_CP_PROTECT_STATUS);  in a6xx_cp_hw_err_irq()
1487 	if (gpu_read(gpu, REG_A6XX_RBBM_STATUS3) & A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT)  in a6xx_fault_detect_irq()
1499 		gpu_read(gpu, REG_A6XX_RBBM_STATUS),  in a6xx_fault_detect_irq()
1500 		gpu_read(gpu, REG_A6XX_CP_RB_RPTR),  in a6xx_fault_detect_irq()
1501 		gpu_read(gpu, REG_A6XX_CP_RB_WPTR),  in a6xx_fault_detect_irq()
1503 		gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE),  in a6xx_fault_detect_irq()
1505 		gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE));  in a6xx_fault_detect_irq()
1516 	u32 status = gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS);  in a6xx_irq()
1851 	return ring->memptrs->rptr = gpu_read(gpu, REG_A6XX_CP_RB_RPTR);  in a6xx_get_rptr()