63 		OUT_RING(ring, lower_32_bits(shadowptr(a6xx_gpu, ring)));  in update_shadow_rptr()
64 		OUT_RING(ring, upper_32_bits(shadowptr(a6xx_gpu, ring)));  in update_shadow_rptr()
95 	OUT_RING(ring, CP_REG_TO_MEM_0_REG(counter) |  in get_stats_counter()
98 	OUT_RING(ring, lower_32_bits(iova));  in get_stats_counter()
99 	OUT_RING(ring, upper_32_bits(iova));  in get_stats_counter()
119 		OUT_RING(ring, 0);  in a6xx_set_pagetable()
122 		OUT_RING(ring, 1);  in a6xx_set_pagetable()
127 	OUT_RING(ring, CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(lower_32_bits(ttbr)));  in a6xx_set_pagetable()
129 	OUT_RING(ring,  in a6xx_set_pagetable()
132 	OUT_RING(ring, CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(0));  in a6xx_set_pagetable()
133 	OUT_RING(ring, CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(0));  in a6xx_set_pagetable()
139 	OUT_RING(ring, CP_MEM_WRITE_0_ADDR_LO(lower_32_bits(memptr)));  in a6xx_set_pagetable()
140 	OUT_RING(ring, CP_MEM_WRITE_1_ADDR_HI(upper_32_bits(memptr)));  in a6xx_set_pagetable()
141 	OUT_RING(ring, lower_32_bits(ttbr));  in a6xx_set_pagetable()
142 	OUT_RING(ring, (asid << 16) | upper_32_bits(ttbr));  in a6xx_set_pagetable()
150 	OUT_RING(ring, CACHE_INVALIDATE);  in a6xx_set_pagetable()
158 		OUT_RING(ring, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ));  in a6xx_set_pagetable()
159 		OUT_RING(ring, CP_WAIT_REG_MEM_1_POLL_ADDR_LO(  in a6xx_set_pagetable()
161 		OUT_RING(ring, CP_WAIT_REG_MEM_2_POLL_ADDR_HI(0));  in a6xx_set_pagetable()
162 		OUT_RING(ring, CP_WAIT_REG_MEM_3_REF(0x1));  in a6xx_set_pagetable()
163 		OUT_RING(ring, CP_WAIT_REG_MEM_4_MASK(0x1));  in a6xx_set_pagetable()
164 		OUT_RING(ring, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(0));  in a6xx_set_pagetable()
168 		OUT_RING(ring, 1);  in a6xx_set_pagetable()
195 	OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(PC_CCU_INVALIDATE_DEPTH));  in a6xx_submit()
198 	OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(PC_CCU_INVALIDATE_COLOR));  in a6xx_submit()
211 			OUT_RING(ring, lower_32_bits(submit->cmd[i].iova));  in a6xx_submit()
212 			OUT_RING(ring, upper_32_bits(submit->cmd[i].iova));  in a6xx_submit()
213 			OUT_RING(ring, submit->cmd[i].size);  in a6xx_submit()
236 	OUT_RING(ring, submit->seqno);  in a6xx_submit()
243 	OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(CACHE_FLUSH_TS) |  in a6xx_submit()
245 	OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence)));  in a6xx_submit()
246 	OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence)));  in a6xx_submit()
247 	OUT_RING(ring, submit->seqno);  in a6xx_submit()
831 	OUT_RING(ring, 0x0000002f);  in a6xx_cp_init()
834 	OUT_RING(ring, 0x00000003);  in a6xx_cp_init()
837 	OUT_RING(ring, 0x20000000);  in a6xx_cp_init()
840 	OUT_RING(ring, 0x00000000);  in a6xx_cp_init()
841 	OUT_RING(ring, 0x00000000);  in a6xx_cp_init()
844 	OUT_RING(ring, 0x00000000);  in a6xx_cp_init()
847 	OUT_RING(ring, 0x00000000);  in a6xx_cp_init()
848 	OUT_RING(ring, 0x00000000);  in a6xx_cp_init()
1207 		OUT_RING(gpu->rb[0], 0x00000000);  in hw_init()