519 	void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc");  in a6xx_gmu_rpmh_init()  local
524 	if (IS_ERR(pdcptr))  in a6xx_gmu_rpmh_init()
584 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK, 7);  in a6xx_gmu_rpmh_init()
585 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK, 0);  in a6xx_gmu_rpmh_init()
586 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CONTROL, 0);  in a6xx_gmu_rpmh_init()
587 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID, 0x10108);  in a6xx_gmu_rpmh_init()
588 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR, 0x30010);  in a6xx_gmu_rpmh_init()
589 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA, 1);  in a6xx_gmu_rpmh_init()
590 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 4, 0x10108);  in a6xx_gmu_rpmh_init()
591 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000);  in a6xx_gmu_rpmh_init()
592 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0);  in a6xx_gmu_rpmh_init()
594 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108);  in a6xx_gmu_rpmh_init()
595 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, pdc_address_offset);  in a6xx_gmu_rpmh_init()
596 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0);  in a6xx_gmu_rpmh_init()
598 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK, 7);  in a6xx_gmu_rpmh_init()
599 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0);  in a6xx_gmu_rpmh_init()
600 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CONTROL, 0);  in a6xx_gmu_rpmh_init()
601 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID, 0x10108);  in a6xx_gmu_rpmh_init()
602 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR, 0x30010);  in a6xx_gmu_rpmh_init()
603 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA, 2);  in a6xx_gmu_rpmh_init()
605 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108);  in a6xx_gmu_rpmh_init()
606 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000);  in a6xx_gmu_rpmh_init()
609 		pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x2);  in a6xx_gmu_rpmh_init()
611 		pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3);  in a6xx_gmu_rpmh_init()
612 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108);  in a6xx_gmu_rpmh_init()
613 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, pdc_address_offset);  in a6xx_gmu_rpmh_init()
614 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3);  in a6xx_gmu_rpmh_init()
618 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0);  in a6xx_gmu_rpmh_init()
619 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001);  in a6xx_gmu_rpmh_init()
625 	if (!IS_ERR_OR_NULL(pdcptr))  in a6xx_gmu_rpmh_init()
626 		iounmap(pdcptr);  in a6xx_gmu_rpmh_init()