51 		dev_err_ratelimited(gmu->dev, "GMU fence error: 0x%x\n",  in a6xx_gmu_irq()
113 	int ret = 0;  in a6xx_gmu_set_freq()
120 	for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1; perf_index++)  in a6xx_gmu_set_freq()
144 	gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0);  in a6xx_gmu_set_freq()
147 			((3 & 0xf) << 28) | perf_index);  in a6xx_gmu_set_freq()
153 	gmu_write(gmu, REG_A6XX_GMU_DCVS_BW_SETTING, 0xff);  in a6xx_gmu_set_freq()
207 	val = gmu_read(gmu, REG_A6XX_GMU_CM3_DTCM_START + 0xff8);  in a6xx_gmu_start()
208 	if (val <= 0x20010004) {  in a6xx_gmu_start()
209 		mask = 0xffffffff;  in a6xx_gmu_start()
210 		reset_val = 0xbabeface;  in a6xx_gmu_start()
212 		mask = 0x1ff;  in a6xx_gmu_start()
213 		reset_val = 0x100;  in a6xx_gmu_start()
221 	gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP, 0);  in a6xx_gmu_start()
223 	gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 0);  in a6xx_gmu_start()
328 			"Timeout waiting for GMU OOB set %s: 0x%x\n",  in a6xx_gmu_set_oob()
363 		return 0;  in a6xx_sptprac_enable()
365 	gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778000);  in a6xx_sptprac_enable()
368 		(val & 0x38) == 0x28, 1, 100);  in a6xx_sptprac_enable()
371 		DRM_DEV_ERROR(gmu->dev, "Unable to power on SPTPRAC: 0x%x\n",  in a6xx_sptprac_enable()
375 	return 0;  in a6xx_sptprac_enable()
388 	gmu_rmw(gmu, REG_A6XX_GPU_CC_GX_GDSCR, 0, (1 << 11));  in a6xx_sptprac_disable()
390 	gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778001);  in a6xx_sptprac_disable()
393 		(val & 0x04), 100, 10000);  in a6xx_sptprac_disable()
396 		DRM_DEV_ERROR(gmu->dev, "failed to power off SPTPRAC: 0x%x\n",  in a6xx_sptprac_disable()
406 	gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 0);  in a6xx_gmu_gfx_rail_on()
411 	gmu_write(gmu, REG_A6XX_GMU_GX_VOTE_IDX, vote & 0xff);  in a6xx_gmu_gfx_rail_on()
412 	gmu_write(gmu, REG_A6XX_GMU_MX_VOTE_IDX, (vote >> 8) & 0xff);  in a6xx_gmu_gfx_rail_on()
424 	gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0);  in a6xx_gmu_notify_slumber()
444 			!= 0x0f) {  in a6xx_gmu_notify_slumber()
452 	gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);  in a6xx_gmu_notify_slumber()
480 	gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0);  in a6xx_rpmh_start()
482 	/* Set up CX GMU counter 0 to count busy ticks */  in a6xx_rpmh_start()
483 	gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000);  in a6xx_rpmh_start()
484 	gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, 0x20);  in a6xx_rpmh_start()
488 	return 0;  in a6xx_rpmh_start()
503 	gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0);  in a6xx_rpmh_stop()
530 		pdc_address_offset = 0x30090;  in a6xx_gmu_rpmh_init()
532 		pdc_address_offset = 0x300a0;  in a6xx_gmu_rpmh_init()
534 		pdc_address_offset = 0x30080;  in a6xx_gmu_rpmh_init()
547 	gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA, 0);  in a6xx_gmu_rpmh_init()
548 	gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR, 0);  in a6xx_gmu_rpmh_init()
549 	gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 2, 0);  in a6xx_gmu_rpmh_init()
550 	gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 2, 0);  in a6xx_gmu_rpmh_init()
551 	gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 4, 0x80000000);  in a6xx_gmu_rpmh_init()
552 	gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 4, 0);  in a6xx_gmu_rpmh_init()
553 	gmu_write_rscc(gmu, REG_A6XX_RSCC_OVERRIDE_START_ADDR, 0);  in a6xx_gmu_rpmh_init()
554 	gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SEQ_START_ADDR, 0x4520);  in a6xx_gmu_rpmh_init()
555 	gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_LO, 0x4510);  in a6xx_gmu_rpmh_init()
556 	gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514);  in a6xx_gmu_rpmh_init()
560 		gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xeaaae5a0);  in a6xx_gmu_rpmh_init()
561 		gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xe1a1ebab);  in a6xx_gmu_rpmh_init()
562 		gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e0a581);  in a6xx_gmu_rpmh_init()
563 		gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xecac82e2);  in a6xx_gmu_rpmh_init()
564 		gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020edad);  in a6xx_gmu_rpmh_init()
566 		gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xa7a506a0);  in a6xx_gmu_rpmh_init()
567 		gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xa1e6a6e7);  in a6xx_gmu_rpmh_init()
568 		gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e081e1);  in a6xx_gmu_rpmh_init()
569 		gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xe9a982e2);  in a6xx_gmu_rpmh_init()
570 		gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8);  in a6xx_gmu_rpmh_init()
577 	pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1);  in a6xx_gmu_rpmh_init()
578 	pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 1, 0xa5a4a3a2);  in a6xx_gmu_rpmh_init()
579 	pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 2, 0x8382a6e0);  in a6xx_gmu_rpmh_init()
580 	pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 3, 0xbce3e284);  in a6xx_gmu_rpmh_init()
581 	pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 4, 0x002081fc);  in a6xx_gmu_rpmh_init()
585 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK, 0);  in a6xx_gmu_rpmh_init()
586 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CONTROL, 0);  in a6xx_gmu_rpmh_init()
587 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID, 0x10108);  in a6xx_gmu_rpmh_init()
588 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR, 0x30010);  in a6xx_gmu_rpmh_init()
590 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 4, 0x10108);  in a6xx_gmu_rpmh_init()
591 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000);  in a6xx_gmu_rpmh_init()
592 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0);  in a6xx_gmu_rpmh_init()
594 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108);  in a6xx_gmu_rpmh_init()
596 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0);  in a6xx_gmu_rpmh_init()
599 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0);  in a6xx_gmu_rpmh_init()
600 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CONTROL, 0);  in a6xx_gmu_rpmh_init()
601 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID, 0x10108);  in a6xx_gmu_rpmh_init()
602 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR, 0x30010);  in a6xx_gmu_rpmh_init()
605 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108);  in a6xx_gmu_rpmh_init()
606 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000);  in a6xx_gmu_rpmh_init()
609 		pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x2);  in a6xx_gmu_rpmh_init()
611 		pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3);  in a6xx_gmu_rpmh_init()
612 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108);  in a6xx_gmu_rpmh_init()
614 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3);  in a6xx_gmu_rpmh_init()
618 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0);  in a6xx_gmu_rpmh_init()
619 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001);  in a6xx_gmu_rpmh_init()
633  * hysteresis which is set at 0x1680 cycles (300 us).  The higher 16 bits are
634  * for the shorter hysteresis that happens after main - this is 0xa (.5 us)
637 #define GMU_PWR_COL_HYST 0x000a1680
643 	gmu_write(gmu, REG_A6XX_GMU_SYS_BUS_CONFIG, 0x1);  in a6xx_gmu_power_config()
644 	gmu_write(gmu, REG_A6XX_GMU_ICACHE_CONFIG, 0x1);  in a6xx_gmu_power_config()
645 	gmu_write(gmu, REG_A6XX_GMU_DCACHE_CONFIG, 0x1);  in a6xx_gmu_power_config()
647 	gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9c40400);  in a6xx_gmu_power_config()
653 		gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0,  in a6xx_gmu_power_config()
660 		gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0,  in a6xx_gmu_power_config()
666 	gmu_rmw(gmu, REG_A6XX_GMU_RPMH_CTRL, 0,  in a6xx_gmu_power_config()
706 	u32 itcm_base = 0x00000000;  in a6xx_gmu_fw_load()
707 	u32 dtcm_base = 0x00040000;  in a6xx_gmu_fw_load()
710 		dtcm_base = 0x10004000;  in a6xx_gmu_fw_load()
714 		if (fw_image->size > 0x8000) {  in a6xx_gmu_fw_load()
722 		return 0;  in a6xx_gmu_fw_load()
729 		if (blk->size == 0)  in a6xx_gmu_fw_load()
746 				"failed to match fw block (addr=%.8x size=%d data[0]=%.8x)\n",  in a6xx_gmu_fw_load()
747 				blk->addr, blk->size, blk->data[0]);  in a6xx_gmu_fw_load()
751 	return 0;  in a6xx_gmu_fw_load()
794 	gmu_write(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, 0);  in a6xx_gmu_fw_start()
795 	gmu_write(gmu, REG_A6XX_GMU_CM3_BOOT_CONFIG, 0x02);  in a6xx_gmu_fw_start()
802 		(1 << 31) | (0xa << 18) | (0xa0));  in a6xx_gmu_fw_start()
841 	return 0;  in a6xx_gmu_fw_start()
857 	gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~0);  in a6xx_gmu_irq_disable()
858 	gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~0);  in a6xx_gmu_irq_disable()
876 #define GBIF_CLIENT_HALT_MASK             BIT(0)
884 		gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0xf);  in a6xx_bus_clear_pending_transactions()
886 								0xf) == 0xf);  in a6xx_bus_clear_pending_transactions()
887 		gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0);  in a6xx_bus_clear_pending_transactions()
907 	gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0);  in a6xx_bus_clear_pending_transactions()
948 	gmu->freq = 0; /* so a6xx_gmu_set_freq() doesn't exit early */  in a6xx_gmu_set_initial_freq()
974 		return 0;  in a6xx_gmu_resume()
1003 	gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0);  in a6xx_gmu_resume()
1030 	gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, ~0);  in a6xx_gmu_resume()
1077 	if (val != 0xf) {  in a6xx_gmu_shutdown()
1107 				"Unable to slumber GMU: status = 0%x/0%x\n",  in a6xx_gmu_shutdown()
1131 		return 0;  in a6xx_gmu_stop()
1157 	return 0;  in a6xx_gmu_stop()
1185 		range_start = 0x60000000 + PAGE_SIZE; /* skip dummy page */  in a6xx_gmu_memory_alloc()
1186 		range_end = 0x80000000;  in a6xx_gmu_memory_alloc()
1211 	return 0;  in a6xx_gmu_memory_alloc()
1224 	gmu->aspace = msm_gem_address_space_create(mmu, "gmu", 0x0, 0x80000000);  in a6xx_gmu_memory_probe()
1230 	return 0;  in a6xx_gmu_memory_probe()
1241 		return 0;  in a6xx_gmu_get_arc_level()
1245 		return 0;  in a6xx_gmu_get_arc_level()
1281 	for (i = 0; i < freqs_count; i++) {  in a6xx_gmu_rpmh_arc_votes_init()
1282 		u8 pindex = 0, sindex = 0;  in a6xx_gmu_rpmh_arc_votes_init()
1286 		for (j = 0; j < pri_count; j++) {  in a6xx_gmu_rpmh_arc_votes_init()
1298 			for (j = 0; j < pri_count; j++)  in a6xx_gmu_rpmh_arc_votes_init()
1309 		for (j = 0; j < sec_count; j++) {  in a6xx_gmu_rpmh_arc_votes_init()
1319 		votes[i] = ((pri[pindex] & 0xffff) << 16) |  in a6xx_gmu_rpmh_arc_votes_init()
1323 	return 0;  in a6xx_gmu_rpmh_arc_votes_init()
1355 	int i, index = 0;  in a6xx_gmu_build_freq_table()
1368 	freqs[index++] = 0;  in a6xx_gmu_build_freq_table()
1370 	for (i = 0; i < count; i++) {  in a6xx_gmu_build_freq_table()
1388 	int ret = 0;  in a6xx_gmu_pwrlevels_probe()
1431 	return 0;  in a6xx_gmu_clocks_probe()
1546 					    0x60400000, "debug");  in a6xx_gmu_init()
1555 				    0x60000000, "dummy");  in a6xx_gmu_init()
1562 			SZ_16M - SZ_16K, 0x04000, "icache");  in a6xx_gmu_init()
1573 			SZ_256K - SZ_16K, 0x04000, "icache");  in a6xx_gmu_init()
1578 			SZ_256K - SZ_16K, 0x44000, "dcache");  in a6xx_gmu_init()
1586 		ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_16K, 0, "debug");  in a6xx_gmu_init()
1592 	ret = a6xx_gmu_memory_alloc(gmu, &gmu->hfi, SZ_16K, 0, "hfi");  in a6xx_gmu_init()
1597 	ret = a6xx_gmu_memory_alloc(gmu, &gmu->log, SZ_4K, 0, "log");  in a6xx_gmu_init()
1613 		gmu->rscc = gmu->mmio + 0x23000;  in a6xx_gmu_init()
1620 	if (gmu->hfi_irq < 0 || gmu->gmu_irq < 0)  in a6xx_gmu_init()
1637 	return 0;  in a6xx_gmu_init()