52 	TILE6_LINEAR = 0,
194 	DEPTH6_NONE = 0,
293 	PERF_CP_ALWAYS_COUNT = 0,
346 	PERF_RBBM_ALWAYS_COUNT = 0,
363 	PERF_PC_BUSY_CYCLES = 0,
408 	PERF_VFD_BUSY_CYCLES = 0,
434 	PERF_HLSQ_BUSY_CYCLES = 0,
458 	PERF_VPC_BUSY_CYCLES = 0,
489 	PERF_TSE_BUSY_CYCLES = 0,
512 	PERF_RAS_BUSY_CYCLES = 0,
528 	PERF_UCHE_BUSY_CYCLES = 0,
571 	PERF_TP_BUSY_CYCLES = 0,
631 	PERF_SP_BUSY_CYCLES = 0,
719 	PERF_RB_BUSY_CYCLES = 0,
770 	PERF_VSC_BUSY_CYCLES = 0,
778 	PERF_CCU_BUSY_CYCLES = 0,
810 	PERF_LRZ_BUSY_CYCLES = 0,
841 	PERF_CMPDECMP_STALL_CYCLES_ARB = 0,
891 	R2D_RAW = 0,
895 	A6XX_EARLY_Z = 0,
901 	DIST_SCREEN_COORD = 0,
906 	NO_FLUSH = 0,
912 	TYPE_TILED = 0,
917 	LR_TB = 0,
924 	RENDERING_PASS = 0,
929 	BUFFERS_IN_GMEM = 0,
934 	FRAGCOORD_CENTER = 0,
939 	ROTATE_0 = 0,
948 	TESS_EQUAL = 0,
954 	TESS_POINTS = 0,
961 	THREAD64 = 0,
970 	A6XX_TEX_NEAREST = 0,
977 	A6XX_TEX_REPEAT = 0,
985 	A6XX_TEX_ANISO_1 = 0,
993 	A6XX_REDUCTION_MODE_AVERAGE = 0,
999 	A6XX_TEX_X = 0,
1008 	A6XX_TEX_1D = 0,
1015 #define A6XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE			0x00000001
1016 #define A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR			0x00000002
1017 #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW	0x00000040
1018 #define A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR			0x00000080
1019 #define A6XX_RBBM_INT_0_MASK_CP_SW				0x00000100
1020 #define A6XX_RBBM_INT_0_MASK_CP_HW_ERROR			0x00000200
1021 #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS		0x00000400
1022 #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS		0x00000800
1023 #define A6XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS			0x00001000
1024 #define A6XX_RBBM_INT_0_MASK_CP_IB2				0x00002000
1025 #define A6XX_RBBM_INT_0_MASK_CP_IB1				0x00004000
1026 #define A6XX_RBBM_INT_0_MASK_CP_RB				0x00008000
1027 #define A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS			0x00020000
1028 #define A6XX_RBBM_INT_0_MASK_CP_WT_DONE_TS			0x00040000
1029 #define A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS			0x00100000
1030 #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW		0x00400000
1031 #define A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT			0x00800000
1032 #define A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS			0x01000000
1033 #define A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR			0x02000000
1034 #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_0			0x04000000
1035 #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_1			0x08000000
1036 #define A6XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ			0x40000000
1037 #define A6XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG			0x80000000
1038 #define A6XX_CP_INT_CP_OPCODE_ERROR				0x00000001
1039 #define A6XX_CP_INT_CP_UCODE_ERROR				0x00000002
1040 #define A6XX_CP_INT_CP_HW_FAULT_ERROR				0x00000004
1041 #define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR		0x00000010
1042 #define A6XX_CP_INT_CP_AHB_ERROR				0x00000020
1043 #define A6XX_CP_INT_CP_VSD_PARITY_ERROR				0x00000040
1044 #define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR			0x00000080
1045 #define REG_A6XX_CP_RB_BASE					0x00000800
1047 #define REG_A6XX_CP_RB_BASE_HI					0x00000801
1049 #define REG_A6XX_CP_RB_CNTL					0x00000802
1051 #define REG_A6XX_CP_RB_RPTR_ADDR_LO				0x00000804
1053 #define REG_A6XX_CP_RB_RPTR_ADDR_HI				0x00000805
1055 #define REG_A6XX_CP_RB_RPTR					0x00000806
1057 #define REG_A6XX_CP_RB_WPTR					0x00000807
1059 #define REG_A6XX_CP_SQE_CNTL					0x00000808
1061 #define REG_A6XX_CP_CP2GMU_STATUS				0x00000812
1062 #define A6XX_CP_CP2GMU_STATUS_IFPC				0x00000001
1064 #define REG_A6XX_CP_HW_FAULT					0x00000821
1066 #define REG_A6XX_CP_INTERRUPT_STATUS				0x00000823
1068 #define REG_A6XX_CP_PROTECT_STATUS				0x00000824
1070 #define REG_A6XX_CP_SQE_INSTR_BASE				0x00000830
1072 #define REG_A6XX_CP_MISC_CNTL					0x00000840
1074 #define REG_A6XX_CP_APRIV_CNTL					0x00000844
1076 #define REG_A6XX_CP_ROQ_THRESHOLDS_1				0x000008c1
1077 #define A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__MASK			0x000000ff
1078 #define A6XX_CP_ROQ_THRESHOLDS_1_RB_LO__SHIFT			0
1083 #define A6XX_CP_ROQ_THRESHOLDS_1_RB_HI__MASK			0x0000ff00
1089 #define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK		0x00ff0000
1095 #define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK		0xff000000
1102 #define REG_A6XX_CP_ROQ_THRESHOLDS_2				0x000008c2
1103 #define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK		0x000001ff
1104 #define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT		0
1109 #define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK			0xffff0000
1116 #define REG_A6XX_CP_MEM_POOL_SIZE				0x000008c3
1118 #define REG_A6XX_CP_CHICKEN_DBG					0x00000841
1120 #define REG_A6XX_CP_ADDR_MODE_CNTL				0x00000842
1122 #define REG_A6XX_CP_DBG_ECO_CNTL				0x00000843
1124 #define REG_A6XX_CP_PROTECT_CNTL				0x0000084f
1126 static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; }  in REG_A6XX_CP_SCRATCH()
1128 static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000883 + 0x1*i0; }  in REG_A6XX_CP_SCRATCH_REG()
1130 static inline uint32_t REG_A6XX_CP_PROTECT(uint32_t i0) { return 0x00000850 + 0x1*i0; }  in REG_A6XX_CP_PROTECT()
1132 static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000850 + 0x1*i0; }  in REG_A6XX_CP_PROTECT_REG()
1133 #define A6XX_CP_PROTECT_REG_BASE_ADDR__MASK			0x0003ffff
1134 #define A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT			0
1139 #define A6XX_CP_PROTECT_REG_MASK_LEN__MASK			0x7ffc0000
1145 #define A6XX_CP_PROTECT_REG_READ				0x80000000
1147 #define REG_A6XX_CP_CONTEXT_SWITCH_CNTL				0x000008a0
1149 #define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO			0x000008a1
1151 #define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI			0x000008a2
1153 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO	0x000008a3
1155 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI	0x000008a4
1157 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO	0x000008a5
1159 #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI	0x000008a6
1161 #define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO	0x000008a7
1163 #define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI	0x000008a8
1165 static inline uint32_t REG_A6XX_CP_PERFCTR_CP_SEL(uint32_t i0) { return 0x000008d0 + 0x1*i0; }  in REG_A6XX_CP_PERFCTR_CP_SEL()
1167 #define REG_A6XX_CP_CRASH_SCRIPT_BASE_LO			0x00000900
1169 #define REG_A6XX_CP_CRASH_SCRIPT_BASE_HI			0x00000901
1171 #define REG_A6XX_CP_CRASH_DUMP_CNTL				0x00000902
1173 #define REG_A6XX_CP_CRASH_DUMP_STATUS				0x00000903
1175 #define REG_A6XX_CP_SQE_STAT_ADDR				0x00000908
1177 #define REG_A6XX_CP_SQE_STAT_DATA				0x00000909
1179 #define REG_A6XX_CP_DRAW_STATE_ADDR				0x0000090a
1181 #define REG_A6XX_CP_DRAW_STATE_DATA				0x0000090b
1183 #define REG_A6XX_CP_ROQ_DBG_ADDR				0x0000090c
1185 #define REG_A6XX_CP_ROQ_DBG_DATA				0x0000090d
1187 #define REG_A6XX_CP_MEM_POOL_DBG_ADDR				0x0000090e
1189 #define REG_A6XX_CP_MEM_POOL_DBG_DATA				0x0000090f
1191 #define REG_A6XX_CP_SQE_UCODE_DBG_ADDR				0x00000910
1193 #define REG_A6XX_CP_SQE_UCODE_DBG_DATA				0x00000911
1195 #define REG_A6XX_CP_IB1_BASE					0x00000928
1197 #define REG_A6XX_CP_IB1_BASE_HI					0x00000929
1199 #define REG_A6XX_CP_IB1_REM_SIZE				0x0000092a
1201 #define REG_A6XX_CP_IB2_BASE					0x0000092b
1203 #define REG_A6XX_CP_IB2_BASE_HI					0x0000092c
1205 #define REG_A6XX_CP_IB2_REM_SIZE				0x0000092d
1207 #define REG_A6XX_CP_SDS_BASE					0x0000092e
1209 #define REG_A6XX_CP_SDS_BASE_HI					0x0000092f
1211 #define REG_A6XX_CP_SDS_REM_SIZE				0x00000930
1213 #define REG_A6XX_CP_MRB_BASE					0x00000931
1215 #define REG_A6XX_CP_MRB_BASE_HI					0x00000932
1217 #define REG_A6XX_CP_MRB_REM_SIZE				0x00000933
1219 #define REG_A6XX_CP_VSD_BASE					0x00000934
1221 #define REG_A6XX_CP_VSD_BASE_HI					0x00000935
1223 #define REG_A6XX_CP_MRB_DWORDS					0x00000946
1225 #define REG_A6XX_CP_VSD_DWORDS					0x00000947
1227 #define REG_A6XX_CP_CSQ_IB1_STAT				0x00000949
1228 #define A6XX_CP_CSQ_IB1_STAT_REM__MASK				0xffff0000
1235 #define REG_A6XX_CP_CSQ_IB2_STAT				0x0000094a
1236 #define A6XX_CP_CSQ_IB2_STAT_REM__MASK				0xffff0000
1243 #define REG_A6XX_CP_MRQ_MRB_STAT				0x0000094c
1244 #define A6XX_CP_MRQ_MRB_STAT_REM__MASK				0xffff0000
1251 #define REG_A6XX_CP_ALWAYS_ON_COUNTER_LO			0x00000980
1253 #define REG_A6XX_CP_ALWAYS_ON_COUNTER_HI			0x00000981
1255 #define REG_A6XX_CP_AHB_CNTL					0x0000098d
1257 #define REG_A6XX_CP_APERTURE_CNTL_HOST				0x00000a00
1259 #define REG_A6XX_CP_APERTURE_CNTL_CD				0x00000a03
1261 #define REG_A6XX_CP_LPAC_PROG_FIFO_SIZE				0x00000b34
1263 #define REG_A6XX_CP_LPAC_SQE_INSTR_BASE				0x00000b82
1265 #define REG_A6XX_VSC_ADDR_MODE_CNTL				0x00000c01
1267 #define REG_A6XX_RBBM_INT_0_STATUS				0x00000201
1269 #define REG_A6XX_RBBM_STATUS					0x00000210
1270 #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB			0x00800000
1271 #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP			0x00400000
1272 #define A6XX_RBBM_STATUS_HLSQ_BUSY				0x00200000
1273 #define A6XX_RBBM_STATUS_VSC_BUSY				0x00100000
1274 #define A6XX_RBBM_STATUS_TPL1_BUSY				0x00080000
1275 #define A6XX_RBBM_STATUS_SP_BUSY				0x00040000
1276 #define A6XX_RBBM_STATUS_UCHE_BUSY				0x00020000
1277 #define A6XX_RBBM_STATUS_VPC_BUSY				0x00010000
1278 #define A6XX_RBBM_STATUS_VFD_BUSY				0x00008000
1279 #define A6XX_RBBM_STATUS_TESS_BUSY				0x00004000
1280 #define A6XX_RBBM_STATUS_PC_VSD_BUSY				0x00002000
1281 #define A6XX_RBBM_STATUS_PC_DCALL_BUSY				0x00001000
1282 #define A6XX_RBBM_STATUS_COM_DCOM_BUSY				0x00000800
1283 #define A6XX_RBBM_STATUS_LRZ_BUSY				0x00000400
1284 #define A6XX_RBBM_STATUS_A2D_BUSY				0x00000200
1285 #define A6XX_RBBM_STATUS_CCU_BUSY				0x00000100
1286 #define A6XX_RBBM_STATUS_RB_BUSY				0x00000080
1287 #define A6XX_RBBM_STATUS_RAS_BUSY				0x00000040
1288 #define A6XX_RBBM_STATUS_TSE_BUSY				0x00000020
1289 #define A6XX_RBBM_STATUS_VBIF_BUSY				0x00000010
1290 #define A6XX_RBBM_STATUS_GFX_DBGC_BUSY				0x00000008
1291 #define A6XX_RBBM_STATUS_CP_BUSY				0x00000004
1292 #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CP_MASTER			0x00000002
1293 #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER			0x00000001
1295 #define REG_A6XX_RBBM_STATUS3					0x00000213
1296 #define A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT			0x01000000
1298 #define REG_A6XX_RBBM_VBIF_GX_RESET_STATUS			0x00000215
1300 static inline uint32_t REG_A6XX_RBBM_PERFCTR_CP(uint32_t i0) { return 0x00000400 + 0x2*i0; }  in REG_A6XX_RBBM_PERFCTR_CP()
1302 static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM(uint32_t i0) { return 0x0000041c + 0x2*i0; }  in REG_A6XX_RBBM_PERFCTR_RBBM()
1304 static inline uint32_t REG_A6XX_RBBM_PERFCTR_PC(uint32_t i0) { return 0x00000424 + 0x2*i0; }  in REG_A6XX_RBBM_PERFCTR_PC()
1306 static inline uint32_t REG_A6XX_RBBM_PERFCTR_VFD(uint32_t i0) { return 0x00000434 + 0x2*i0; }  in REG_A6XX_RBBM_PERFCTR_VFD()
1308 static inline uint32_t REG_A6XX_RBBM_PERFCTR_HLSQ(uint32_t i0) { return 0x00000444 + 0x2*i0; }  in REG_A6XX_RBBM_PERFCTR_HLSQ()
1310 static inline uint32_t REG_A6XX_RBBM_PERFCTR_VPC(uint32_t i0) { return 0x00000450 + 0x2*i0; }  in REG_A6XX_RBBM_PERFCTR_VPC()
1312 static inline uint32_t REG_A6XX_RBBM_PERFCTR_CCU(uint32_t i0) { return 0x0000045c + 0x2*i0; }  in REG_A6XX_RBBM_PERFCTR_CCU()
1314 static inline uint32_t REG_A6XX_RBBM_PERFCTR_TSE(uint32_t i0) { return 0x00000466 + 0x2*i0; }  in REG_A6XX_RBBM_PERFCTR_TSE()
1316 static inline uint32_t REG_A6XX_RBBM_PERFCTR_RAS(uint32_t i0) { return 0x0000046e + 0x2*i0; }  in REG_A6XX_RBBM_PERFCTR_RAS()
1318 static inline uint32_t REG_A6XX_RBBM_PERFCTR_UCHE(uint32_t i0) { return 0x00000476 + 0x2*i0; }  in REG_A6XX_RBBM_PERFCTR_UCHE()
1320 static inline uint32_t REG_A6XX_RBBM_PERFCTR_TP(uint32_t i0) { return 0x0000048e + 0x2*i0; }  in REG_A6XX_RBBM_PERFCTR_TP()
1322 static inline uint32_t REG_A6XX_RBBM_PERFCTR_SP(uint32_t i0) { return 0x000004a6 + 0x2*i0; }  in REG_A6XX_RBBM_PERFCTR_SP()
1324 static inline uint32_t REG_A6XX_RBBM_PERFCTR_RB(uint32_t i0) { return 0x000004d6 + 0x2*i0; }  in REG_A6XX_RBBM_PERFCTR_RB()
1326 static inline uint32_t REG_A6XX_RBBM_PERFCTR_VSC(uint32_t i0) { return 0x000004e6 + 0x2*i0; }  in REG_A6XX_RBBM_PERFCTR_VSC()
1328 static inline uint32_t REG_A6XX_RBBM_PERFCTR_LRZ(uint32_t i0) { return 0x000004ea + 0x2*i0; }  in REG_A6XX_RBBM_PERFCTR_LRZ()
1330 static inline uint32_t REG_A6XX_RBBM_PERFCTR_CMP(uint32_t i0) { return 0x000004f2 + 0x2*i0; }  in REG_A6XX_RBBM_PERFCTR_CMP()
1332 #define REG_A6XX_RBBM_PERFCTR_CNTL				0x00000500
1334 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD0				0x00000501
1336 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD1				0x00000502
1338 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD2				0x00000503
1340 #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD3				0x00000504
1342 #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_LO			0x00000505
1344 #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI			0x00000506
1346 static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00000507 + 0x1*i0; }  in REG_A6XX_RBBM_PERFCTR_RBBM_SEL()
1348 #define REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED			0x0000050b
1350 #define REG_A6XX_RBBM_PERFCTR_SRAM_INIT_CMD			0x0000050e
1352 #define REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS			0x0000050f
1354 #define REG_A6XX_RBBM_ISDB_CNT					0x00000533
1356 #define REG_A6XX_RBBM_PRIMCTR_0_LO				0x00000540
1358 #define REG_A6XX_RBBM_PRIMCTR_0_HI				0x00000541
1360 #define REG_A6XX_RBBM_PRIMCTR_1_LO				0x00000542
1362 #define REG_A6XX_RBBM_PRIMCTR_1_HI				0x00000543
1364 #define REG_A6XX_RBBM_PRIMCTR_2_LO				0x00000544
1366 #define REG_A6XX_RBBM_PRIMCTR_2_HI				0x00000545
1368 #define REG_A6XX_RBBM_PRIMCTR_3_LO				0x00000546
1370 #define REG_A6XX_RBBM_PRIMCTR_3_HI				0x00000547
1372 #define REG_A6XX_RBBM_PRIMCTR_4_LO				0x00000548
1374 #define REG_A6XX_RBBM_PRIMCTR_4_HI				0x00000549
1376 #define REG_A6XX_RBBM_PRIMCTR_5_LO				0x0000054a
1378 #define REG_A6XX_RBBM_PRIMCTR_5_HI				0x0000054b
1380 #define REG_A6XX_RBBM_PRIMCTR_6_LO				0x0000054c
1382 #define REG_A6XX_RBBM_PRIMCTR_6_HI				0x0000054d
1384 #define REG_A6XX_RBBM_PRIMCTR_7_LO				0x0000054e
1386 #define REG_A6XX_RBBM_PRIMCTR_7_HI				0x0000054f
1388 #define REG_A6XX_RBBM_PRIMCTR_8_LO				0x00000550
1390 #define REG_A6XX_RBBM_PRIMCTR_8_HI				0x00000551
1392 #define REG_A6XX_RBBM_PRIMCTR_9_LO				0x00000552
1394 #define REG_A6XX_RBBM_PRIMCTR_9_HI				0x00000553
1396 #define REG_A6XX_RBBM_PRIMCTR_10_LO				0x00000554
1398 #define REG_A6XX_RBBM_PRIMCTR_10_HI				0x00000555
1400 #define REG_A6XX_RBBM_SECVID_TRUST_CNTL				0x0000f400
1402 #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO		0x0000f800
1404 #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI		0x0000f801
1406 #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE			0x0000f802
1408 #define REG_A6XX_RBBM_SECVID_TSB_CNTL				0x0000f803
1410 #define REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL			0x0000f810
1412 #define REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL			0x00000010
1414 #define REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL			0x00000011
1416 #define REG_A6XX_RBBM_GBIF_HALT					0x00000016
1418 #define REG_A6XX_RBBM_GBIF_HALT_ACK				0x00000017
1420 #define REG_A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD			0x0000001c
1421 #define A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD_WAIT_GPU_IDLE		0x00000001
1423 #define REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL			0x0000001f
1425 #define REG_A6XX_RBBM_INT_CLEAR_CMD				0x00000037
1427 #define REG_A6XX_RBBM_INT_0_MASK				0x00000038
1429 #define REG_A6XX_RBBM_SP_HYST_CNT				0x00000042
1431 #define REG_A6XX_RBBM_SW_RESET_CMD				0x00000043
1433 #define REG_A6XX_RBBM_RAC_THRESHOLD_CNT				0x00000044
1435 #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD			0x00000045
1437 #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2			0x00000046
1439 #define REG_A6XX_RBBM_CLOCK_CNTL				0x000000ae
1441 #define REG_A6XX_RBBM_CLOCK_CNTL_SP0				0x000000b0
1443 #define REG_A6XX_RBBM_CLOCK_CNTL_SP1				0x000000b1
1445 #define REG_A6XX_RBBM_CLOCK_CNTL_SP2				0x000000b2
1447 #define REG_A6XX_RBBM_CLOCK_CNTL_SP3				0x000000b3
1449 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP0				0x000000b4
1451 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP1				0x000000b5
1453 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP2				0x000000b6
1455 #define REG_A6XX_RBBM_CLOCK_CNTL2_SP3				0x000000b7
1457 #define REG_A6XX_RBBM_CLOCK_DELAY_SP0				0x000000b8
1459 #define REG_A6XX_RBBM_CLOCK_DELAY_SP1				0x000000b9
1461 #define REG_A6XX_RBBM_CLOCK_DELAY_SP2				0x000000ba
1463 #define REG_A6XX_RBBM_CLOCK_DELAY_SP3				0x000000bb
1465 #define REG_A6XX_RBBM_CLOCK_HYST_SP0				0x000000bc
1467 #define REG_A6XX_RBBM_CLOCK_HYST_SP1				0x000000bd
1469 #define REG_A6XX_RBBM_CLOCK_HYST_SP2				0x000000be
1471 #define REG_A6XX_RBBM_CLOCK_HYST_SP3				0x000000bf
1473 #define REG_A6XX_RBBM_CLOCK_CNTL_TP0				0x000000c0
1475 #define REG_A6XX_RBBM_CLOCK_CNTL_TP1				0x000000c1
1477 #define REG_A6XX_RBBM_CLOCK_CNTL_TP2				0x000000c2
1479 #define REG_A6XX_RBBM_CLOCK_CNTL_TP3				0x000000c3
1481 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP0				0x000000c4
1483 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP1				0x000000c5
1485 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP2				0x000000c6
1487 #define REG_A6XX_RBBM_CLOCK_CNTL2_TP3				0x000000c7
1489 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP0				0x000000c8
1491 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP1				0x000000c9
1493 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP2				0x000000ca
1495 #define REG_A6XX_RBBM_CLOCK_CNTL3_TP3				0x000000cb
1497 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP0				0x000000cc
1499 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP1				0x000000cd
1501 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP2				0x000000ce
1503 #define REG_A6XX_RBBM_CLOCK_CNTL4_TP3				0x000000cf
1505 #define REG_A6XX_RBBM_CLOCK_DELAY_TP0				0x000000d0
1507 #define REG_A6XX_RBBM_CLOCK_DELAY_TP1				0x000000d1
1509 #define REG_A6XX_RBBM_CLOCK_DELAY_TP2				0x000000d2
1511 #define REG_A6XX_RBBM_CLOCK_DELAY_TP3				0x000000d3
1513 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP0				0x000000d4
1515 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP1				0x000000d5
1517 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP2				0x000000d6
1519 #define REG_A6XX_RBBM_CLOCK_DELAY2_TP3				0x000000d7
1521 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP0				0x000000d8
1523 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP1				0x000000d9
1525 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP2				0x000000da
1527 #define REG_A6XX_RBBM_CLOCK_DELAY3_TP3				0x000000db
1529 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP0				0x000000dc
1531 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP1				0x000000dd
1533 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP2				0x000000de
1535 #define REG_A6XX_RBBM_CLOCK_DELAY4_TP3				0x000000df
1537 #define REG_A6XX_RBBM_CLOCK_HYST_TP0				0x000000e0
1539 #define REG_A6XX_RBBM_CLOCK_HYST_TP1				0x000000e1
1541 #define REG_A6XX_RBBM_CLOCK_HYST_TP2				0x000000e2
1543 #define REG_A6XX_RBBM_CLOCK_HYST_TP3				0x000000e3
1545 #define REG_A6XX_RBBM_CLOCK_HYST2_TP0				0x000000e4
1547 #define REG_A6XX_RBBM_CLOCK_HYST2_TP1				0x000000e5
1549 #define REG_A6XX_RBBM_CLOCK_HYST2_TP2				0x000000e6
1551 #define REG_A6XX_RBBM_CLOCK_HYST2_TP3				0x000000e7
1553 #define REG_A6XX_RBBM_CLOCK_HYST3_TP0				0x000000e8
1555 #define REG_A6XX_RBBM_CLOCK_HYST3_TP1				0x000000e9
1557 #define REG_A6XX_RBBM_CLOCK_HYST3_TP2				0x000000ea
1559 #define REG_A6XX_RBBM_CLOCK_HYST3_TP3				0x000000eb
1561 #define REG_A6XX_RBBM_CLOCK_HYST4_TP0				0x000000ec
1563 #define REG_A6XX_RBBM_CLOCK_HYST4_TP1				0x000000ed
1565 #define REG_A6XX_RBBM_CLOCK_HYST4_TP2				0x000000ee
1567 #define REG_A6XX_RBBM_CLOCK_HYST4_TP3				0x000000ef
1569 #define REG_A6XX_RBBM_CLOCK_CNTL_RB0				0x000000f0
1571 #define REG_A6XX_RBBM_CLOCK_CNTL_RB1				0x000000f1
1573 #define REG_A6XX_RBBM_CLOCK_CNTL_RB2				0x000000f2
1575 #define REG_A6XX_RBBM_CLOCK_CNTL_RB3				0x000000f3
1577 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB0				0x000000f4
1579 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB1				0x000000f5
1581 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB2				0x000000f6
1583 #define REG_A6XX_RBBM_CLOCK_CNTL2_RB3				0x000000f7
1585 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU0				0x000000f8
1587 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU1				0x000000f9
1589 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU2				0x000000fa
1591 #define REG_A6XX_RBBM_CLOCK_CNTL_CCU3				0x000000fb
1593 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0			0x00000100
1595 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1			0x00000101
1597 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2			0x00000102
1599 #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3			0x00000103
1601 #define REG_A6XX_RBBM_CLOCK_CNTL_RAC				0x00000104
1603 #define REG_A6XX_RBBM_CLOCK_CNTL2_RAC				0x00000105
1605 #define REG_A6XX_RBBM_CLOCK_DELAY_RAC				0x00000106
1607 #define REG_A6XX_RBBM_CLOCK_HYST_RAC				0x00000107
1609 #define REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM			0x00000108
1611 #define REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM			0x00000109
1613 #define REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM			0x0000010a
1615 #define REG_A6XX_RBBM_CLOCK_CNTL_UCHE				0x0000010b
1617 #define REG_A6XX_RBBM_CLOCK_CNTL2_UCHE				0x0000010c
1619 #define REG_A6XX_RBBM_CLOCK_CNTL3_UCHE				0x0000010d
1621 #define REG_A6XX_RBBM_CLOCK_CNTL4_UCHE				0x0000010e
1623 #define REG_A6XX_RBBM_CLOCK_DELAY_UCHE				0x0000010f
1625 #define REG_A6XX_RBBM_CLOCK_HYST_UCHE				0x00000110
1627 #define REG_A6XX_RBBM_CLOCK_MODE_VFD				0x00000111
1629 #define REG_A6XX_RBBM_CLOCK_DELAY_VFD				0x00000112
1631 #define REG_A6XX_RBBM_CLOCK_HYST_VFD				0x00000113
1633 #define REG_A6XX_RBBM_CLOCK_MODE_GPC				0x00000114
1635 #define REG_A6XX_RBBM_CLOCK_DELAY_GPC				0x00000115
1637 #define REG_A6XX_RBBM_CLOCK_HYST_GPC				0x00000116
1639 #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2			0x00000117
1641 #define REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX				0x00000118
1643 #define REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX			0x00000119
1645 #define REG_A6XX_RBBM_CLOCK_HYST_GMU_GX				0x0000011a
1647 #define REG_A6XX_RBBM_CLOCK_MODE_HLSQ				0x0000011b
1649 #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ				0x0000011c
1651 #define REG_A6XX_RBBM_CLOCK_HYST_HLSQ				0x0000011d
1653 #define REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE			0x00000120
1655 #define REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE			0x00000121
1657 #define REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE			0x00000122
1659 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_A				0x00000600
1661 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_B				0x00000601
1663 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_C				0x00000602
1665 #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_D				0x00000603
1666 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK		0x000000ff
1667 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT		0
1672 #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK		0x0000ff00
1679 #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLT				0x00000604
1680 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK		0x0000003f
1681 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT		0
1686 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK			0x00007000
1692 #define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK			0xf0000000
1699 #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLM				0x00000605
1700 #define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK			0x0f000000
1707 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0				0x00000608
1709 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1				0x00000609
1711 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2				0x0000060a
1713 #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3				0x0000060b
1715 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0			0x0000060c
1717 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1			0x0000060d
1719 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2			0x0000060e
1721 #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3			0x0000060f
1723 #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0			0x00000610
1724 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK		0x0000000f
1725 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT		0
1730 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK		0x000000f0
1736 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK		0x00000f00
1742 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK		0x0000f000
1748 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK		0x000f0000
1754 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK		0x00f00000
1760 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK		0x0f000000
1766 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK		0xf0000000
1773 #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1			0x00000611
1774 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK		0x0000000f
1775 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT		0
1780 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK		0x000000f0
1786 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK		0x00000f00
1792 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK		0x0000f000
1798 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK		0x000f0000
1804 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK		0x00f00000
1810 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK		0x0f000000
1816 #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK		0xf0000000
1823 #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1			0x0000062f
1825 #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2			0x00000630
1827 static inline uint32_t REG_A6XX_VSC_PERFCTR_VSC_SEL(uint32_t i0) { return 0x00000cd8 + 0x1*i0; }  in REG_A6XX_VSC_PERFCTR_VSC_SEL()
1829 #define REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE			0x0000c800
1831 #define REG_A6XX_HLSQ_DBG_READ_SEL				0x0000d000
1833 #define REG_A6XX_UCHE_ADDR_MODE_CNTL				0x00000e00
1835 #define REG_A6XX_UCHE_MODE_CNTL					0x00000e01
1837 #define REG_A6XX_UCHE_WRITE_RANGE_MAX_LO			0x00000e05
1839 #define REG_A6XX_UCHE_WRITE_RANGE_MAX_HI			0x00000e06
1841 #define REG_A6XX_UCHE_WRITE_THRU_BASE_LO			0x00000e07
1843 #define REG_A6XX_UCHE_WRITE_THRU_BASE_HI			0x00000e08
1845 #define REG_A6XX_UCHE_TRAP_BASE_LO				0x00000e09
1847 #define REG_A6XX_UCHE_TRAP_BASE_HI				0x00000e0a
1849 #define REG_A6XX_UCHE_GMEM_RANGE_MIN_LO				0x00000e0b
1851 #define REG_A6XX_UCHE_GMEM_RANGE_MIN_HI				0x00000e0c
1853 #define REG_A6XX_UCHE_GMEM_RANGE_MAX_LO				0x00000e0d
1855 #define REG_A6XX_UCHE_GMEM_RANGE_MAX_HI				0x00000e0e
1857 #define REG_A6XX_UCHE_CACHE_WAYS				0x00000e17
1859 #define REG_A6XX_UCHE_FILTER_CNTL				0x00000e18
1861 #define REG_A6XX_UCHE_CLIENT_PF					0x00000e19
1862 #define A6XX_UCHE_CLIENT_PF_PERFSEL__MASK			0x000000ff
1863 #define A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT			0
1869 static inline uint32_t REG_A6XX_UCHE_PERFCTR_UCHE_SEL(uint32_t i0) { return 0x00000e1c + 0x1*i0; }  in REG_A6XX_UCHE_PERFCTR_UCHE_SEL()
1871 #define REG_A6XX_UCHE_CMDQ_CONFIG				0x00000e3c
1873 #define REG_A6XX_VBIF_VERSION					0x00003000
1875 #define REG_A6XX_VBIF_CLKON					0x00003001
1876 #define A6XX_VBIF_CLKON_FORCE_ON_TESTBUS			0x00000002
1878 #define REG_A6XX_VBIF_GATE_OFF_WRREQ_EN				0x0000302a
1880 #define REG_A6XX_VBIF_XIN_HALT_CTRL0				0x00003080
1882 #define REG_A6XX_VBIF_XIN_HALT_CTRL1				0x00003081
1884 #define REG_A6XX_VBIF_TEST_BUS_OUT_CTRL				0x00003084
1886 #define REG_A6XX_VBIF_TEST_BUS1_CTRL0				0x00003085
1888 #define REG_A6XX_VBIF_TEST_BUS1_CTRL1				0x00003086
1889 #define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK		0x0000000f
1890 #define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT		0
1896 #define REG_A6XX_VBIF_TEST_BUS2_CTRL0				0x00003087
1898 #define REG_A6XX_VBIF_TEST_BUS2_CTRL1				0x00003088
1899 #define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK		0x000001ff
1900 #define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT		0
1906 #define REG_A6XX_VBIF_TEST_BUS_OUT				0x0000308c
1908 #define REG_A6XX_VBIF_PERF_CNT_SEL0				0x000030d0
1910 #define REG_A6XX_VBIF_PERF_CNT_SEL1				0x000030d1
1912 #define REG_A6XX_VBIF_PERF_CNT_SEL2				0x000030d2
1914 #define REG_A6XX_VBIF_PERF_CNT_SEL3				0x000030d3
1916 #define REG_A6XX_VBIF_PERF_CNT_LOW0				0x000030d8
1918 #define REG_A6XX_VBIF_PERF_CNT_LOW1				0x000030d9
1920 #define REG_A6XX_VBIF_PERF_CNT_LOW2				0x000030da
1922 #define REG_A6XX_VBIF_PERF_CNT_LOW3				0x000030db
1924 #define REG_A6XX_VBIF_PERF_CNT_HIGH0				0x000030e0
1926 #define REG_A6XX_VBIF_PERF_CNT_HIGH1				0x000030e1
1928 #define REG_A6XX_VBIF_PERF_CNT_HIGH2				0x000030e2
1930 #define REG_A6XX_VBIF_PERF_CNT_HIGH3				0x000030e3
1932 #define REG_A6XX_VBIF_PERF_PWR_CNT_EN0				0x00003100
1934 #define REG_A6XX_VBIF_PERF_PWR_CNT_EN1				0x00003101
1936 #define REG_A6XX_VBIF_PERF_PWR_CNT_EN2				0x00003102
1938 #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW0				0x00003110
1940 #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW1				0x00003111
1942 #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW2				0x00003112
1944 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH0			0x00003118
1946 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH1			0x00003119
1948 #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2			0x0000311a
1950 #define REG_A6XX_GBIF_SCACHE_CNTL0				0x00003c01
1952 #define REG_A6XX_GBIF_SCACHE_CNTL1				0x00003c02
1954 #define REG_A6XX_GBIF_QSB_SIDE0					0x00003c03
1956 #define REG_A6XX_GBIF_QSB_SIDE1					0x00003c04
1958 #define REG_A6XX_GBIF_QSB_SIDE2					0x00003c05
1960 #define REG_A6XX_GBIF_QSB_SIDE3					0x00003c06
1962 #define REG_A6XX_GBIF_HALT					0x00003c45
1964 #define REG_A6XX_GBIF_HALT_ACK					0x00003c46
1966 #define REG_A6XX_GBIF_PERF_PWR_CNT_EN				0x00003cc0
1968 #define REG_A6XX_GBIF_PERF_CNT_SEL				0x00003cc2
1970 #define REG_A6XX_GBIF_PERF_PWR_CNT_SEL				0x00003cc3
1972 #define REG_A6XX_GBIF_PERF_CNT_LOW0				0x00003cc4
1974 #define REG_A6XX_GBIF_PERF_CNT_LOW1				0x00003cc5
1976 #define REG_A6XX_GBIF_PERF_CNT_LOW2				0x00003cc6
1978 #define REG_A6XX_GBIF_PERF_CNT_LOW3				0x00003cc7
1980 #define REG_A6XX_GBIF_PERF_CNT_HIGH0				0x00003cc8
1982 #define REG_A6XX_GBIF_PERF_CNT_HIGH1				0x00003cc9
1984 #define REG_A6XX_GBIF_PERF_CNT_HIGH2				0x00003cca
1986 #define REG_A6XX_GBIF_PERF_CNT_HIGH3				0x00003ccb
1988 #define REG_A6XX_GBIF_PWR_CNT_LOW0				0x00003ccc
1990 #define REG_A6XX_GBIF_PWR_CNT_LOW1				0x00003ccd
1992 #define REG_A6XX_GBIF_PWR_CNT_LOW2				0x00003cce
1994 #define REG_A6XX_GBIF_PWR_CNT_HIGH0				0x00003ccf
1996 #define REG_A6XX_GBIF_PWR_CNT_HIGH1				0x00003cd0
1998 #define REG_A6XX_GBIF_PWR_CNT_HIGH2				0x00003cd1
2000 #define REG_A6XX_VSC_DBG_ECO_CNTL				0x00000c00
2002 #define REG_A6XX_VSC_BIN_SIZE					0x00000c02
2003 #define A6XX_VSC_BIN_SIZE_WIDTH__MASK				0x000000ff
2004 #define A6XX_VSC_BIN_SIZE_WIDTH__SHIFT				0
2009 #define A6XX_VSC_BIN_SIZE_HEIGHT__MASK				0x0001ff00
2016 #define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS			0x00000c03
2018 #define REG_A6XX_VSC_BIN_COUNT					0x00000c06
2019 #define A6XX_VSC_BIN_COUNT_NX__MASK				0x000007fe
2025 #define A6XX_VSC_BIN_COUNT_NY__MASK				0x001ff800
2032 static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }  in REG_A6XX_VSC_PIPE_CONFIG()
2034 static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }  in REG_A6XX_VSC_PIPE_CONFIG_REG()
2035 #define A6XX_VSC_PIPE_CONFIG_REG_X__MASK			0x000003ff
2036 #define A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT			0
2041 #define A6XX_VSC_PIPE_CONFIG_REG_Y__MASK			0x000ffc00
2047 #define A6XX_VSC_PIPE_CONFIG_REG_W__MASK			0x03f00000
2053 #define A6XX_VSC_PIPE_CONFIG_REG_H__MASK			0xfc000000
2060 #define REG_A6XX_VSC_PRIM_STRM_ADDRESS				0x00000c30
2062 #define REG_A6XX_VSC_PRIM_STRM_PITCH				0x00000c32
2064 #define REG_A6XX_VSC_PRIM_STRM_LIMIT				0x00000c33
2066 #define REG_A6XX_VSC_DRAW_STRM_ADDRESS				0x00000c34
2068 #define REG_A6XX_VSC_DRAW_STRM_PITCH				0x00000c36
2070 #define REG_A6XX_VSC_DRAW_STRM_LIMIT				0x00000c37
2072 static inline uint32_t REG_A6XX_VSC_STATE(uint32_t i0) { return 0x00000c38 + 0x1*i0; }  in REG_A6XX_VSC_STATE()
2074 static inline uint32_t REG_A6XX_VSC_STATE_REG(uint32_t i0) { return 0x00000c38 + 0x1*i0; }  in REG_A6XX_VSC_STATE_REG()
2076 static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE(uint32_t i0) { return 0x00000c58 + 0x1*i0; }  in REG_A6XX_VSC_PRIM_STRM_SIZE()
2078 static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE_REG(uint32_t i0) { return 0x00000c58 + 0x1*i0; }  in REG_A6XX_VSC_PRIM_STRM_SIZE_REG()
2080 static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE(uint32_t i0) { return 0x00000c78 + 0x1*i0; }  in REG_A6XX_VSC_DRAW_STRM_SIZE()
2082 static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE_REG(uint32_t i0) { return 0x00000c78 + 0x1*i0; }  in REG_A6XX_VSC_DRAW_STRM_SIZE_REG()
2084 #define REG_A6XX_UCHE_UNKNOWN_0E12				0x00000e12
2086 #define REG_A6XX_GRAS_CL_CNTL					0x00008000
2087 #define A6XX_GRAS_CL_CNTL_CLIP_DISABLE				0x00000001
2088 #define A6XX_GRAS_CL_CNTL_ZNEAR_CLIP_DISABLE			0x00000002
2089 #define A6XX_GRAS_CL_CNTL_ZFAR_CLIP_DISABLE			0x00000004
2090 #define A6XX_GRAS_CL_CNTL_UNK5					0x00000020
2091 #define A6XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z			0x00000040
2092 #define A6XX_GRAS_CL_CNTL_VP_CLIP_CODE_IGNORE			0x00000080
2093 #define A6XX_GRAS_CL_CNTL_VP_XFORM_DISABLE			0x00000100
2094 #define A6XX_GRAS_CL_CNTL_PERSP_DIVISION_DISABLE		0x00000200
2096 #define REG_A6XX_GRAS_VS_CL_CNTL				0x00008001
2097 #define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK			0x000000ff
2098 #define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT			0
2103 #define A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK			0x0000ff00
2110 #define REG_A6XX_GRAS_DS_CL_CNTL				0x00008002
2111 #define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK			0x000000ff
2112 #define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT			0
2117 #define A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK			0x0000ff00
2124 #define REG_A6XX_GRAS_GS_CL_CNTL				0x00008003
2125 #define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK			0x000000ff
2126 #define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT			0
2131 #define A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK			0x0000ff00
2138 #define REG_A6XX_GRAS_MAX_LAYER_INDEX				0x00008004
2140 #define REG_A6XX_GRAS_CNTL					0x00008005
2141 #define A6XX_GRAS_CNTL_IJ_PERSP_PIXEL				0x00000001
2142 #define A6XX_GRAS_CNTL_IJ_PERSP_CENTROID			0x00000002
2143 #define A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE				0x00000004
2144 #define A6XX_GRAS_CNTL_IJ_LINEAR_PIXEL				0x00000008
2145 #define A6XX_GRAS_CNTL_IJ_LINEAR_CENTROID			0x00000010
2146 #define A6XX_GRAS_CNTL_IJ_LINEAR_SAMPLE				0x00000020
2147 #define A6XX_GRAS_CNTL_COORD_MASK__MASK				0x000003c0
2154 #define REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ			0x00008006
2155 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK		0x000001ff
2156 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT		0
2161 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK		0x0007fc00
2168 static inline uint32_t REG_A6XX_GRAS_CL_VPORT(uint32_t i0) { return 0x00008010 + 0x6*i0; }  in REG_A6XX_GRAS_CL_VPORT()
2170 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XOFFSET(uint32_t i0) { return 0x00008010 + 0x6*i0; }  in REG_A6XX_GRAS_CL_VPORT_XOFFSET()
2171 #define A6XX_GRAS_CL_VPORT_XOFFSET__MASK			0xffffffff
2172 #define A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT			0
2178 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XSCALE(uint32_t i0) { return 0x00008011 + 0x6*i0; }  in REG_A6XX_GRAS_CL_VPORT_XSCALE()
2179 #define A6XX_GRAS_CL_VPORT_XSCALE__MASK				0xffffffff
2180 #define A6XX_GRAS_CL_VPORT_XSCALE__SHIFT			0
2186 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YOFFSET(uint32_t i0) { return 0x00008012 + 0x6*i0; }  in REG_A6XX_GRAS_CL_VPORT_YOFFSET()
2187 #define A6XX_GRAS_CL_VPORT_YOFFSET__MASK			0xffffffff
2188 #define A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT			0
2194 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YSCALE(uint32_t i0) { return 0x00008013 + 0x6*i0; }  in REG_A6XX_GRAS_CL_VPORT_YSCALE()
2195 #define A6XX_GRAS_CL_VPORT_YSCALE__MASK				0xffffffff
2196 #define A6XX_GRAS_CL_VPORT_YSCALE__SHIFT			0
2202 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZOFFSET(uint32_t i0) { return 0x00008014 + 0x6*i0; }  in REG_A6XX_GRAS_CL_VPORT_ZOFFSET()
2203 #define A6XX_GRAS_CL_VPORT_ZOFFSET__MASK			0xffffffff
2204 #define A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT			0
2210 static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZSCALE(uint32_t i0) { return 0x00008015 + 0x6*i0; }  in REG_A6XX_GRAS_CL_VPORT_ZSCALE()
2211 #define A6XX_GRAS_CL_VPORT_ZSCALE__MASK				0xffffffff
2212 #define A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT			0
2218 static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP(uint32_t i0) { return 0x00008070 + 0x2*i0; }  in REG_A6XX_GRAS_CL_Z_CLAMP()
2220 static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MIN(uint32_t i0) { return 0x00008070 + 0x2*i0; }  in REG_A6XX_GRAS_CL_Z_CLAMP_MIN()
2221 #define A6XX_GRAS_CL_Z_CLAMP_MIN__MASK				0xffffffff
2222 #define A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT				0
2228 static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MAX(uint32_t i0) { return 0x00008071 + 0x2*i0; }  in REG_A6XX_GRAS_CL_Z_CLAMP_MAX()
2229 #define A6XX_GRAS_CL_Z_CLAMP_MAX__MASK				0xffffffff
2230 #define A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT				0
2236 #define REG_A6XX_GRAS_SU_CNTL					0x00008090
2237 #define A6XX_GRAS_SU_CNTL_CULL_FRONT				0x00000001
2238 #define A6XX_GRAS_SU_CNTL_CULL_BACK				0x00000002
2239 #define A6XX_GRAS_SU_CNTL_FRONT_CW				0x00000004
2240 #define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK			0x000007f8
2246 #define A6XX_GRAS_SU_CNTL_POLY_OFFSET				0x00000800
2247 #define A6XX_GRAS_SU_CNTL_UNK12__MASK				0x00001000
2253 #define A6XX_GRAS_SU_CNTL_LINE_MODE__MASK			0x00002000
2259 #define A6XX_GRAS_SU_CNTL_UNK15__MASK				0x00018000
2265 #define A6XX_GRAS_SU_CNTL_UNK17					0x00020000
2266 #define A6XX_GRAS_SU_CNTL_MULTIVIEW_ENABLE			0x00040000
2267 #define A6XX_GRAS_SU_CNTL_UNK19__MASK				0x00780000
2274 #define REG_A6XX_GRAS_SU_POINT_MINMAX				0x00008091
2275 #define A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK			0x0000ffff
2276 #define A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT			0
2281 #define A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK			0xffff0000
2288 #define REG_A6XX_GRAS_SU_POINT_SIZE				0x00008092
2289 #define A6XX_GRAS_SU_POINT_SIZE__MASK				0x0000ffff
2290 #define A6XX_GRAS_SU_POINT_SIZE__SHIFT				0
2296 #define REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL			0x00008094
2297 #define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK		0x00000003
2298 #define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT		0
2304 #define REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE			0x00008095
2305 #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK			0xffffffff
2306 #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT			0
2312 #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET			0x00008096
2313 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK			0xffffffff
2314 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT			0
2320 #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP		0x00008097
2321 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK		0xffffffff
2322 #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT		0
2328 #define REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO			0x00008098
2329 #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK	0x00000007
2330 #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT	0
2335 #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__MASK		0x00000008
2342 #define REG_A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL			0x00008099
2343 #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN	0x00000001
2344 #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__MASK	0x00000006
2350 #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_INNERCONSERVATIVERASEN	0x00000008
2351 #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__MASK		0x00000030
2358 #define REG_A6XX_GRAS_SU_PATH_RENDERING_CNTL			0x0000809a
2359 #define A6XX_GRAS_SU_PATH_RENDERING_CNTL_UNK0			0x00000001
2360 #define A6XX_GRAS_SU_PATH_RENDERING_CNTL_LINELENGTHEN		0x00000002
2362 #define REG_A6XX_GRAS_VS_LAYER_CNTL				0x0000809b
2363 #define A6XX_GRAS_VS_LAYER_CNTL_WRITES_LAYER			0x00000001
2364 #define A6XX_GRAS_VS_LAYER_CNTL_WRITES_VIEW			0x00000002
2366 #define REG_A6XX_GRAS_GS_LAYER_CNTL				0x0000809c
2367 #define A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER			0x00000001
2368 #define A6XX_GRAS_GS_LAYER_CNTL_WRITES_VIEW			0x00000002
2370 #define REG_A6XX_GRAS_DS_LAYER_CNTL				0x0000809d
2371 #define A6XX_GRAS_DS_LAYER_CNTL_WRITES_LAYER			0x00000001
2372 #define A6XX_GRAS_DS_LAYER_CNTL_WRITES_VIEW			0x00000002
2374 #define REG_A6XX_GRAS_SC_CNTL					0x000080a0
2375 #define A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__MASK		0x00000007
2376 #define A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__SHIFT		0
2381 #define A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__MASK		0x00000018
2387 #define A6XX_GRAS_SC_CNTL_RASTER_MODE__MASK			0x00000020
2393 #define A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__MASK		0x000000c0
2399 #define A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__MASK	0x00000100
2405 #define A6XX_GRAS_SC_CNTL_UNK9__MASK				0x00000e00
2411 #define A6XX_GRAS_SC_CNTL_EARLYVIZOUTEN				0x00001000
2413 #define REG_A6XX_GRAS_BIN_CONTROL				0x000080a1
2414 #define A6XX_GRAS_BIN_CONTROL_BINW__MASK			0x0000003f
2415 #define A6XX_GRAS_BIN_CONTROL_BINW__SHIFT			0
2420 #define A6XX_GRAS_BIN_CONTROL_BINH__MASK			0x00007f00
2426 #define A6XX_GRAS_BIN_CONTROL_RENDER_MODE__MASK			0x001c0000
2432 #define A6XX_GRAS_BIN_CONTROL_FORCE_LRZ_WRITE_DIS		0x00200000
2433 #define A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__MASK		0x00c00000
2439 #define A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK	0x07000000
2445 #define A6XX_GRAS_BIN_CONTROL_UNK27__MASK			0x08000000
2452 #define REG_A6XX_GRAS_RAS_MSAA_CNTL				0x000080a2
2453 #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK			0x00000003
2454 #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT			0
2459 #define A6XX_GRAS_RAS_MSAA_CNTL_UNK2__MASK			0x00000004
2465 #define A6XX_GRAS_RAS_MSAA_CNTL_UNK3__MASK			0x00000008
2472 #define REG_A6XX_GRAS_DEST_MSAA_CNTL				0x000080a3
2473 #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK			0x00000003
2474 #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT			0
2479 #define A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE			0x00000004
2481 #define REG_A6XX_GRAS_SAMPLE_CONFIG				0x000080a4
2482 #define A6XX_GRAS_SAMPLE_CONFIG_UNK0				0x00000001
2483 #define A6XX_GRAS_SAMPLE_CONFIG_LOCATION_ENABLE			0x00000002
2485 #define REG_A6XX_GRAS_SAMPLE_LOCATION_0				0x000080a5
2486 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK		0x0000000f
2487 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT		0
2492 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK		0x000000f0
2498 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK		0x00000f00
2504 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK		0x0000f000
2510 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK		0x000f0000
2516 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK		0x00f00000
2522 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK		0x0f000000
2528 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK		0xf0000000
2535 #define REG_A6XX_GRAS_SAMPLE_LOCATION_1				0x000080a6
2536 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK		0x0000000f
2537 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT		0
2542 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK		0x000000f0
2548 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK		0x00000f00
2554 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK		0x0000f000
2560 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK		0x000f0000
2566 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK		0x00f00000
2572 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK		0x0f000000
2578 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK		0xf0000000
2585 #define REG_A6XX_GRAS_UNKNOWN_80AF				0x000080af
2587 static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR(uint32_t i0) { return 0x000080b0 + 0x2*i0; }  in REG_A6XX_GRAS_SC_SCREEN_SCISSOR()
2589 static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL(uint32_t i0) { return 0x000080b0 + 0x2*i0…  in REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL()
2590 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK			0x0000ffff
2591 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT			0
2596 #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK			0xffff0000
2603 static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_BR(uint32_t i0) { return 0x000080b1 + 0x2*i0…  in REG_A6XX_GRAS_SC_SCREEN_SCISSOR_BR()
2604 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK			0x0000ffff
2605 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT			0
2610 #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK			0xffff0000
2617 static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR(uint32_t i0) { return 0x000080d0 + 0x2*i0;…  in REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR()
2619 static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(uint32_t i0) { return 0x000080d0 + 0x2*…  in REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL()
2620 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK		0x0000ffff
2621 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT		0
2626 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK		0xffff0000
2633 static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR(uint32_t i0) { return 0x000080d1 + 0x2*…  in REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR()
2634 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK		0x0000ffff
2635 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT		0
2640 #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK		0xffff0000
2647 #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL			0x000080f0
2648 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK			0x00003fff
2649 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT			0
2654 #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK			0x3fff0000
2661 #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_BR			0x000080f1
2662 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK			0x00003fff
2663 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT			0
2668 #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK			0x3fff0000
2675 #define REG_A6XX_GRAS_LRZ_CNTL					0x00008100
2676 #define A6XX_GRAS_LRZ_CNTL_ENABLE				0x00000001
2677 #define A6XX_GRAS_LRZ_CNTL_LRZ_WRITE				0x00000002
2678 #define A6XX_GRAS_LRZ_CNTL_GREATER				0x00000004
2679 #define A6XX_GRAS_LRZ_CNTL_FC_ENABLE				0x00000008
2680 #define A6XX_GRAS_LRZ_CNTL_Z_TEST_ENABLE			0x00000010
2681 #define A6XX_GRAS_LRZ_CNTL_Z_BOUNDS_ENABLE			0x00000020
2682 #define A6XX_GRAS_LRZ_CNTL_UNK6__MASK				0x000003c0
2689 #define REG_A6XX_GRAS_LRZ_PS_INPUT_CNTL				0x00008101
2690 #define A6XX_GRAS_LRZ_PS_INPUT_CNTL_SAMPLEID			0x00000001
2691 #define A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__MASK	0x00000006
2698 #define REG_A6XX_GRAS_LRZ_MRT_BUF_INFO_0			0x00008102
2699 #define A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__MASK		0x000000ff
2700 #define A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__SHIFT	0
2706 #define REG_A6XX_GRAS_LRZ_BUFFER_BASE				0x00008103
2707 #define A6XX_GRAS_LRZ_BUFFER_BASE__MASK				0xffffffff
2708 #define A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT			0
2714 #define REG_A6XX_GRAS_LRZ_BUFFER_PITCH				0x00008105
2715 #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK			0x000000ff
2716 #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT			0
2721 #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK		0x1ffffc00
2728 #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE		0x00008106
2729 #define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK		0xffffffff
2730 #define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT		0
2736 #define REG_A6XX_GRAS_SAMPLE_CNTL				0x00008109
2737 #define A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE			0x00000001
2739 #define REG_A6XX_GRAS_UNKNOWN_810A				0x0000810a
2740 #define A6XX_GRAS_UNKNOWN_810A_UNK0__MASK			0x000007ff
2741 #define A6XX_GRAS_UNKNOWN_810A_UNK0__SHIFT			0
2746 #define A6XX_GRAS_UNKNOWN_810A_UNK16__MASK			0x07ff0000
2752 #define A6XX_GRAS_UNKNOWN_810A_UNK28__MASK			0xf0000000
2759 #define REG_A6XX_GRAS_UNKNOWN_8110				0x00008110
2761 #define REG_A6XX_GRAS_2D_BLIT_CNTL				0x00008400
2762 #define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK			0x00000007
2763 #define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT			0
2768 #define A6XX_GRAS_2D_BLIT_CNTL_OVERWRITEEN			0x00000008
2769 #define A6XX_GRAS_2D_BLIT_CNTL_UNK4__MASK			0x00000070
2775 #define A6XX_GRAS_2D_BLIT_CNTL_SOLID_COLOR			0x00000080
2776 #define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK		0x0000ff00
2782 #define A6XX_GRAS_2D_BLIT_CNTL_SCISSOR				0x00010000
2783 #define A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK			0x00060000
2789 #define A6XX_GRAS_2D_BLIT_CNTL_D24S8				0x00080000
2790 #define A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK			0x00f00000
2796 #define A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK			0x1f000000
2802 #define A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__MASK		0x20000000
2809 #define REG_A6XX_GRAS_2D_SRC_TL_X				0x00008401
2811 #define REG_A6XX_GRAS_2D_SRC_BR_X				0x00008402
2813 #define REG_A6XX_GRAS_2D_SRC_TL_Y				0x00008403
2815 #define REG_A6XX_GRAS_2D_SRC_BR_Y				0x00008404
2817 #define REG_A6XX_GRAS_2D_DST_TL					0x00008405
2818 #define A6XX_GRAS_2D_DST_TL_X__MASK				0x00003fff
2819 #define A6XX_GRAS_2D_DST_TL_X__SHIFT				0
2824 #define A6XX_GRAS_2D_DST_TL_Y__MASK				0x3fff0000
2831 #define REG_A6XX_GRAS_2D_DST_BR					0x00008406
2832 #define A6XX_GRAS_2D_DST_BR_X__MASK				0x00003fff
2833 #define A6XX_GRAS_2D_DST_BR_X__SHIFT				0
2838 #define A6XX_GRAS_2D_DST_BR_Y__MASK				0x3fff0000
2845 #define REG_A6XX_GRAS_2D_UNKNOWN_8407				0x00008407
2847 #define REG_A6XX_GRAS_2D_UNKNOWN_8408				0x00008408
2849 #define REG_A6XX_GRAS_2D_UNKNOWN_8409				0x00008409
2851 #define REG_A6XX_GRAS_2D_RESOLVE_CNTL_1				0x0000840a
2852 #define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK			0x00003fff
2853 #define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT			0
2858 #define A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK			0x3fff0000
2865 #define REG_A6XX_GRAS_2D_RESOLVE_CNTL_2				0x0000840b
2866 #define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK			0x00003fff
2867 #define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT			0
2872 #define A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK			0x3fff0000
2879 #define REG_A6XX_GRAS_DBG_ECO_CNTL				0x00008600
2880 #define A6XX_GRAS_DBG_ECO_CNTL_UNK7				0x00000080
2881 #define A6XX_GRAS_DBG_ECO_CNTL_LRZCACHELOCKDIS			0x00000800
2883 #define REG_A6XX_GRAS_ADDR_MODE_CNTL				0x00008601
2885 static inline uint32_t REG_A6XX_GRAS_PERFCTR_TSE_SEL(uint32_t i0) { return 0x00008610 + 0x1*i0; }  in REG_A6XX_GRAS_PERFCTR_TSE_SEL()
2887 static inline uint32_t REG_A6XX_GRAS_PERFCTR_RAS_SEL(uint32_t i0) { return 0x00008614 + 0x1*i0; }  in REG_A6XX_GRAS_PERFCTR_RAS_SEL()
2889 static inline uint32_t REG_A6XX_GRAS_PERFCTR_LRZ_SEL(uint32_t i0) { return 0x00008618 + 0x1*i0; }  in REG_A6XX_GRAS_PERFCTR_LRZ_SEL()
2891 #define REG_A6XX_RB_BIN_CONTROL					0x00008800
2892 #define A6XX_RB_BIN_CONTROL_BINW__MASK				0x0000003f
2893 #define A6XX_RB_BIN_CONTROL_BINW__SHIFT				0
2898 #define A6XX_RB_BIN_CONTROL_BINH__MASK				0x00007f00
2904 #define A6XX_RB_BIN_CONTROL_RENDER_MODE__MASK			0x001c0000
2910 #define A6XX_RB_BIN_CONTROL_FORCE_LRZ_WRITE_DIS			0x00200000
2911 #define A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__MASK		0x00c00000
2917 #define A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK	0x07000000
2924 #define REG_A6XX_RB_RENDER_CNTL					0x00008801
2925 #define A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__MASK	0x00000038
2931 #define A6XX_RB_RENDER_CNTL_EARLYVIZOUTEN			0x00000040
2932 #define A6XX_RB_RENDER_CNTL_BINNING				0x00000080
2933 #define A6XX_RB_RENDER_CNTL_UNK8__MASK				0x00000700
2939 #define A6XX_RB_RENDER_CNTL_RASTER_MODE__MASK			0x00000100
2945 #define A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK		0x00000600
2951 #define A6XX_RB_RENDER_CNTL_CONSERVATIVERASEN			0x00000800
2952 #define A6XX_RB_RENDER_CNTL_INNERCONSERVATIVERASEN		0x00001000
2953 #define A6XX_RB_RENDER_CNTL_FLAG_DEPTH				0x00004000
2954 #define A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK			0x00ff0000
2961 #define REG_A6XX_RB_RAS_MSAA_CNTL				0x00008802
2962 #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK			0x00000003
2963 #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT			0
2968 #define A6XX_RB_RAS_MSAA_CNTL_UNK2__MASK			0x00000004
2974 #define A6XX_RB_RAS_MSAA_CNTL_UNK3__MASK			0x00000008
2981 #define REG_A6XX_RB_DEST_MSAA_CNTL				0x00008803
2982 #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK			0x00000003
2983 #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT			0
2988 #define A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE			0x00000004
2990 #define REG_A6XX_RB_SAMPLE_CONFIG				0x00008804
2991 #define A6XX_RB_SAMPLE_CONFIG_UNK0				0x00000001
2992 #define A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE			0x00000002
2994 #define REG_A6XX_RB_SAMPLE_LOCATION_0				0x00008805
2995 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK		0x0000000f
2996 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT		0
3001 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK		0x000000f0
3007 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK		0x00000f00
3013 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK		0x0000f000
3019 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK		0x000f0000
3025 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK		0x00f00000
3031 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK		0x0f000000
3037 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK		0xf0000000
3044 #define REG_A6XX_RB_SAMPLE_LOCATION_1				0x00008806
3045 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK		0x0000000f
3046 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT		0
3051 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK		0x000000f0
3057 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK		0x00000f00
3063 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK		0x0000f000
3069 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK		0x000f0000
3075 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK		0x00f00000
3081 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK		0x0f000000
3087 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK		0xf0000000
3094 #define REG_A6XX_RB_RENDER_CONTROL0				0x00008809
3095 #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL			0x00000001
3096 #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID		0x00000002
3097 #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE			0x00000004
3098 #define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL			0x00000008
3099 #define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_CENTROID		0x00000010
3100 #define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_SAMPLE		0x00000020
3101 #define A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK		0x000003c0
3107 #define A6XX_RB_RENDER_CONTROL0_UNK10				0x00000400
3109 #define REG_A6XX_RB_RENDER_CONTROL1				0x0000880a
3110 #define A6XX_RB_RENDER_CONTROL1_SAMPLEMASK			0x00000001
3111 #define A6XX_RB_RENDER_CONTROL1_UNK1				0x00000002
3112 #define A6XX_RB_RENDER_CONTROL1_FACENESS			0x00000004
3113 #define A6XX_RB_RENDER_CONTROL1_SAMPLEID			0x00000008
3114 #define A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__MASK	0x00000030
3120 #define A6XX_RB_RENDER_CONTROL1_SIZE				0x00000040
3121 #define A6XX_RB_RENDER_CONTROL1_LINELENGTHEN			0x00000080
3122 #define A6XX_RB_RENDER_CONTROL1_FOVEATION			0x00000100
3124 #define REG_A6XX_RB_FS_OUTPUT_CNTL0				0x0000880b
3125 #define A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE		0x00000001
3126 #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z			0x00000002
3127 #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK		0x00000004
3128 #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_STENCILREF		0x00000008
3130 #define REG_A6XX_RB_FS_OUTPUT_CNTL1				0x0000880c
3131 #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK			0x0000000f
3132 #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT			0
3138 #define REG_A6XX_RB_RENDER_COMPONENTS				0x0000880d
3139 #define A6XX_RB_RENDER_COMPONENTS_RT0__MASK			0x0000000f
3140 #define A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT			0
3145 #define A6XX_RB_RENDER_COMPONENTS_RT1__MASK			0x000000f0
3151 #define A6XX_RB_RENDER_COMPONENTS_RT2__MASK			0x00000f00
3157 #define A6XX_RB_RENDER_COMPONENTS_RT3__MASK			0x0000f000
3163 #define A6XX_RB_RENDER_COMPONENTS_RT4__MASK			0x000f0000
3169 #define A6XX_RB_RENDER_COMPONENTS_RT5__MASK			0x00f00000
3175 #define A6XX_RB_RENDER_COMPONENTS_RT6__MASK			0x0f000000
3181 #define A6XX_RB_RENDER_COMPONENTS_RT7__MASK			0xf0000000
3188 #define REG_A6XX_RB_DITHER_CNTL					0x0000880e
3189 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK		0x00000003
3190 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT		0
3195 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK		0x0000000c
3201 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK		0x00000030
3207 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK		0x000000c0
3213 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK		0x00000300
3219 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK		0x00000c00
3225 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK		0x00001000
3231 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK		0x0000c000
3238 #define REG_A6XX_RB_SRGB_CNTL					0x0000880f
3239 #define A6XX_RB_SRGB_CNTL_SRGB_MRT0				0x00000001
3240 #define A6XX_RB_SRGB_CNTL_SRGB_MRT1				0x00000002
3241 #define A6XX_RB_SRGB_CNTL_SRGB_MRT2				0x00000004
3242 #define A6XX_RB_SRGB_CNTL_SRGB_MRT3				0x00000008
3243 #define A6XX_RB_SRGB_CNTL_SRGB_MRT4				0x00000010
3244 #define A6XX_RB_SRGB_CNTL_SRGB_MRT5				0x00000020
3245 #define A6XX_RB_SRGB_CNTL_SRGB_MRT6				0x00000040
3246 #define A6XX_RB_SRGB_CNTL_SRGB_MRT7				0x00000080
3248 #define REG_A6XX_RB_SAMPLE_CNTL					0x00008810
3249 #define A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE			0x00000001
3251 #define REG_A6XX_RB_UNKNOWN_8811				0x00008811
3253 #define REG_A6XX_RB_UNKNOWN_8818				0x00008818
3255 #define REG_A6XX_RB_UNKNOWN_8819				0x00008819
3257 #define REG_A6XX_RB_UNKNOWN_881A				0x0000881a
3259 #define REG_A6XX_RB_UNKNOWN_881B				0x0000881b
3261 #define REG_A6XX_RB_UNKNOWN_881C				0x0000881c
3263 #define REG_A6XX_RB_UNKNOWN_881D				0x0000881d
3265 #define REG_A6XX_RB_UNKNOWN_881E				0x0000881e
3267 static inline uint32_t REG_A6XX_RB_MRT(uint32_t i0) { return 0x00008820 + 0x8*i0; }  in REG_A6XX_RB_MRT()
3269 static inline uint32_t REG_A6XX_RB_MRT_CONTROL(uint32_t i0) { return 0x00008820 + 0x8*i0; }  in REG_A6XX_RB_MRT_CONTROL()
3270 #define A6XX_RB_MRT_CONTROL_BLEND				0x00000001
3271 #define A6XX_RB_MRT_CONTROL_BLEND2				0x00000002
3272 #define A6XX_RB_MRT_CONTROL_ROP_ENABLE				0x00000004
3273 #define A6XX_RB_MRT_CONTROL_ROP_CODE__MASK			0x00000078
3279 #define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK		0x00000780
3286 static inline uint32_t REG_A6XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x00008821 + 0x8*i0; }  in REG_A6XX_RB_MRT_BLEND_CONTROL()
3287 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK		0x0000001f
3288 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT		0
3293 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK	0x000000e0
3299 #define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK		0x00001f00
3305 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK	0x001f0000
3311 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK	0x00e00000
3317 #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK	0x1f000000
3324 static inline uint32_t REG_A6XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x00008822 + 0x8*i0; }  in REG_A6XX_RB_MRT_BUF_INFO()
3325 #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK			0x000000ff
3326 #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT		0
3331 #define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK		0x00000300
3337 #define A6XX_RB_MRT_BUF_INFO_UNK10__MASK			0x00000400
3343 #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK			0x00006000
3350 static inline uint32_t REG_A6XX_RB_MRT_PITCH(uint32_t i0) { return 0x00008823 + 0x8*i0; }  in REG_A6XX_RB_MRT_PITCH()
3351 #define A6XX_RB_MRT_PITCH__MASK					0x0000ffff
3352 #define A6XX_RB_MRT_PITCH__SHIFT				0
3358 static inline uint32_t REG_A6XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x00008824 + 0x8*i0; }  in REG_A6XX_RB_MRT_ARRAY_PITCH()
3359 #define A6XX_RB_MRT_ARRAY_PITCH__MASK				0x1fffffff
3360 #define A6XX_RB_MRT_ARRAY_PITCH__SHIFT				0
3366 static inline uint32_t REG_A6XX_RB_MRT_BASE(uint32_t i0) { return 0x00008825 + 0x8*i0; }  in REG_A6XX_RB_MRT_BASE()
3367 #define A6XX_RB_MRT_BASE__MASK					0xffffffff
3368 #define A6XX_RB_MRT_BASE__SHIFT					0
3374 static inline uint32_t REG_A6XX_RB_MRT_BASE_GMEM(uint32_t i0) { return 0x00008827 + 0x8*i0; }  in REG_A6XX_RB_MRT_BASE_GMEM()
3375 #define A6XX_RB_MRT_BASE_GMEM__MASK				0xfffff000
3382 #define REG_A6XX_RB_BLEND_RED_F32				0x00008860
3383 #define A6XX_RB_BLEND_RED_F32__MASK				0xffffffff
3384 #define A6XX_RB_BLEND_RED_F32__SHIFT				0
3390 #define REG_A6XX_RB_BLEND_GREEN_F32				0x00008861
3391 #define A6XX_RB_BLEND_GREEN_F32__MASK				0xffffffff
3392 #define A6XX_RB_BLEND_GREEN_F32__SHIFT				0
3398 #define REG_A6XX_RB_BLEND_BLUE_F32				0x00008862
3399 #define A6XX_RB_BLEND_BLUE_F32__MASK				0xffffffff
3400 #define A6XX_RB_BLEND_BLUE_F32__SHIFT				0
3406 #define REG_A6XX_RB_BLEND_ALPHA_F32				0x00008863
3407 #define A6XX_RB_BLEND_ALPHA_F32__MASK				0xffffffff
3408 #define A6XX_RB_BLEND_ALPHA_F32__SHIFT				0
3414 #define REG_A6XX_RB_ALPHA_CONTROL				0x00008864
3415 #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK			0x000000ff
3416 #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT			0
3421 #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST			0x00000100
3422 #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK		0x00000e00
3429 #define REG_A6XX_RB_BLEND_CNTL					0x00008865
3430 #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK			0x000000ff
3431 #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT			0
3436 #define A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND			0x00000100
3437 #define A6XX_RB_BLEND_CNTL_DUAL_COLOR_IN_ENABLE			0x00000200
3438 #define A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE			0x00000400
3439 #define A6XX_RB_BLEND_CNTL_ALPHA_TO_ONE				0x00000800
3440 #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK			0xffff0000
3447 #define REG_A6XX_RB_DEPTH_PLANE_CNTL				0x00008870
3448 #define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK			0x00000003
3449 #define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT			0
3455 #define REG_A6XX_RB_DEPTH_CNTL					0x00008871
3456 #define A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE			0x00000001
3457 #define A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE			0x00000002
3458 #define A6XX_RB_DEPTH_CNTL_ZFUNC__MASK				0x0000001c
3464 #define A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE			0x00000020
3465 #define A6XX_RB_DEPTH_CNTL_Z_READ_ENABLE			0x00000040
3466 #define A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE			0x00000080
3468 #define REG_A6XX_RB_DEPTH_BUFFER_INFO				0x00008872
3469 #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK		0x00000007
3470 #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT		0
3475 #define A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK			0x00000018
3482 #define REG_A6XX_RB_DEPTH_BUFFER_PITCH				0x00008873
3483 #define A6XX_RB_DEPTH_BUFFER_PITCH__MASK			0x00003fff
3484 #define A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT			0
3490 #define REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH			0x00008874
3491 #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK			0x0fffffff
3492 #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT			0
3498 #define REG_A6XX_RB_DEPTH_BUFFER_BASE				0x00008875
3499 #define A6XX_RB_DEPTH_BUFFER_BASE__MASK				0xffffffff
3500 #define A6XX_RB_DEPTH_BUFFER_BASE__SHIFT			0
3506 #define REG_A6XX_RB_DEPTH_BUFFER_BASE_GMEM			0x00008877
3507 #define A6XX_RB_DEPTH_BUFFER_BASE_GMEM__MASK			0xfffff000
3514 #define REG_A6XX_RB_Z_BOUNDS_MIN				0x00008878
3515 #define A6XX_RB_Z_BOUNDS_MIN__MASK				0xffffffff
3516 #define A6XX_RB_Z_BOUNDS_MIN__SHIFT				0
3522 #define REG_A6XX_RB_Z_BOUNDS_MAX				0x00008879
3523 #define A6XX_RB_Z_BOUNDS_MAX__MASK				0xffffffff
3524 #define A6XX_RB_Z_BOUNDS_MAX__SHIFT				0
3530 #define REG_A6XX_RB_STENCIL_CONTROL				0x00008880
3531 #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE			0x00000001
3532 #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF		0x00000002
3533 #define A6XX_RB_STENCIL_CONTROL_STENCIL_READ			0x00000004
3534 #define A6XX_RB_STENCIL_CONTROL_FUNC__MASK			0x00000700
3540 #define A6XX_RB_STENCIL_CONTROL_FAIL__MASK			0x00003800
3546 #define A6XX_RB_STENCIL_CONTROL_ZPASS__MASK			0x0001c000
3552 #define A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK			0x000e0000
3558 #define A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK			0x00700000
3564 #define A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK			0x03800000
3570 #define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK			0x1c000000
3576 #define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK			0xe0000000
3583 #define REG_A6XX_RB_STENCIL_INFO				0x00008881
3584 #define A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL			0x00000001
3585 #define A6XX_RB_STENCIL_INFO_UNK1				0x00000002
3587 #define REG_A6XX_RB_STENCIL_BUFFER_PITCH			0x00008882
3588 #define A6XX_RB_STENCIL_BUFFER_PITCH__MASK			0x00000fff
3589 #define A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT			0
3595 #define REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH			0x00008883
3596 #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK		0x00ffffff
3597 #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT		0
3603 #define REG_A6XX_RB_STENCIL_BUFFER_BASE				0x00008884
3604 #define A6XX_RB_STENCIL_BUFFER_BASE__MASK			0xffffffff
3605 #define A6XX_RB_STENCIL_BUFFER_BASE__SHIFT			0
3611 #define REG_A6XX_RB_STENCIL_BUFFER_BASE_GMEM			0x00008886
3612 #define A6XX_RB_STENCIL_BUFFER_BASE_GMEM__MASK			0xfffff000
3619 #define REG_A6XX_RB_STENCILREF					0x00008887
3620 #define A6XX_RB_STENCILREF_REF__MASK				0x000000ff
3621 #define A6XX_RB_STENCILREF_REF__SHIFT				0
3626 #define A6XX_RB_STENCILREF_BFREF__MASK				0x0000ff00
3633 #define REG_A6XX_RB_STENCILMASK					0x00008888
3634 #define A6XX_RB_STENCILMASK_MASK__MASK				0x000000ff
3635 #define A6XX_RB_STENCILMASK_MASK__SHIFT				0
3640 #define A6XX_RB_STENCILMASK_BFMASK__MASK			0x0000ff00
3647 #define REG_A6XX_RB_STENCILWRMASK				0x00008889
3648 #define A6XX_RB_STENCILWRMASK_WRMASK__MASK			0x000000ff
3649 #define A6XX_RB_STENCILWRMASK_WRMASK__SHIFT			0
3654 #define A6XX_RB_STENCILWRMASK_BFWRMASK__MASK			0x0000ff00
3661 #define REG_A6XX_RB_WINDOW_OFFSET				0x00008890
3662 #define A6XX_RB_WINDOW_OFFSET_X__MASK				0x00003fff
3663 #define A6XX_RB_WINDOW_OFFSET_X__SHIFT				0
3668 #define A6XX_RB_WINDOW_OFFSET_Y__MASK				0x3fff0000
3675 #define REG_A6XX_RB_SAMPLE_COUNT_CONTROL			0x00008891
3676 #define A6XX_RB_SAMPLE_COUNT_CONTROL_UNK0			0x00000001
3677 #define A6XX_RB_SAMPLE_COUNT_CONTROL_COPY			0x00000002
3679 #define REG_A6XX_RB_LRZ_CNTL					0x00008898
3680 #define A6XX_RB_LRZ_CNTL_ENABLE					0x00000001
3682 #define REG_A6XX_RB_Z_CLAMP_MIN					0x000088c0
3683 #define A6XX_RB_Z_CLAMP_MIN__MASK				0xffffffff
3684 #define A6XX_RB_Z_CLAMP_MIN__SHIFT				0
3690 #define REG_A6XX_RB_Z_CLAMP_MAX					0x000088c1
3691 #define A6XX_RB_Z_CLAMP_MAX__MASK				0xffffffff
3692 #define A6XX_RB_Z_CLAMP_MAX__SHIFT				0
3698 #define REG_A6XX_RB_UNKNOWN_88D0				0x000088d0
3699 #define A6XX_RB_UNKNOWN_88D0_UNK0__MASK				0x00001fff
3700 #define A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT			0
3705 #define A6XX_RB_UNKNOWN_88D0_UNK16__MASK			0x07ff0000
3712 #define REG_A6XX_RB_BLIT_SCISSOR_TL				0x000088d1
3713 #define A6XX_RB_BLIT_SCISSOR_TL_X__MASK				0x00003fff
3714 #define A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT			0
3719 #define A6XX_RB_BLIT_SCISSOR_TL_Y__MASK				0x3fff0000
3726 #define REG_A6XX_RB_BLIT_SCISSOR_BR				0x000088d2
3727 #define A6XX_RB_BLIT_SCISSOR_BR_X__MASK				0x00003fff
3728 #define A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT			0
3733 #define A6XX_RB_BLIT_SCISSOR_BR_Y__MASK				0x3fff0000
3740 #define REG_A6XX_RB_BIN_CONTROL2				0x000088d3
3741 #define A6XX_RB_BIN_CONTROL2_BINW__MASK				0x0000003f
3742 #define A6XX_RB_BIN_CONTROL2_BINW__SHIFT			0
3747 #define A6XX_RB_BIN_CONTROL2_BINH__MASK				0x00007f00
3754 #define REG_A6XX_RB_WINDOW_OFFSET2				0x000088d4
3755 #define A6XX_RB_WINDOW_OFFSET2_X__MASK				0x00003fff
3756 #define A6XX_RB_WINDOW_OFFSET2_X__SHIFT				0
3761 #define A6XX_RB_WINDOW_OFFSET2_Y__MASK				0x3fff0000
3768 #define REG_A6XX_RB_MSAA_CNTL					0x000088d5
3769 #define A6XX_RB_MSAA_CNTL_SAMPLES__MASK				0x00000018
3776 #define REG_A6XX_RB_BLIT_BASE_GMEM				0x000088d6
3777 #define A6XX_RB_BLIT_BASE_GMEM__MASK				0xfffff000
3784 #define REG_A6XX_RB_BLIT_DST_INFO				0x000088d7
3785 #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK			0x00000003
3786 #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT			0
3791 #define A6XX_RB_BLIT_DST_INFO_FLAGS				0x00000004
3792 #define A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK			0x00000018
3798 #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK			0x00000060
3804 #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK		0x00007f80
3810 #define A6XX_RB_BLIT_DST_INFO_UNK15				0x00008000
3812 #define REG_A6XX_RB_BLIT_DST					0x000088d8
3813 #define A6XX_RB_BLIT_DST__MASK					0xffffffff
3814 #define A6XX_RB_BLIT_DST__SHIFT					0
3820 #define REG_A6XX_RB_BLIT_DST_PITCH				0x000088da
3821 #define A6XX_RB_BLIT_DST_PITCH__MASK				0x0000ffff
3822 #define A6XX_RB_BLIT_DST_PITCH__SHIFT				0
3828 #define REG_A6XX_RB_BLIT_DST_ARRAY_PITCH			0x000088db
3829 #define A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK			0x1fffffff
3830 #define A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT			0
3836 #define REG_A6XX_RB_BLIT_FLAG_DST				0x000088dc
3837 #define A6XX_RB_BLIT_FLAG_DST__MASK				0xffffffff
3838 #define A6XX_RB_BLIT_FLAG_DST__SHIFT				0
3844 #define REG_A6XX_RB_BLIT_FLAG_DST_PITCH				0x000088de
3845 #define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK			0x000007ff
3846 #define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT		0
3851 #define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK		0x0ffff800
3858 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0			0x000088df
3860 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW1			0x000088e0
3862 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW2			0x000088e1
3864 #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW3			0x000088e2
3866 #define REG_A6XX_RB_BLIT_INFO					0x000088e3
3867 #define A6XX_RB_BLIT_INFO_UNK0					0x00000001
3868 #define A6XX_RB_BLIT_INFO_GMEM					0x00000002
3869 #define A6XX_RB_BLIT_INFO_SAMPLE_0				0x00000004
3870 #define A6XX_RB_BLIT_INFO_DEPTH					0x00000008
3871 #define A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK			0x000000f0
3877 #define A6XX_RB_BLIT_INFO_UNK8__MASK				0x00000300
3883 #define A6XX_RB_BLIT_INFO_UNK12__MASK				0x0000f000
3890 #define REG_A6XX_RB_UNKNOWN_88F0				0x000088f0
3892 #define REG_A6XX_RB_UNK_FLAG_BUFFER_BASE			0x000088f1
3893 #define A6XX_RB_UNK_FLAG_BUFFER_BASE__MASK			0xffffffff
3894 #define A6XX_RB_UNK_FLAG_BUFFER_BASE__SHIFT			0
3900 #define REG_A6XX_RB_UNK_FLAG_BUFFER_PITCH			0x000088f3
3901 #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK		0x000007ff
3902 #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT		0
3907 #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK		0x00fff800
3914 #define REG_A6XX_RB_UNKNOWN_88F4				0x000088f4
3916 #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE			0x00008900
3917 #define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK			0xffffffff
3918 #define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT			0
3924 #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH			0x00008902
3925 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK		0x0000007f
3926 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT		0
3931 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK		0x00000700
3937 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK	0x0ffff800
3944 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x00008903 + 0x3*i0; }  in REG_A6XX_RB_MRT_FLAG_BUFFER()
3946 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t i0) { return 0x00008903 + 0x3*i0; }  in REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR()
3947 #define A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK			0xffffffff
3948 #define A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT			0
3954 static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x00008905 + 0x3*i0;…  in REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH()
3955 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK		0x000007ff
3956 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT		0
3961 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK		0x1ffff800
3968 #define REG_A6XX_RB_SAMPLE_COUNT_ADDR				0x00008927
3969 #define A6XX_RB_SAMPLE_COUNT_ADDR__MASK				0xffffffff
3970 #define A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT			0
3976 #define REG_A6XX_RB_UNKNOWN_8A00				0x00008a00
3978 #define REG_A6XX_RB_UNKNOWN_8A10				0x00008a10
3980 #define REG_A6XX_RB_UNKNOWN_8A20				0x00008a20
3982 #define REG_A6XX_RB_UNKNOWN_8A30				0x00008a30
3984 #define REG_A6XX_RB_2D_BLIT_CNTL				0x00008c00
3985 #define A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK			0x00000007
3986 #define A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT			0
3991 #define A6XX_RB_2D_BLIT_CNTL_OVERWRITEEN			0x00000008
3992 #define A6XX_RB_2D_BLIT_CNTL_UNK4__MASK				0x00000070
3998 #define A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR			0x00000080
3999 #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK			0x0000ff00
4005 #define A6XX_RB_2D_BLIT_CNTL_SCISSOR				0x00010000
4006 #define A6XX_RB_2D_BLIT_CNTL_UNK17__MASK			0x00060000
4012 #define A6XX_RB_2D_BLIT_CNTL_D24S8				0x00080000
4013 #define A6XX_RB_2D_BLIT_CNTL_MASK__MASK				0x00f00000
4019 #define A6XX_RB_2D_BLIT_CNTL_IFMT__MASK				0x1f000000
4025 #define A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__MASK			0x20000000
4032 #define REG_A6XX_RB_2D_UNKNOWN_8C01				0x00008c01
4034 #define REG_A6XX_RB_2D_DST_INFO					0x00008c17
4035 #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK			0x000000ff
4036 #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT			0
4041 #define A6XX_RB_2D_DST_INFO_TILE_MODE__MASK			0x00000300
4047 #define A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK			0x00000c00
4053 #define A6XX_RB_2D_DST_INFO_FLAGS				0x00001000
4054 #define A6XX_RB_2D_DST_INFO_SRGB				0x00002000
4055 #define A6XX_RB_2D_DST_INFO_SAMPLES__MASK			0x0000c000
4061 #define A6XX_RB_2D_DST_INFO_FILTER				0x00010000
4062 #define A6XX_RB_2D_DST_INFO_UNK17				0x00020000
4063 #define A6XX_RB_2D_DST_INFO_SAMPLES_AVERAGE			0x00040000
4064 #define A6XX_RB_2D_DST_INFO_UNK19				0x00080000
4065 #define A6XX_RB_2D_DST_INFO_UNK20				0x00100000
4066 #define A6XX_RB_2D_DST_INFO_UNK21				0x00200000
4067 #define A6XX_RB_2D_DST_INFO_UNK22				0x00400000
4068 #define A6XX_RB_2D_DST_INFO_UNK23__MASK				0x07800000
4074 #define A6XX_RB_2D_DST_INFO_UNK28				0x10000000
4076 #define REG_A6XX_RB_2D_DST					0x00008c18
4077 #define A6XX_RB_2D_DST__MASK					0xffffffff
4078 #define A6XX_RB_2D_DST__SHIFT					0
4084 #define REG_A6XX_RB_2D_DST_PITCH				0x00008c1a
4085 #define A6XX_RB_2D_DST_PITCH__MASK				0x0000ffff
4086 #define A6XX_RB_2D_DST_PITCH__SHIFT				0
4092 #define REG_A6XX_RB_2D_DST_PLANE1				0x00008c1b
4093 #define A6XX_RB_2D_DST_PLANE1__MASK				0xffffffff
4094 #define A6XX_RB_2D_DST_PLANE1__SHIFT				0
4100 #define REG_A6XX_RB_2D_DST_PLANE_PITCH				0x00008c1d
4101 #define A6XX_RB_2D_DST_PLANE_PITCH__MASK			0x0000ffff
4102 #define A6XX_RB_2D_DST_PLANE_PITCH__SHIFT			0
4108 #define REG_A6XX_RB_2D_DST_PLANE2				0x00008c1e
4109 #define A6XX_RB_2D_DST_PLANE2__MASK				0xffffffff
4110 #define A6XX_RB_2D_DST_PLANE2__SHIFT				0
4116 #define REG_A6XX_RB_2D_DST_FLAGS				0x00008c20
4117 #define A6XX_RB_2D_DST_FLAGS__MASK				0xffffffff
4118 #define A6XX_RB_2D_DST_FLAGS__SHIFT				0
4124 #define REG_A6XX_RB_2D_DST_FLAGS_PITCH				0x00008c22
4125 #define A6XX_RB_2D_DST_FLAGS_PITCH__MASK			0x000000ff
4126 #define A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT			0
4132 #define REG_A6XX_RB_2D_DST_FLAGS_PLANE				0x00008c23
4133 #define A6XX_RB_2D_DST_FLAGS_PLANE__MASK			0xffffffff
4134 #define A6XX_RB_2D_DST_FLAGS_PLANE__SHIFT			0
4140 #define REG_A6XX_RB_2D_DST_FLAGS_PLANE_PITCH			0x00008c25
4141 #define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK			0x000000ff
4142 #define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT			0
4148 #define REG_A6XX_RB_2D_SRC_SOLID_C0				0x00008c2c
4150 #define REG_A6XX_RB_2D_SRC_SOLID_C1				0x00008c2d
4152 #define REG_A6XX_RB_2D_SRC_SOLID_C2				0x00008c2e
4154 #define REG_A6XX_RB_2D_SRC_SOLID_C3				0x00008c2f
4156 #define REG_A6XX_RB_UNKNOWN_8E01				0x00008e01
4158 #define REG_A6XX_RB_UNKNOWN_8E04				0x00008e04
4160 #define REG_A6XX_RB_ADDR_MODE_CNTL				0x00008e05
4162 #define REG_A6XX_RB_CCU_CNTL					0x00008e07
4163 #define A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK			0xff800000
4169 #define A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK			0x001ff000
4175 #define A6XX_RB_CCU_CNTL_GMEM					0x00400000
4176 #define A6XX_RB_CCU_CNTL_UNK2					0x00000004
4178 #define REG_A6XX_RB_NC_MODE_CNTL				0x00008e08
4179 #define A6XX_RB_NC_MODE_CNTL_MODE				0x00000001
4180 #define A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK			0x00000006
4186 #define A6XX_RB_NC_MODE_CNTL_MIN_ACCESS_LENGTH			0x00000008
4187 #define A6XX_RB_NC_MODE_CNTL_AMSBC				0x00000010
4188 #define A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK			0x00000400
4194 #define A6XX_RB_NC_MODE_CNTL_RGB565_PREDICATOR			0x00000800
4195 #define A6XX_RB_NC_MODE_CNTL_UNK12__MASK			0x00003000
4202 static inline uint32_t REG_A6XX_RB_PERFCTR_RB_SEL(uint32_t i0) { return 0x00008e10 + 0x1*i0; }  in REG_A6XX_RB_PERFCTR_RB_SEL()
4204 static inline uint32_t REG_A6XX_RB_PERFCTR_CCU_SEL(uint32_t i0) { return 0x00008e18 + 0x1*i0; }  in REG_A6XX_RB_PERFCTR_CCU_SEL()
4206 #define REG_A6XX_RB_UNKNOWN_8E28				0x00008e28
4208 static inline uint32_t REG_A6XX_RB_PERFCTR_CMP_SEL(uint32_t i0) { return 0x00008e2c + 0x1*i0; }  in REG_A6XX_RB_PERFCTR_CMP_SEL()
4210 #define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST			0x00008e3b
4212 #define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD			0x00008e3d
4214 #define REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE		0x00008e50
4216 #define REG_A6XX_RB_UNKNOWN_8E51				0x00008e51
4217 #define A6XX_RB_UNKNOWN_8E51__MASK				0xffffffff
4218 #define A6XX_RB_UNKNOWN_8E51__SHIFT				0
4224 #define REG_A6XX_VPC_GS_PARAM					0x00009100
4225 #define A6XX_VPC_GS_PARAM_LINELENGTHLOC__MASK			0x000000ff
4226 #define A6XX_VPC_GS_PARAM_LINELENGTHLOC__SHIFT			0
4232 #define REG_A6XX_VPC_VS_CLIP_CNTL				0x00009101
4233 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK			0x000000ff
4234 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT			0
4239 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK		0x0000ff00
4245 #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK		0x00ff0000
4252 #define REG_A6XX_VPC_GS_CLIP_CNTL				0x00009102
4253 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK			0x000000ff
4254 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT			0
4259 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK		0x0000ff00
4265 #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK		0x00ff0000
4272 #define REG_A6XX_VPC_DS_CLIP_CNTL				0x00009103
4273 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK			0x000000ff
4274 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT			0
4279 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK		0x0000ff00
4285 #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK		0x00ff0000
4292 #define REG_A6XX_VPC_VS_LAYER_CNTL				0x00009104
4293 #define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK			0x000000ff
4294 #define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT			0
4299 #define A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK			0x0000ff00
4306 #define REG_A6XX_VPC_GS_LAYER_CNTL				0x00009105
4307 #define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK			0x000000ff
4308 #define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT			0
4313 #define A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK			0x0000ff00
4320 #define REG_A6XX_VPC_DS_LAYER_CNTL				0x00009106
4321 #define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK			0x000000ff
4322 #define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT			0
4327 #define A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK			0x0000ff00
4334 #define REG_A6XX_VPC_UNKNOWN_9107				0x00009107
4335 #define A6XX_VPC_UNKNOWN_9107_RASTER_DISCARD			0x00000001
4336 #define A6XX_VPC_UNKNOWN_9107_UNK2				0x00000004
4338 #define REG_A6XX_VPC_POLYGON_MODE				0x00009108
4339 #define A6XX_VPC_POLYGON_MODE_MODE__MASK			0x00000003
4340 #define A6XX_VPC_POLYGON_MODE_MODE__SHIFT			0
4346 static inline uint32_t REG_A6XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00009200 + 0x1*i0; }  in REG_A6XX_VPC_VARYING_INTERP()
4348 static inline uint32_t REG_A6XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00009200 + 0x1*i0; }  in REG_A6XX_VPC_VARYING_INTERP_MODE()
4350 static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00009208 + 0x1*i0; }  in REG_A6XX_VPC_VARYING_PS_REPL()
4352 static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00009208 + 0x1*i0;…  in REG_A6XX_VPC_VARYING_PS_REPL_MODE()
4354 #define REG_A6XX_VPC_UNKNOWN_9210				0x00009210
4356 #define REG_A6XX_VPC_UNKNOWN_9211				0x00009211
4358 static inline uint32_t REG_A6XX_VPC_VAR(uint32_t i0) { return 0x00009212 + 0x1*i0; }  in REG_A6XX_VPC_VAR()
4360 static inline uint32_t REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x00009212 + 0x1*i0; }  in REG_A6XX_VPC_VAR_DISABLE()
4362 #define REG_A6XX_VPC_SO_CNTL					0x00009216
4363 #define A6XX_VPC_SO_CNTL_ADDR__MASK				0x000000ff
4364 #define A6XX_VPC_SO_CNTL_ADDR__SHIFT				0
4369 #define A6XX_VPC_SO_CNTL_RESET					0x00010000
4371 #define REG_A6XX_VPC_SO_PROG					0x00009217
4372 #define A6XX_VPC_SO_PROG_A_BUF__MASK				0x00000003
4373 #define A6XX_VPC_SO_PROG_A_BUF__SHIFT				0
4378 #define A6XX_VPC_SO_PROG_A_OFF__MASK				0x000007fc
4384 #define A6XX_VPC_SO_PROG_A_EN					0x00000800
4385 #define A6XX_VPC_SO_PROG_B_BUF__MASK				0x00003000
4391 #define A6XX_VPC_SO_PROG_B_OFF__MASK				0x007fc000
4397 #define A6XX_VPC_SO_PROG_B_EN					0x00800000
4399 #define REG_A6XX_VPC_SO_STREAM_COUNTS				0x00009218
4400 #define A6XX_VPC_SO_STREAM_COUNTS__MASK				0xffffffff
4401 #define A6XX_VPC_SO_STREAM_COUNTS__SHIFT			0
4407 static inline uint32_t REG_A6XX_VPC_SO(uint32_t i0) { return 0x0000921a + 0x7*i0; }  in REG_A6XX_VPC_SO()
4409 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE(uint32_t i0) { return 0x0000921a + 0x7*i0; }  in REG_A6XX_VPC_SO_BUFFER_BASE()
4410 #define A6XX_VPC_SO_BUFFER_BASE__MASK				0xffffffff
4411 #define A6XX_VPC_SO_BUFFER_BASE__SHIFT				0
4417 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000921c + 0x7*i0; }  in REG_A6XX_VPC_SO_BUFFER_SIZE()
4418 #define A6XX_VPC_SO_BUFFER_SIZE__MASK				0xfffffffc
4425 static inline uint32_t REG_A6XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000921d + 0x7*i0; }  in REG_A6XX_VPC_SO_NCOMP()
4427 static inline uint32_t REG_A6XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000921e + 0x7*i0; }  in REG_A6XX_VPC_SO_BUFFER_OFFSET()
4428 #define A6XX_VPC_SO_BUFFER_OFFSET__MASK				0xfffffffc
4435 static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE(uint32_t i0) { return 0x0000921f + 0x7*i0; }  in REG_A6XX_VPC_SO_FLUSH_BASE()
4436 #define A6XX_VPC_SO_FLUSH_BASE__MASK				0xffffffff
4437 #define A6XX_VPC_SO_FLUSH_BASE__SHIFT				0
4443 #define REG_A6XX_VPC_POINT_COORD_INVERT				0x00009236
4444 #define A6XX_VPC_POINT_COORD_INVERT_INVERT			0x00000001
4446 #define REG_A6XX_VPC_UNKNOWN_9300				0x00009300
4448 #define REG_A6XX_VPC_VS_PACK					0x00009301
4449 #define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK			0x000000ff
4450 #define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT			0
4455 #define A6XX_VPC_VS_PACK_POSITIONLOC__MASK			0x0000ff00
4461 #define A6XX_VPC_VS_PACK_PSIZELOC__MASK				0x00ff0000
4467 #define A6XX_VPC_VS_PACK_EXTRAPOS__MASK				0x0f000000
4474 #define REG_A6XX_VPC_GS_PACK					0x00009302
4475 #define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK			0x000000ff
4476 #define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT			0
4481 #define A6XX_VPC_GS_PACK_POSITIONLOC__MASK			0x0000ff00
4487 #define A6XX_VPC_GS_PACK_PSIZELOC__MASK				0x00ff0000
4493 #define A6XX_VPC_GS_PACK_EXTRAPOS__MASK				0x0f000000
4500 #define REG_A6XX_VPC_DS_PACK					0x00009303
4501 #define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK			0x000000ff
4502 #define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT			0
4507 #define A6XX_VPC_DS_PACK_POSITIONLOC__MASK			0x0000ff00
4513 #define A6XX_VPC_DS_PACK_PSIZELOC__MASK				0x00ff0000
4519 #define A6XX_VPC_DS_PACK_EXTRAPOS__MASK				0x0f000000
4526 #define REG_A6XX_VPC_CNTL_0					0x00009304
4527 #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK			0x000000ff
4528 #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT			0
4533 #define A6XX_VPC_CNTL_0_PRIMIDLOC__MASK				0x0000ff00
4539 #define A6XX_VPC_CNTL_0_VARYING					0x00010000
4540 #define A6XX_VPC_CNTL_0_VIEWIDLOC__MASK				0xff000000
4547 #define REG_A6XX_VPC_SO_STREAM_CNTL				0x00009305
4548 #define A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK		0x00000007
4549 #define A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT		0
4554 #define A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK		0x00000038
4560 #define A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK		0x000001c0
4566 #define A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK		0x00000e00
4572 #define A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK		0x00078000
4579 #define REG_A6XX_VPC_SO_DISABLE					0x00009306
4580 #define A6XX_VPC_SO_DISABLE_DISABLE				0x00000001
4582 #define REG_A6XX_VPC_UNKNOWN_9600				0x00009600
4584 #define REG_A6XX_VPC_ADDR_MODE_CNTL				0x00009601
4586 #define REG_A6XX_VPC_UNKNOWN_9602				0x00009602
4588 #define REG_A6XX_VPC_UNKNOWN_9603				0x00009603
4590 static inline uint32_t REG_A6XX_VPC_PERFCTR_VPC_SEL(uint32_t i0) { return 0x00009604 + 0x1*i0; }  in REG_A6XX_VPC_PERFCTR_VPC_SEL()
4592 #define REG_A6XX_PC_TESS_NUM_VERTEX				0x00009800
4594 #define REG_A6XX_PC_HS_INPUT_SIZE				0x00009801
4595 #define A6XX_PC_HS_INPUT_SIZE_SIZE__MASK			0x000007ff
4596 #define A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT			0
4601 #define A6XX_PC_HS_INPUT_SIZE_UNK13__MASK			0x00002000
4608 #define REG_A6XX_PC_TESS_CNTL					0x00009802
4609 #define A6XX_PC_TESS_CNTL_SPACING__MASK				0x00000003
4610 #define A6XX_PC_TESS_CNTL_SPACING__SHIFT			0
4615 #define A6XX_PC_TESS_CNTL_OUTPUT__MASK				0x0000000c
4622 #define REG_A6XX_PC_RESTART_INDEX				0x00009803
4624 #define REG_A6XX_PC_MODE_CNTL					0x00009804
4626 #define REG_A6XX_PC_POWER_CNTL					0x00009805
4628 #define REG_A6XX_PC_PRIMID_PASSTHRU				0x00009806
4630 #define REG_A6XX_PC_SO_STREAM_CNTL				0x00009808
4631 #define A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE			0x00008000
4633 #define REG_A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL		0x0000980a
4634 #define A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN	0x00000001
4636 #define REG_A6XX_PC_DRAW_CMD					0x00009840
4637 #define A6XX_PC_DRAW_CMD_STATE_ID__MASK				0x000000ff
4638 #define A6XX_PC_DRAW_CMD_STATE_ID__SHIFT			0
4644 #define REG_A6XX_PC_DISPATCH_CMD				0x00009841
4645 #define A6XX_PC_DISPATCH_CMD_STATE_ID__MASK			0x000000ff
4646 #define A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT			0
4652 #define REG_A6XX_PC_EVENT_CMD					0x00009842
4653 #define A6XX_PC_EVENT_CMD_STATE_ID__MASK			0x00ff0000
4659 #define A6XX_PC_EVENT_CMD_EVENT__MASK				0x0000007f
4660 #define A6XX_PC_EVENT_CMD_EVENT__SHIFT				0
4666 #define REG_A6XX_PC_MARKER					0x00009880
4668 #define REG_A6XX_PC_POLYGON_MODE				0x00009981
4669 #define A6XX_PC_POLYGON_MODE_MODE__MASK				0x00000003
4670 #define A6XX_PC_POLYGON_MODE_MODE__SHIFT			0
4676 #define REG_A6XX_PC_RASTER_CNTL					0x00009980
4677 #define A6XX_PC_RASTER_CNTL_STREAM__MASK			0x00000003
4678 #define A6XX_PC_RASTER_CNTL_STREAM__SHIFT			0
4683 #define A6XX_PC_RASTER_CNTL_DISCARD				0x00000004
4685 #define REG_A6XX_PC_PRIMITIVE_CNTL_0				0x00009b00
4686 #define A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART		0x00000001
4687 #define A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST		0x00000002
4688 #define A6XX_PC_PRIMITIVE_CNTL_0_TESS_UPPER_LEFT_DOMAIN_ORIGIN	0x00000004
4689 #define A6XX_PC_PRIMITIVE_CNTL_0_UNK3				0x00000008
4691 #define REG_A6XX_PC_VS_OUT_CNTL					0x00009b01
4692 #define A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK			0x000000ff
4693 #define A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT		0
4698 #define A6XX_PC_VS_OUT_CNTL_PSIZE				0x00000100
4699 #define A6XX_PC_VS_OUT_CNTL_LAYER				0x00000200
4700 #define A6XX_PC_VS_OUT_CNTL_VIEW				0x00000400
4701 #define A6XX_PC_VS_OUT_CNTL_PRIMITIVE_ID			0x00000800
4702 #define A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK			0x00ff0000
4709 #define REG_A6XX_PC_GS_OUT_CNTL					0x00009b02
4710 #define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK			0x000000ff
4711 #define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT		0
4716 #define A6XX_PC_GS_OUT_CNTL_PSIZE				0x00000100
4717 #define A6XX_PC_GS_OUT_CNTL_LAYER				0x00000200
4718 #define A6XX_PC_GS_OUT_CNTL_VIEW				0x00000400
4719 #define A6XX_PC_GS_OUT_CNTL_PRIMITIVE_ID			0x00000800
4720 #define A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK			0x00ff0000
4727 #define REG_A6XX_PC_HS_OUT_CNTL					0x00009b03
4728 #define A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__MASK			0x000000ff
4729 #define A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__SHIFT		0
4734 #define A6XX_PC_HS_OUT_CNTL_PSIZE				0x00000100
4735 #define A6XX_PC_HS_OUT_CNTL_LAYER				0x00000200
4736 #define A6XX_PC_HS_OUT_CNTL_VIEW				0x00000400
4737 #define A6XX_PC_HS_OUT_CNTL_PRIMITIVE_ID			0x00000800
4738 #define A6XX_PC_HS_OUT_CNTL_CLIP_MASK__MASK			0x00ff0000
4745 #define REG_A6XX_PC_DS_OUT_CNTL					0x00009b04
4746 #define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK			0x000000ff
4747 #define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT		0
4752 #define A6XX_PC_DS_OUT_CNTL_PSIZE				0x00000100
4753 #define A6XX_PC_DS_OUT_CNTL_LAYER				0x00000200
4754 #define A6XX_PC_DS_OUT_CNTL_VIEW				0x00000400
4755 #define A6XX_PC_DS_OUT_CNTL_PRIMITIVE_ID			0x00000800
4756 #define A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK			0x00ff0000
4763 #define REG_A6XX_PC_PRIMITIVE_CNTL_5				0x00009b05
4764 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK		0x000000ff
4765 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT		0
4770 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK		0x00007c00
4776 #define A6XX_PC_PRIMITIVE_CNTL_5_LINELENGTHEN			0x00008000
4777 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK		0x00030000
4783 #define A6XX_PC_PRIMITIVE_CNTL_5_UNK18__MASK			0x00040000
4790 #define REG_A6XX_PC_PRIMITIVE_CNTL_6				0x00009b06
4791 #define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK		0x000007ff
4792 #define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT		0
4798 #define REG_A6XX_PC_MULTIVIEW_CNTL				0x00009b07
4799 #define A6XX_PC_MULTIVIEW_CNTL_ENABLE				0x00000001
4800 #define A6XX_PC_MULTIVIEW_CNTL_DISABLEMULTIPOS			0x00000002
4801 #define A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK			0x0000007c
4808 #define REG_A6XX_PC_MULTIVIEW_MASK				0x00009b08
4810 #define REG_A6XX_PC_2D_EVENT_CMD				0x00009c00
4811 #define A6XX_PC_2D_EVENT_CMD_EVENT__MASK			0x0000007f
4812 #define A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT			0
4817 #define A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK			0x0000ff00
4824 #define REG_A6XX_PC_DBG_ECO_CNTL				0x00009e00
4826 #define REG_A6XX_PC_ADDR_MODE_CNTL				0x00009e01
4828 #define REG_A6XX_PC_DRAW_INDX_BASE				0x00009e04
4830 #define REG_A6XX_PC_DRAW_FIRST_INDX				0x00009e06
4832 #define REG_A6XX_PC_DRAW_MAX_INDICES				0x00009e07
4834 #define REG_A6XX_PC_TESSFACTOR_ADDR				0x00009e08
4835 #define A6XX_PC_TESSFACTOR_ADDR__MASK				0xffffffff
4836 #define A6XX_PC_TESSFACTOR_ADDR__SHIFT				0
4842 #define REG_A6XX_PC_DRAW_INITIATOR				0x00009e0b
4843 #define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK			0x0000003f
4844 #define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT			0
4849 #define A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK		0x000000c0
4855 #define A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK			0x00000300
4861 #define A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK			0x00000c00
4867 #define A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK			0x00003000
4873 #define A6XX_PC_DRAW_INITIATOR_GS_ENABLE			0x00010000
4874 #define A6XX_PC_DRAW_INITIATOR_TESS_ENABLE			0x00020000
4876 #define REG_A6XX_PC_DRAW_NUM_INSTANCES				0x00009e0c
4878 #define REG_A6XX_PC_DRAW_NUM_INDICES				0x00009e0d
4880 #define REG_A6XX_PC_VSTREAM_CONTROL				0x00009e11
4881 #define A6XX_PC_VSTREAM_CONTROL_UNK0__MASK			0x0000ffff
4882 #define A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT			0
4887 #define A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK			0x003f0000
4893 #define A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK			0x07c00000
4900 #define REG_A6XX_PC_BIN_PRIM_STRM				0x00009e12
4901 #define A6XX_PC_BIN_PRIM_STRM__MASK				0xffffffff
4902 #define A6XX_PC_BIN_PRIM_STRM__SHIFT				0
4908 #define REG_A6XX_PC_BIN_DRAW_STRM				0x00009e14
4909 #define A6XX_PC_BIN_DRAW_STRM__MASK				0xffffffff
4910 #define A6XX_PC_BIN_DRAW_STRM__SHIFT				0
4916 #define REG_A6XX_PC_VISIBILITY_OVERRIDE				0x00009e1c
4917 #define A6XX_PC_VISIBILITY_OVERRIDE_OVERRIDE			0x00000001
4919 static inline uint32_t REG_A6XX_PC_PERFCTR_PC_SEL(uint32_t i0) { return 0x00009e34 + 0x1*i0; }  in REG_A6XX_PC_PERFCTR_PC_SEL()
4921 #define REG_A6XX_PC_UNKNOWN_9E72				0x00009e72
4923 #define REG_A6XX_VFD_CONTROL_0					0x0000a000
4924 #define A6XX_VFD_CONTROL_0_FETCH_CNT__MASK			0x0000003f
4925 #define A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT			0
4930 #define A6XX_VFD_CONTROL_0_DECODE_CNT__MASK			0x00003f00
4937 #define REG_A6XX_VFD_CONTROL_1					0x0000a001
4938 #define A6XX_VFD_CONTROL_1_REGID4VTX__MASK			0x000000ff
4939 #define A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT			0
4944 #define A6XX_VFD_CONTROL_1_REGID4INST__MASK			0x0000ff00
4950 #define A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK			0x00ff0000
4956 #define A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK			0xff000000
4963 #define REG_A6XX_VFD_CONTROL_2					0x0000a002
4964 #define A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__MASK		0x000000ff
4965 #define A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__SHIFT		0
4970 #define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK		0x0000ff00
4977 #define REG_A6XX_VFD_CONTROL_3					0x0000a003
4978 #define A6XX_VFD_CONTROL_3_REGID_DSPRIMID__MASK			0x000000ff
4979 #define A6XX_VFD_CONTROL_3_REGID_DSPRIMID__SHIFT		0
4984 #define A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__MASK		0x0000ff00
4990 #define A6XX_VFD_CONTROL_3_REGID_TESSX__MASK			0x00ff0000
4996 #define A6XX_VFD_CONTROL_3_REGID_TESSY__MASK			0xff000000
5003 #define REG_A6XX_VFD_CONTROL_4					0x0000a004
5004 #define A6XX_VFD_CONTROL_4_UNK0__MASK				0x000000ff
5005 #define A6XX_VFD_CONTROL_4_UNK0__SHIFT				0
5011 #define REG_A6XX_VFD_CONTROL_5					0x0000a005
5012 #define A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK			0x000000ff
5013 #define A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT		0
5018 #define A6XX_VFD_CONTROL_5_UNK8__MASK				0x0000ff00
5025 #define REG_A6XX_VFD_CONTROL_6					0x0000a006
5026 #define A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU			0x00000001
5028 #define REG_A6XX_VFD_MODE_CNTL					0x0000a007
5029 #define A6XX_VFD_MODE_CNTL_RENDER_MODE__MASK			0x00000007
5030 #define A6XX_VFD_MODE_CNTL_RENDER_MODE__SHIFT			0
5036 #define REG_A6XX_VFD_MULTIVIEW_CNTL				0x0000a008
5037 #define A6XX_VFD_MULTIVIEW_CNTL_ENABLE				0x00000001
5038 #define A6XX_VFD_MULTIVIEW_CNTL_DISABLEMULTIPOS			0x00000002
5039 #define A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK			0x0000007c
5046 #define REG_A6XX_VFD_ADD_OFFSET					0x0000a009
5047 #define A6XX_VFD_ADD_OFFSET_VERTEX				0x00000001
5048 #define A6XX_VFD_ADD_OFFSET_INSTANCE				0x00000002
5050 #define REG_A6XX_VFD_INDEX_OFFSET				0x0000a00e
5052 #define REG_A6XX_VFD_INSTANCE_START_OFFSET			0x0000a00f
5054 static inline uint32_t REG_A6XX_VFD_FETCH(uint32_t i0) { return 0x0000a010 + 0x4*i0; }  in REG_A6XX_VFD_FETCH()
5056 static inline uint32_t REG_A6XX_VFD_FETCH_BASE(uint32_t i0) { return 0x0000a010 + 0x4*i0; }  in REG_A6XX_VFD_FETCH_BASE()
5057 #define A6XX_VFD_FETCH_BASE__MASK				0xffffffff
5058 #define A6XX_VFD_FETCH_BASE__SHIFT				0
5064 static inline uint32_t REG_A6XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000a012 + 0x4*i0; }  in REG_A6XX_VFD_FETCH_SIZE()
5066 static inline uint32_t REG_A6XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000a013 + 0x4*i0; }  in REG_A6XX_VFD_FETCH_STRIDE()
5068 static inline uint32_t REG_A6XX_VFD_DECODE(uint32_t i0) { return 0x0000a090 + 0x2*i0; }  in REG_A6XX_VFD_DECODE()
5070 static inline uint32_t REG_A6XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000a090 + 0x2*i0; }  in REG_A6XX_VFD_DECODE_INSTR()
5071 #define A6XX_VFD_DECODE_INSTR_IDX__MASK				0x0000001f
5072 #define A6XX_VFD_DECODE_INSTR_IDX__SHIFT			0
5077 #define A6XX_VFD_DECODE_INSTR_OFFSET__MASK			0x0001ffe0
5083 #define A6XX_VFD_DECODE_INSTR_INSTANCED				0x00020000
5084 #define A6XX_VFD_DECODE_INSTR_FORMAT__MASK			0x0ff00000
5090 #define A6XX_VFD_DECODE_INSTR_SWAP__MASK			0x30000000
5096 #define A6XX_VFD_DECODE_INSTR_UNK30				0x40000000
5097 #define A6XX_VFD_DECODE_INSTR_FLOAT				0x80000000
5099 static inline uint32_t REG_A6XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000a091 + 0x2*i0; }  in REG_A6XX_VFD_DECODE_STEP_RATE()
5101 static inline uint32_t REG_A6XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; }  in REG_A6XX_VFD_DEST_CNTL()
5103 static inline uint32_t REG_A6XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; }  in REG_A6XX_VFD_DEST_CNTL_INSTR()
5104 #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK		0x0000000f
5105 #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT		0
5110 #define A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK			0x00000ff0
5117 #define REG_A6XX_VFD_POWER_CNTL					0x0000a0f8
5119 #define REG_A6XX_VFD_ADDR_MODE_CNTL				0x0000a601
5121 static inline uint32_t REG_A6XX_VFD_PERFCTR_VFD_SEL(uint32_t i0) { return 0x0000a610 + 0x1*i0; }  in REG_A6XX_VFD_PERFCTR_VFD_SEL()
5123 #define REG_A6XX_SP_VS_CTRL_REG0				0x0000a800
5124 #define A6XX_SP_VS_CTRL_REG0_MERGEDREGS				0x00100000
5125 #define A6XX_SP_VS_CTRL_REG0_UNK21				0x00200000
5126 #define A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK			0x00000001
5127 #define A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT			0
5132 #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x0000007e
5138 #define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x00001f80
5144 #define A6XX_SP_VS_CTRL_REG0_UNK13				0x00002000
5145 #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK			0x000fc000
5152 #define REG_A6XX_SP_VS_BRANCH_COND				0x0000a801
5154 #define REG_A6XX_SP_VS_PRIMITIVE_CNTL				0x0000a802
5155 #define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK			0x0000003f
5156 #define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT			0
5161 #define A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK		0x00003fc0
5168 static inline uint32_t REG_A6XX_SP_VS_OUT(uint32_t i0) { return 0x0000a803 + 0x1*i0; }  in REG_A6XX_SP_VS_OUT()
5170 static inline uint32_t REG_A6XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000a803 + 0x1*i0; }  in REG_A6XX_SP_VS_OUT_REG()
5171 #define A6XX_SP_VS_OUT_REG_A_REGID__MASK			0x000000ff
5172 #define A6XX_SP_VS_OUT_REG_A_REGID__SHIFT			0
5177 #define A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK			0x00000f00
5183 #define A6XX_SP_VS_OUT_REG_B_REGID__MASK			0x00ff0000
5189 #define A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK			0x0f000000
5196 static inline uint32_t REG_A6XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000a813 + 0x1*i0; }  in REG_A6XX_SP_VS_VPC_DST()
5198 static inline uint32_t REG_A6XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000a813 + 0x1*i0; }  in REG_A6XX_SP_VS_VPC_DST_REG()
5199 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK			0x000000ff
5200 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT			0
5205 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK			0x0000ff00
5211 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK			0x00ff0000
5217 #define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK			0xff000000
5224 #define REG_A6XX_SP_VS_OBJ_FIRST_EXEC_OFFSET			0x0000a81b
5226 #define REG_A6XX_SP_VS_OBJ_START				0x0000a81c
5227 #define A6XX_SP_VS_OBJ_START__MASK				0xffffffff
5228 #define A6XX_SP_VS_OBJ_START__SHIFT				0
5234 #define REG_A6XX_SP_VS_PVT_MEM_PARAM				0x0000a81e
5235 #define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK		0x000000ff
5236 #define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT		0
5241 #define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK	0xff000000
5248 #define REG_A6XX_SP_VS_PVT_MEM_ADDR				0x0000a81f
5249 #define A6XX_SP_VS_PVT_MEM_ADDR__MASK				0xffffffff
5250 #define A6XX_SP_VS_PVT_MEM_ADDR__SHIFT				0
5256 #define REG_A6XX_SP_VS_PVT_MEM_SIZE				0x0000a821
5257 #define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK		0x0003ffff
5258 #define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT		0
5263 #define A6XX_SP_VS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT		0x80000000
5265 #define REG_A6XX_SP_VS_TEX_COUNT				0x0000a822
5267 #define REG_A6XX_SP_VS_CONFIG					0x0000a823
5268 #define A6XX_SP_VS_CONFIG_BINDLESS_TEX				0x00000001
5269 #define A6XX_SP_VS_CONFIG_BINDLESS_SAMP				0x00000002
5270 #define A6XX_SP_VS_CONFIG_BINDLESS_IBO				0x00000004
5271 #define A6XX_SP_VS_CONFIG_BINDLESS_UBO				0x00000008
5272 #define A6XX_SP_VS_CONFIG_ENABLED				0x00000100
5273 #define A6XX_SP_VS_CONFIG_NTEX__MASK				0x0001fe00
5279 #define A6XX_SP_VS_CONFIG_NSAMP__MASK				0x003e0000
5285 #define A6XX_SP_VS_CONFIG_NIBO__MASK				0x1fc00000
5292 #define REG_A6XX_SP_VS_INSTRLEN					0x0000a824
5294 #define REG_A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET			0x0000a825
5295 #define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK		0x0007ffff
5296 #define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT	0
5302 #define REG_A6XX_SP_HS_CTRL_REG0				0x0000a830
5303 #define A6XX_SP_HS_CTRL_REG0_UNK20				0x00100000
5304 #define A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK			0x00000001
5305 #define A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT			0
5310 #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x0000007e
5316 #define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x00001f80
5322 #define A6XX_SP_HS_CTRL_REG0_UNK13				0x00002000
5323 #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK			0x000fc000
5330 #define REG_A6XX_SP_HS_WAVE_INPUT_SIZE				0x0000a831
5332 #define REG_A6XX_SP_HS_BRANCH_COND				0x0000a832
5334 #define REG_A6XX_SP_HS_OBJ_FIRST_EXEC_OFFSET			0x0000a833
5336 #define REG_A6XX_SP_HS_OBJ_START				0x0000a834
5337 #define A6XX_SP_HS_OBJ_START__MASK				0xffffffff
5338 #define A6XX_SP_HS_OBJ_START__SHIFT				0
5344 #define REG_A6XX_SP_HS_PVT_MEM_PARAM				0x0000a836
5345 #define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK		0x000000ff
5346 #define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT		0
5351 #define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK	0xff000000
5358 #define REG_A6XX_SP_HS_PVT_MEM_ADDR				0x0000a837
5359 #define A6XX_SP_HS_PVT_MEM_ADDR__MASK				0xffffffff
5360 #define A6XX_SP_HS_PVT_MEM_ADDR__SHIFT				0
5366 #define REG_A6XX_SP_HS_PVT_MEM_SIZE				0x0000a839
5367 #define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK		0x0003ffff
5368 #define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT		0
5373 #define A6XX_SP_HS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT		0x80000000
5375 #define REG_A6XX_SP_HS_TEX_COUNT				0x0000a83a
5377 #define REG_A6XX_SP_HS_CONFIG					0x0000a83b
5378 #define A6XX_SP_HS_CONFIG_BINDLESS_TEX				0x00000001
5379 #define A6XX_SP_HS_CONFIG_BINDLESS_SAMP				0x00000002
5380 #define A6XX_SP_HS_CONFIG_BINDLESS_IBO				0x00000004
5381 #define A6XX_SP_HS_CONFIG_BINDLESS_UBO				0x00000008
5382 #define A6XX_SP_HS_CONFIG_ENABLED				0x00000100
5383 #define A6XX_SP_HS_CONFIG_NTEX__MASK				0x0001fe00
5389 #define A6XX_SP_HS_CONFIG_NSAMP__MASK				0x003e0000
5395 #define A6XX_SP_HS_CONFIG_NIBO__MASK				0x1fc00000
5402 #define REG_A6XX_SP_HS_INSTRLEN					0x0000a83c
5404 #define REG_A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET			0x0000a83d
5405 #define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK		0x0007ffff
5406 #define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT	0
5412 #define REG_A6XX_SP_DS_CTRL_REG0				0x0000a840
5413 #define A6XX_SP_DS_CTRL_REG0_MERGEDREGS				0x00100000
5414 #define A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK			0x00000001
5415 #define A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT			0
5420 #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x0000007e
5426 #define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x00001f80
5432 #define A6XX_SP_DS_CTRL_REG0_UNK13				0x00002000
5433 #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK			0x000fc000
5440 #define REG_A6XX_SP_DS_BRANCH_COND				0x0000a841
5442 #define REG_A6XX_SP_DS_PRIMITIVE_CNTL				0x0000a842
5443 #define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK			0x0000003f
5444 #define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT			0
5449 #define A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK		0x00003fc0
5456 static inline uint32_t REG_A6XX_SP_DS_OUT(uint32_t i0) { return 0x0000a843 + 0x1*i0; }  in REG_A6XX_SP_DS_OUT()
5458 static inline uint32_t REG_A6XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000a843 + 0x1*i0; }  in REG_A6XX_SP_DS_OUT_REG()
5459 #define A6XX_SP_DS_OUT_REG_A_REGID__MASK			0x000000ff
5460 #define A6XX_SP_DS_OUT_REG_A_REGID__SHIFT			0
5465 #define A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK			0x00000f00
5471 #define A6XX_SP_DS_OUT_REG_B_REGID__MASK			0x00ff0000
5477 #define A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK			0x0f000000
5484 static inline uint32_t REG_A6XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000a853 + 0x1*i0; }  in REG_A6XX_SP_DS_VPC_DST()
5486 static inline uint32_t REG_A6XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000a853 + 0x1*i0; }  in REG_A6XX_SP_DS_VPC_DST_REG()
5487 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK			0x000000ff
5488 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT			0
5493 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK			0x0000ff00
5499 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK			0x00ff0000
5505 #define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK			0xff000000
5512 #define REG_A6XX_SP_DS_OBJ_FIRST_EXEC_OFFSET			0x0000a85b
5514 #define REG_A6XX_SP_DS_OBJ_START				0x0000a85c
5515 #define A6XX_SP_DS_OBJ_START__MASK				0xffffffff
5516 #define A6XX_SP_DS_OBJ_START__SHIFT				0
5522 #define REG_A6XX_SP_DS_PVT_MEM_PARAM				0x0000a85e
5523 #define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK		0x000000ff
5524 #define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT		0
5529 #define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK	0xff000000
5536 #define REG_A6XX_SP_DS_PVT_MEM_ADDR				0x0000a85f
5537 #define A6XX_SP_DS_PVT_MEM_ADDR__MASK				0xffffffff
5538 #define A6XX_SP_DS_PVT_MEM_ADDR__SHIFT				0
5544 #define REG_A6XX_SP_DS_PVT_MEM_SIZE				0x0000a861
5545 #define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK		0x0003ffff
5546 #define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT		0
5551 #define A6XX_SP_DS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT		0x80000000
5553 #define REG_A6XX_SP_DS_TEX_COUNT				0x0000a862
5555 #define REG_A6XX_SP_DS_CONFIG					0x0000a863
5556 #define A6XX_SP_DS_CONFIG_BINDLESS_TEX				0x00000001
5557 #define A6XX_SP_DS_CONFIG_BINDLESS_SAMP				0x00000002
5558 #define A6XX_SP_DS_CONFIG_BINDLESS_IBO				0x00000004
5559 #define A6XX_SP_DS_CONFIG_BINDLESS_UBO				0x00000008
5560 #define A6XX_SP_DS_CONFIG_ENABLED				0x00000100
5561 #define A6XX_SP_DS_CONFIG_NTEX__MASK				0x0001fe00
5567 #define A6XX_SP_DS_CONFIG_NSAMP__MASK				0x003e0000
5573 #define A6XX_SP_DS_CONFIG_NIBO__MASK				0x1fc00000
5580 #define REG_A6XX_SP_DS_INSTRLEN					0x0000a864
5582 #define REG_A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET			0x0000a865
5583 #define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK		0x0007ffff
5584 #define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT	0
5590 #define REG_A6XX_SP_GS_CTRL_REG0				0x0000a870
5591 #define A6XX_SP_GS_CTRL_REG0_UNK20				0x00100000
5592 #define A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK			0x00000001
5593 #define A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT			0
5598 #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x0000007e
5604 #define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x00001f80
5610 #define A6XX_SP_GS_CTRL_REG0_UNK13				0x00002000
5611 #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK			0x000fc000
5618 #define REG_A6XX_SP_GS_PRIM_SIZE				0x0000a871
5620 #define REG_A6XX_SP_GS_BRANCH_COND				0x0000a872
5622 #define REG_A6XX_SP_GS_PRIMITIVE_CNTL				0x0000a873
5623 #define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK			0x0000003f
5624 #define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT			0
5629 #define A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK		0x00003fc0
5636 static inline uint32_t REG_A6XX_SP_GS_OUT(uint32_t i0) { return 0x0000a874 + 0x1*i0; }  in REG_A6XX_SP_GS_OUT()
5638 static inline uint32_t REG_A6XX_SP_GS_OUT_REG(uint32_t i0) { return 0x0000a874 + 0x1*i0; }  in REG_A6XX_SP_GS_OUT_REG()
5639 #define A6XX_SP_GS_OUT_REG_A_REGID__MASK			0x000000ff
5640 #define A6XX_SP_GS_OUT_REG_A_REGID__SHIFT			0
5645 #define A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK			0x00000f00
5651 #define A6XX_SP_GS_OUT_REG_B_REGID__MASK			0x00ff0000
5657 #define A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK			0x0f000000
5664 static inline uint32_t REG_A6XX_SP_GS_VPC_DST(uint32_t i0) { return 0x0000a884 + 0x1*i0; }  in REG_A6XX_SP_GS_VPC_DST()
5666 static inline uint32_t REG_A6XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x0000a884 + 0x1*i0; }  in REG_A6XX_SP_GS_VPC_DST_REG()
5667 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK			0x000000ff
5668 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT			0
5673 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK			0x0000ff00
5679 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK			0x00ff0000
5685 #define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK			0xff000000
5692 #define REG_A6XX_SP_GS_OBJ_FIRST_EXEC_OFFSET			0x0000a88c
5694 #define REG_A6XX_SP_GS_OBJ_START				0x0000a88d
5695 #define A6XX_SP_GS_OBJ_START__MASK				0xffffffff
5696 #define A6XX_SP_GS_OBJ_START__SHIFT				0
5702 #define REG_A6XX_SP_GS_PVT_MEM_PARAM				0x0000a88f
5703 #define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK		0x000000ff
5704 #define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT		0
5709 #define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK	0xff000000
5716 #define REG_A6XX_SP_GS_PVT_MEM_ADDR				0x0000a890
5717 #define A6XX_SP_GS_PVT_MEM_ADDR__MASK				0xffffffff
5718 #define A6XX_SP_GS_PVT_MEM_ADDR__SHIFT				0
5724 #define REG_A6XX_SP_GS_PVT_MEM_SIZE				0x0000a892
5725 #define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK		0x0003ffff
5726 #define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT		0
5731 #define A6XX_SP_GS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT		0x80000000
5733 #define REG_A6XX_SP_GS_TEX_COUNT				0x0000a893
5735 #define REG_A6XX_SP_GS_CONFIG					0x0000a894
5736 #define A6XX_SP_GS_CONFIG_BINDLESS_TEX				0x00000001
5737 #define A6XX_SP_GS_CONFIG_BINDLESS_SAMP				0x00000002
5738 #define A6XX_SP_GS_CONFIG_BINDLESS_IBO				0x00000004
5739 #define A6XX_SP_GS_CONFIG_BINDLESS_UBO				0x00000008
5740 #define A6XX_SP_GS_CONFIG_ENABLED				0x00000100
5741 #define A6XX_SP_GS_CONFIG_NTEX__MASK				0x0001fe00
5747 #define A6XX_SP_GS_CONFIG_NSAMP__MASK				0x003e0000
5753 #define A6XX_SP_GS_CONFIG_NIBO__MASK				0x1fc00000
5760 #define REG_A6XX_SP_GS_INSTRLEN					0x0000a895
5762 #define REG_A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET			0x0000a896
5763 #define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK		0x0007ffff
5764 #define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT	0
5770 #define REG_A6XX_SP_VS_TEX_SAMP					0x0000a8a0
5771 #define A6XX_SP_VS_TEX_SAMP__MASK				0xffffffff
5772 #define A6XX_SP_VS_TEX_SAMP__SHIFT				0
5778 #define REG_A6XX_SP_HS_TEX_SAMP					0x0000a8a2
5779 #define A6XX_SP_HS_TEX_SAMP__MASK				0xffffffff
5780 #define A6XX_SP_HS_TEX_SAMP__SHIFT				0
5786 #define REG_A6XX_SP_DS_TEX_SAMP					0x0000a8a4
5787 #define A6XX_SP_DS_TEX_SAMP__MASK				0xffffffff
5788 #define A6XX_SP_DS_TEX_SAMP__SHIFT				0
5794 #define REG_A6XX_SP_GS_TEX_SAMP					0x0000a8a6
5795 #define A6XX_SP_GS_TEX_SAMP__MASK				0xffffffff
5796 #define A6XX_SP_GS_TEX_SAMP__SHIFT				0
5802 #define REG_A6XX_SP_VS_TEX_CONST				0x0000a8a8
5803 #define A6XX_SP_VS_TEX_CONST__MASK				0xffffffff
5804 #define A6XX_SP_VS_TEX_CONST__SHIFT				0
5810 #define REG_A6XX_SP_HS_TEX_CONST				0x0000a8aa
5811 #define A6XX_SP_HS_TEX_CONST__MASK				0xffffffff
5812 #define A6XX_SP_HS_TEX_CONST__SHIFT				0
5818 #define REG_A6XX_SP_DS_TEX_CONST				0x0000a8ac
5819 #define A6XX_SP_DS_TEX_CONST__MASK				0xffffffff
5820 #define A6XX_SP_DS_TEX_CONST__SHIFT				0
5826 #define REG_A6XX_SP_GS_TEX_CONST				0x0000a8ae
5827 #define A6XX_SP_GS_TEX_CONST__MASK				0xffffffff
5828 #define A6XX_SP_GS_TEX_CONST__SHIFT				0
5834 #define REG_A6XX_SP_FS_CTRL_REG0				0x0000a980
5835 #define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK			0x00100000
5841 #define A6XX_SP_FS_CTRL_REG0_UNK21				0x00200000
5842 #define A6XX_SP_FS_CTRL_REG0_VARYING				0x00400000
5843 #define A6XX_SP_FS_CTRL_REG0_DIFF_FINE				0x00800000
5844 #define A6XX_SP_FS_CTRL_REG0_UNK24				0x01000000
5845 #define A6XX_SP_FS_CTRL_REG0_UNK25				0x02000000
5846 #define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE			0x04000000
5847 #define A6XX_SP_FS_CTRL_REG0_UNK27__MASK			0x18000000
5853 #define A6XX_SP_FS_CTRL_REG0_MERGEDREGS				0x80000000
5854 #define A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK			0x00000001
5855 #define A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT			0
5860 #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x0000007e
5866 #define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x00001f80
5872 #define A6XX_SP_FS_CTRL_REG0_UNK13				0x00002000
5873 #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK			0x000fc000
5880 #define REG_A6XX_SP_FS_BRANCH_COND				0x0000a981
5882 #define REG_A6XX_SP_FS_OBJ_FIRST_EXEC_OFFSET			0x0000a982
5884 #define REG_A6XX_SP_FS_OBJ_START				0x0000a983
5885 #define A6XX_SP_FS_OBJ_START__MASK				0xffffffff
5886 #define A6XX_SP_FS_OBJ_START__SHIFT				0
5892 #define REG_A6XX_SP_FS_PVT_MEM_PARAM				0x0000a985
5893 #define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK		0x000000ff
5894 #define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT		0
5899 #define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK	0xff000000
5906 #define REG_A6XX_SP_FS_PVT_MEM_ADDR				0x0000a986
5907 #define A6XX_SP_FS_PVT_MEM_ADDR__MASK				0xffffffff
5908 #define A6XX_SP_FS_PVT_MEM_ADDR__SHIFT				0
5914 #define REG_A6XX_SP_FS_PVT_MEM_SIZE				0x0000a988
5915 #define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK		0x0003ffff
5916 #define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT		0
5921 #define A6XX_SP_FS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT		0x80000000
5923 #define REG_A6XX_SP_BLEND_CNTL					0x0000a989
5924 #define A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK			0x000000ff
5925 #define A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT			0
5930 #define A6XX_SP_BLEND_CNTL_UNK8					0x00000100
5931 #define A6XX_SP_BLEND_CNTL_DUAL_COLOR_IN_ENABLE			0x00000200
5932 #define A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE			0x00000400
5934 #define REG_A6XX_SP_SRGB_CNTL					0x0000a98a
5935 #define A6XX_SP_SRGB_CNTL_SRGB_MRT0				0x00000001
5936 #define A6XX_SP_SRGB_CNTL_SRGB_MRT1				0x00000002
5937 #define A6XX_SP_SRGB_CNTL_SRGB_MRT2				0x00000004
5938 #define A6XX_SP_SRGB_CNTL_SRGB_MRT3				0x00000008
5939 #define A6XX_SP_SRGB_CNTL_SRGB_MRT4				0x00000010
5940 #define A6XX_SP_SRGB_CNTL_SRGB_MRT5				0x00000020
5941 #define A6XX_SP_SRGB_CNTL_SRGB_MRT6				0x00000040
5942 #define A6XX_SP_SRGB_CNTL_SRGB_MRT7				0x00000080
5944 #define REG_A6XX_SP_FS_RENDER_COMPONENTS			0x0000a98b
5945 #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK			0x0000000f
5946 #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT			0
5951 #define A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK			0x000000f0
5957 #define A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK			0x00000f00
5963 #define A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK			0x0000f000
5969 #define A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK			0x000f0000
5975 #define A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK			0x00f00000
5981 #define A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK			0x0f000000
5987 #define A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK			0xf0000000
5994 #define REG_A6XX_SP_FS_OUTPUT_CNTL0				0x0000a98c
5995 #define A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE		0x00000001
5996 #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK		0x0000ff00
6002 #define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK		0x00ff0000
6008 #define A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK		0xff000000
6015 #define REG_A6XX_SP_FS_OUTPUT_CNTL1				0x0000a98d
6016 #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK			0x0000000f
6017 #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT			0
6023 static inline uint32_t REG_A6XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000a98e + 0x1*i0; }  in REG_A6XX_SP_FS_OUTPUT()
6025 static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; }  in REG_A6XX_SP_FS_OUTPUT_REG()
6026 #define A6XX_SP_FS_OUTPUT_REG_REGID__MASK			0x000000ff
6027 #define A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT			0
6032 #define A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION			0x00000100
6034 static inline uint32_t REG_A6XX_SP_FS_MRT(uint32_t i0) { return 0x0000a996 + 0x1*i0; }  in REG_A6XX_SP_FS_MRT()
6036 static inline uint32_t REG_A6XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000a996 + 0x1*i0; }  in REG_A6XX_SP_FS_MRT_REG()
6037 #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK			0x000000ff
6038 #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT			0
6043 #define A6XX_SP_FS_MRT_REG_COLOR_SINT				0x00000100
6044 #define A6XX_SP_FS_MRT_REG_COLOR_UINT				0x00000200
6045 #define A6XX_SP_FS_MRT_REG_UNK10				0x00000400
6047 #define REG_A6XX_SP_FS_PREFETCH_CNTL				0x0000a99e
6048 #define A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK			0x00000007
6049 #define A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT			0
6054 #define A6XX_SP_FS_PREFETCH_CNTL_UNK3				0x00000008
6055 #define A6XX_SP_FS_PREFETCH_CNTL_UNK4__MASK			0x00000ff0
6061 #define A6XX_SP_FS_PREFETCH_CNTL_UNK12__MASK			0x00007000
6068 static inline uint32_t REG_A6XX_SP_FS_PREFETCH(uint32_t i0) { return 0x0000a99f + 0x1*i0; }  in REG_A6XX_SP_FS_PREFETCH()
6070 static inline uint32_t REG_A6XX_SP_FS_PREFETCH_CMD(uint32_t i0) { return 0x0000a99f + 0x1*i0; }  in REG_A6XX_SP_FS_PREFETCH_CMD()
6071 #define A6XX_SP_FS_PREFETCH_CMD_SRC__MASK			0x0000007f
6072 #define A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT			0
6077 #define A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK			0x00000780
6083 #define A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK			0x0000f800
6089 #define A6XX_SP_FS_PREFETCH_CMD_DST__MASK			0x003f0000
6095 #define A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK			0x03c00000
6101 #define A6XX_SP_FS_PREFETCH_CMD_HALF				0x04000000
6102 #define A6XX_SP_FS_PREFETCH_CMD_CMD__MASK			0xf8000000
6109 static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; }  in REG_A6XX_SP_FS_BINDLESS_PREFETCH()
6111 static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(uint32_t i0) { return 0x0000a9a3 + 0x1*…  in REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD()
6112 #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK		0x0000ffff
6113 #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT		0
6118 #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK		0xffff0000
6125 #define REG_A6XX_SP_FS_TEX_COUNT				0x0000a9a7
6127 #define REG_A6XX_SP_UNKNOWN_A9A8				0x0000a9a8
6129 #define REG_A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET			0x0000a9a9
6130 #define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK		0x0007ffff
6131 #define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT	0
6137 #define REG_A6XX_SP_CS_CTRL_REG0				0x0000a9b0
6138 #define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK			0x00100000
6144 #define A6XX_SP_CS_CTRL_REG0_UNK21				0x00200000
6145 #define A6XX_SP_CS_CTRL_REG0_UNK22				0x00400000
6146 #define A6XX_SP_CS_CTRL_REG0_SEPARATEPROLOG			0x00800000
6147 #define A6XX_SP_CS_CTRL_REG0_MERGEDREGS				0x80000000
6148 #define A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK			0x00000001
6149 #define A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT			0
6154 #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x0000007e
6160 #define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x00001f80
6166 #define A6XX_SP_CS_CTRL_REG0_UNK13				0x00002000
6167 #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK			0x000fc000
6174 #define REG_A6XX_SP_CS_UNKNOWN_A9B1				0x0000a9b1
6175 #define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK		0x0000001f
6176 #define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT		0
6181 #define A6XX_SP_CS_UNKNOWN_A9B1_UNK5				0x00000020
6182 #define A6XX_SP_CS_UNKNOWN_A9B1_UNK6				0x00000040
6184 #define REG_A6XX_SP_CS_BRANCH_COND				0x0000a9b2
6186 #define REG_A6XX_SP_CS_OBJ_FIRST_EXEC_OFFSET			0x0000a9b3
6188 #define REG_A6XX_SP_CS_OBJ_START				0x0000a9b4
6189 #define A6XX_SP_CS_OBJ_START__MASK				0xffffffff
6190 #define A6XX_SP_CS_OBJ_START__SHIFT				0
6196 #define REG_A6XX_SP_CS_PVT_MEM_PARAM				0x0000a9b6
6197 #define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK		0x000000ff
6198 #define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT		0
6203 #define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK	0xff000000
6210 #define REG_A6XX_SP_CS_PVT_MEM_ADDR				0x0000a9b7
6211 #define A6XX_SP_CS_PVT_MEM_ADDR__MASK				0xffffffff
6212 #define A6XX_SP_CS_PVT_MEM_ADDR__SHIFT				0
6218 #define REG_A6XX_SP_CS_PVT_MEM_SIZE				0x0000a9b9
6219 #define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK		0x0003ffff
6220 #define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT		0
6225 #define A6XX_SP_CS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT		0x80000000
6227 #define REG_A6XX_SP_CS_TEX_COUNT				0x0000a9ba
6229 #define REG_A6XX_SP_CS_CONFIG					0x0000a9bb
6230 #define A6XX_SP_CS_CONFIG_BINDLESS_TEX				0x00000001
6231 #define A6XX_SP_CS_CONFIG_BINDLESS_SAMP				0x00000002
6232 #define A6XX_SP_CS_CONFIG_BINDLESS_IBO				0x00000004
6233 #define A6XX_SP_CS_CONFIG_BINDLESS_UBO				0x00000008
6234 #define A6XX_SP_CS_CONFIG_ENABLED				0x00000100
6235 #define A6XX_SP_CS_CONFIG_NTEX__MASK				0x0001fe00
6241 #define A6XX_SP_CS_CONFIG_NSAMP__MASK				0x003e0000
6247 #define A6XX_SP_CS_CONFIG_NIBO__MASK				0x1fc00000
6254 #define REG_A6XX_SP_CS_INSTRLEN					0x0000a9bc
6256 #define REG_A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET			0x0000a9bd
6257 #define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK		0x0007ffff
6258 #define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT	0
6264 #define REG_A6XX_SP_CS_CNTL_0					0x0000a9c2
6265 #define A6XX_SP_CS_CNTL_0_WGIDCONSTID__MASK			0x000000ff
6266 #define A6XX_SP_CS_CNTL_0_WGIDCONSTID__SHIFT			0
6271 #define A6XX_SP_CS_CNTL_0_WGSIZECONSTID__MASK			0x0000ff00
6277 #define A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__MASK			0x00ff0000
6283 #define A6XX_SP_CS_CNTL_0_LOCALIDREGID__MASK			0xff000000
6290 #define REG_A6XX_SP_CS_CNTL_1					0x0000a9c3
6291 #define A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK		0x000000ff
6292 #define A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT		0
6297 #define A6XX_SP_CS_CNTL_1_SINGLE_SP_CORE			0x00000100
6298 #define A6XX_SP_CS_CNTL_1_THREADSIZE__MASK			0x00000200
6304 #define A6XX_SP_CS_CNTL_1_THREADSIZE_SCALAR			0x00000400
6306 #define REG_A6XX_SP_FS_TEX_SAMP					0x0000a9e0
6307 #define A6XX_SP_FS_TEX_SAMP__MASK				0xffffffff
6308 #define A6XX_SP_FS_TEX_SAMP__SHIFT				0
6314 #define REG_A6XX_SP_CS_TEX_SAMP					0x0000a9e2
6315 #define A6XX_SP_CS_TEX_SAMP__MASK				0xffffffff
6316 #define A6XX_SP_CS_TEX_SAMP__SHIFT				0
6322 #define REG_A6XX_SP_FS_TEX_CONST				0x0000a9e4
6323 #define A6XX_SP_FS_TEX_CONST__MASK				0xffffffff
6324 #define A6XX_SP_FS_TEX_CONST__SHIFT				0
6330 #define REG_A6XX_SP_CS_TEX_CONST				0x0000a9e6
6331 #define A6XX_SP_CS_TEX_CONST__MASK				0xffffffff
6332 #define A6XX_SP_CS_TEX_CONST__SHIFT				0
6338 static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; }  in REG_A6XX_SP_CS_BINDLESS_BASE()
6340 static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000a9e8 + 0x2*i0;…  in REG_A6XX_SP_CS_BINDLESS_BASE_ADDR()
6342 #define REG_A6XX_SP_CS_IBO					0x0000a9f2
6343 #define A6XX_SP_CS_IBO__MASK					0xffffffff
6344 #define A6XX_SP_CS_IBO__SHIFT					0
6350 #define REG_A6XX_SP_CS_IBO_COUNT				0x0000aa00
6352 #define REG_A6XX_SP_MODE_CONTROL				0x0000ab00
6353 #define A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE		0x00000001
6354 #define A6XX_SP_MODE_CONTROL_ISAMMODE__MASK			0x00000006
6360 #define A6XX_SP_MODE_CONTROL_SHARED_CONSTS_ENABLE		0x00000008
6362 #define REG_A6XX_SP_FS_CONFIG					0x0000ab04
6363 #define A6XX_SP_FS_CONFIG_BINDLESS_TEX				0x00000001
6364 #define A6XX_SP_FS_CONFIG_BINDLESS_SAMP				0x00000002
6365 #define A6XX_SP_FS_CONFIG_BINDLESS_IBO				0x00000004
6366 #define A6XX_SP_FS_CONFIG_BINDLESS_UBO				0x00000008
6367 #define A6XX_SP_FS_CONFIG_ENABLED				0x00000100
6368 #define A6XX_SP_FS_CONFIG_NTEX__MASK				0x0001fe00
6374 #define A6XX_SP_FS_CONFIG_NSAMP__MASK				0x003e0000
6380 #define A6XX_SP_FS_CONFIG_NIBO__MASK				0x1fc00000
6387 #define REG_A6XX_SP_FS_INSTRLEN					0x0000ab05
6389 static inline uint32_t REG_A6XX_SP_BINDLESS_BASE(uint32_t i0) { return 0x0000ab10 + 0x2*i0; }  in REG_A6XX_SP_BINDLESS_BASE()
6391 static inline uint32_t REG_A6XX_SP_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000ab10 + 0x2*i0; }  in REG_A6XX_SP_BINDLESS_BASE_ADDR()
6393 #define REG_A6XX_SP_IBO						0x0000ab1a
6394 #define A6XX_SP_IBO__MASK					0xffffffff
6395 #define A6XX_SP_IBO__SHIFT					0
6401 #define REG_A6XX_SP_IBO_COUNT					0x0000ab20
6403 #define REG_A6XX_SP_2D_DST_FORMAT				0x0000acc0
6404 #define A6XX_SP_2D_DST_FORMAT_NORM				0x00000001
6405 #define A6XX_SP_2D_DST_FORMAT_SINT				0x00000002
6406 #define A6XX_SP_2D_DST_FORMAT_UINT				0x00000004
6407 #define A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK		0x000007f8
6413 #define A6XX_SP_2D_DST_FORMAT_SRGB				0x00000800
6414 #define A6XX_SP_2D_DST_FORMAT_MASK__MASK			0x0000f000
6421 #define REG_A6XX_SP_UNKNOWN_AE00				0x0000ae00
6423 #define REG_A6XX_SP_ADDR_MODE_CNTL				0x0000ae01
6425 #define REG_A6XX_SP_NC_MODE_CNTL				0x0000ae02
6427 #define REG_A6XX_SP_CHICKEN_BITS				0x0000ae03
6429 #define REG_A6XX_SP_FLOAT_CNTL					0x0000ae04
6430 #define A6XX_SP_FLOAT_CNTL_F16_NO_INF				0x00000008
6432 #define REG_A6XX_SP_PERFCTR_ENABLE				0x0000ae0f
6433 #define A6XX_SP_PERFCTR_ENABLE_VS				0x00000001
6434 #define A6XX_SP_PERFCTR_ENABLE_HS				0x00000002
6435 #define A6XX_SP_PERFCTR_ENABLE_DS				0x00000004
6436 #define A6XX_SP_PERFCTR_ENABLE_GS				0x00000008
6437 #define A6XX_SP_PERFCTR_ENABLE_FS				0x00000010
6438 #define A6XX_SP_PERFCTR_ENABLE_CS				0x00000020
6440 static inline uint32_t REG_A6XX_SP_PERFCTR_SP_SEL(uint32_t i0) { return 0x0000ae10 + 0x1*i0; }  in REG_A6XX_SP_PERFCTR_SP_SEL()
6442 #define REG_A6XX_SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE	0x0000be22
6444 #define REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR		0x0000b180
6445 #define A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__MASK		0xffffffff
6446 #define A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__SHIFT		0
6452 #define REG_A6XX_SP_UNKNOWN_B182				0x0000b182
6454 #define REG_A6XX_SP_UNKNOWN_B183				0x0000b183
6456 #define REG_A6XX_SP_UNKNOWN_B190				0x0000b190
6458 #define REG_A6XX_SP_UNKNOWN_B191				0x0000b191
6460 #define REG_A6XX_SP_TP_RAS_MSAA_CNTL				0x0000b300
6461 #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK			0x00000003
6462 #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT			0
6467 #define A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK			0x0000000c
6474 #define REG_A6XX_SP_TP_DEST_MSAA_CNTL				0x0000b301
6475 #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK			0x00000003
6476 #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT		0
6481 #define A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE			0x00000004
6483 #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR			0x0000b302
6484 #define A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__MASK			0xffffffff
6485 #define A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__SHIFT		0
6491 #define REG_A6XX_SP_TP_SAMPLE_CONFIG				0x0000b304
6492 #define A6XX_SP_TP_SAMPLE_CONFIG_UNK0				0x00000001
6493 #define A6XX_SP_TP_SAMPLE_CONFIG_LOCATION_ENABLE		0x00000002
6495 #define REG_A6XX_SP_TP_SAMPLE_LOCATION_0			0x0000b305
6496 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK		0x0000000f
6497 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT		0
6502 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK		0x000000f0
6508 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK		0x00000f00
6514 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK		0x0000f000
6520 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK		0x000f0000
6526 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK		0x00f00000
6532 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK		0x0f000000
6538 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK		0xf0000000
6545 #define REG_A6XX_SP_TP_SAMPLE_LOCATION_1			0x0000b306
6546 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK		0x0000000f
6547 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT		0
6552 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK		0x000000f0
6558 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK		0x00000f00
6564 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK		0x0000f000
6570 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK		0x000f0000
6576 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK		0x00f00000
6582 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK		0x0f000000
6588 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK		0xf0000000
6595 #define REG_A6XX_SP_TP_WINDOW_OFFSET				0x0000b307
6596 #define A6XX_SP_TP_WINDOW_OFFSET_X__MASK			0x00003fff
6597 #define A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT			0
6602 #define A6XX_SP_TP_WINDOW_OFFSET_Y__MASK			0x3fff0000
6609 #define REG_A6XX_SP_TP_MODE_CNTL				0x0000b309
6610 #define A6XX_SP_TP_MODE_CNTL_ISAMMODE__MASK			0x00000003
6611 #define A6XX_SP_TP_MODE_CNTL_ISAMMODE__SHIFT			0
6616 #define A6XX_SP_TP_MODE_CNTL_UNK3__MASK				0x000000fc
6623 #define REG_A6XX_SP_PS_2D_SRC_INFO				0x0000b4c0
6624 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK		0x000000ff
6625 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT		0
6630 #define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK			0x00000300
6636 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK			0x00000c00
6642 #define A6XX_SP_PS_2D_SRC_INFO_FLAGS				0x00001000
6643 #define A6XX_SP_PS_2D_SRC_INFO_SRGB				0x00002000
6644 #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK			0x0000c000
6650 #define A6XX_SP_PS_2D_SRC_INFO_FILTER				0x00010000
6651 #define A6XX_SP_PS_2D_SRC_INFO_UNK17				0x00020000
6652 #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE			0x00040000
6653 #define A6XX_SP_PS_2D_SRC_INFO_UNK19				0x00080000
6654 #define A6XX_SP_PS_2D_SRC_INFO_UNK20				0x00100000
6655 #define A6XX_SP_PS_2D_SRC_INFO_UNK21				0x00200000
6656 #define A6XX_SP_PS_2D_SRC_INFO_UNK22				0x00400000
6657 #define A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK			0x07800000
6663 #define A6XX_SP_PS_2D_SRC_INFO_UNK28				0x10000000
6665 #define REG_A6XX_SP_PS_2D_SRC_SIZE				0x0000b4c1
6666 #define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK			0x00007fff
6667 #define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT			0
6672 #define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK			0x3fff8000
6679 #define REG_A6XX_SP_PS_2D_SRC					0x0000b4c2
6680 #define A6XX_SP_PS_2D_SRC__MASK					0xffffffff
6681 #define A6XX_SP_PS_2D_SRC__SHIFT				0
6687 #define REG_A6XX_SP_PS_2D_SRC_PITCH				0x0000b4c4
6688 #define A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK			0x000001ff
6689 #define A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT			0
6694 #define A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK			0x00fffe00
6701 #define REG_A6XX_SP_PS_2D_SRC_PLANE1				0x0000b4c5
6702 #define A6XX_SP_PS_2D_SRC_PLANE1__MASK				0xffffffff
6703 #define A6XX_SP_PS_2D_SRC_PLANE1__SHIFT				0
6709 #define REG_A6XX_SP_PS_2D_SRC_PLANE_PITCH			0x0000b4c7
6710 #define A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK			0x00000fff
6711 #define A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT			0
6717 #define REG_A6XX_SP_PS_2D_SRC_PLANE2				0x0000b4c8
6718 #define A6XX_SP_PS_2D_SRC_PLANE2__MASK				0xffffffff
6719 #define A6XX_SP_PS_2D_SRC_PLANE2__SHIFT				0
6725 #define REG_A6XX_SP_PS_2D_SRC_FLAGS				0x0000b4ca
6726 #define A6XX_SP_PS_2D_SRC_FLAGS__MASK				0xffffffff
6727 #define A6XX_SP_PS_2D_SRC_FLAGS__SHIFT				0
6733 #define REG_A6XX_SP_PS_2D_SRC_FLAGS_PITCH			0x0000b4cc
6734 #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK			0x000000ff
6735 #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT			0
6741 #define REG_A6XX_SP_PS_UNKNOWN_B4CD				0x0000b4cd
6743 #define REG_A6XX_SP_PS_UNKNOWN_B4CE				0x0000b4ce
6745 #define REG_A6XX_SP_PS_UNKNOWN_B4CF				0x0000b4cf
6747 #define REG_A6XX_SP_PS_UNKNOWN_B4D0				0x0000b4d0
6749 #define REG_A6XX_SP_WINDOW_OFFSET				0x0000b4d1
6750 #define A6XX_SP_WINDOW_OFFSET_X__MASK				0x00003fff
6751 #define A6XX_SP_WINDOW_OFFSET_X__SHIFT				0
6756 #define A6XX_SP_WINDOW_OFFSET_Y__MASK				0x3fff0000
6763 #define REG_A6XX_TPL1_DBG_ECO_CNTL				0x0000b600
6765 #define REG_A6XX_TPL1_ADDR_MODE_CNTL				0x0000b601
6767 #define REG_A6XX_TPL1_UNKNOWN_B602				0x0000b602
6769 #define REG_A6XX_TPL1_NC_MODE_CNTL				0x0000b604
6770 #define A6XX_TPL1_NC_MODE_CNTL_MODE				0x00000001
6771 #define A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK			0x00000006
6777 #define A6XX_TPL1_NC_MODE_CNTL_MIN_ACCESS_LENGTH		0x00000008
6778 #define A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK			0x00000010
6784 #define A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK			0x000000c0
6791 #define REG_A6XX_TPL1_UNKNOWN_B605				0x0000b605
6793 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0			0x0000b608
6795 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1			0x0000b609
6797 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2			0x0000b60a
6799 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3			0x0000b60b
6801 #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4			0x0000b60c
6803 static inline uint32_t REG_A6XX_TPL1_PERFCTR_TP_SEL(uint32_t i0) { return 0x0000b610 + 0x1*i0; }  in REG_A6XX_TPL1_PERFCTR_TP_SEL()
6805 #define REG_A6XX_HLSQ_VS_CNTL					0x0000b800
6806 #define A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK			0x000000ff
6807 #define A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT			0
6812 #define A6XX_HLSQ_VS_CNTL_ENABLED				0x00000100
6814 #define REG_A6XX_HLSQ_HS_CNTL					0x0000b801
6815 #define A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK			0x000000ff
6816 #define A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT			0
6821 #define A6XX_HLSQ_HS_CNTL_ENABLED				0x00000100
6823 #define REG_A6XX_HLSQ_DS_CNTL					0x0000b802
6824 #define A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK			0x000000ff
6825 #define A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT			0
6830 #define A6XX_HLSQ_DS_CNTL_ENABLED				0x00000100
6832 #define REG_A6XX_HLSQ_GS_CNTL					0x0000b803
6833 #define A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK			0x000000ff
6834 #define A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT			0
6839 #define A6XX_HLSQ_GS_CNTL_ENABLED				0x00000100
6841 #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD			0x0000b820
6843 #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR		0x0000b821
6844 #define A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__MASK		0xffffffff
6845 #define A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__SHIFT		0
6851 #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_DATA			0x0000b823
6853 #define REG_A6XX_HLSQ_FS_CNTL_0					0x0000b980
6854 #define A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK			0x00000001
6855 #define A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT			0
6860 #define A6XX_HLSQ_FS_CNTL_0_VARYINGS				0x00000002
6861 #define A6XX_HLSQ_FS_CNTL_0_UNK2__MASK				0x00000ffc
6868 #define REG_A6XX_HLSQ_UNKNOWN_B981				0x0000b981
6870 #define REG_A6XX_HLSQ_CONTROL_1_REG				0x0000b982
6872 #define REG_A6XX_HLSQ_CONTROL_2_REG				0x0000b983
6873 #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK			0x000000ff
6874 #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT		0
6879 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK			0x0000ff00
6885 #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK		0x00ff0000
6891 #define A6XX_HLSQ_CONTROL_2_REG_SIZE__MASK			0xff000000
6898 #define REG_A6XX_HLSQ_CONTROL_3_REG				0x0000b984
6899 #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK		0x000000ff
6900 #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT		0
6905 #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK		0x0000ff00
6911 #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK		0x00ff0000
6917 #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK	0xff000000
6924 #define REG_A6XX_HLSQ_CONTROL_4_REG				0x0000b985
6925 #define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK		0x000000ff
6926 #define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT		0
6931 #define A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK		0x0000ff00
6937 #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK		0x00ff0000
6943 #define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK		0xff000000
6950 #define REG_A6XX_HLSQ_CONTROL_5_REG				0x0000b986
6951 #define A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK		0x000000ff
6952 #define A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT		0
6957 #define A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK	0x0000ff00
6964 #define REG_A6XX_HLSQ_CS_CNTL					0x0000b987
6965 #define A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK			0x000000ff
6966 #define A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT			0
6971 #define A6XX_HLSQ_CS_CNTL_ENABLED				0x00000100
6973 #define REG_A6XX_HLSQ_CS_NDRANGE_0				0x0000b990
6974 #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK			0x00000003
6975 #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT			0
6980 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK			0x00000ffc
6986 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK			0x003ff000
6992 #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK			0xffc00000
6999 #define REG_A6XX_HLSQ_CS_NDRANGE_1				0x0000b991
7000 #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK		0xffffffff
7001 #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT		0
7007 #define REG_A6XX_HLSQ_CS_NDRANGE_2				0x0000b992
7008 #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK		0xffffffff
7009 #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT		0
7015 #define REG_A6XX_HLSQ_CS_NDRANGE_3				0x0000b993
7016 #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK		0xffffffff
7017 #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT		0
7023 #define REG_A6XX_HLSQ_CS_NDRANGE_4				0x0000b994
7024 #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK		0xffffffff
7025 #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT		0
7031 #define REG_A6XX_HLSQ_CS_NDRANGE_5				0x0000b995
7032 #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK		0xffffffff
7033 #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT		0
7039 #define REG_A6XX_HLSQ_CS_NDRANGE_6				0x0000b996
7040 #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK		0xffffffff
7041 #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT		0
7047 #define REG_A6XX_HLSQ_CS_CNTL_0					0x0000b997
7048 #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK			0x000000ff
7049 #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT			0
7054 #define A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK			0x0000ff00
7060 #define A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK		0x00ff0000
7066 #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK			0xff000000
7073 #define REG_A6XX_HLSQ_CS_CNTL_1					0x0000b998
7074 #define A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK		0x000000ff
7075 #define A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT		0
7080 #define A6XX_HLSQ_CS_CNTL_1_SINGLE_SP_CORE			0x00000100
7081 #define A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK			0x00000200
7087 #define A6XX_HLSQ_CS_CNTL_1_THREADSIZE_SCALAR			0x00000400
7089 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_X				0x0000b999
7091 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y				0x0000b99a
7093 #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z				0x0000b99b
7095 #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD			0x0000b9a0
7097 #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR		0x0000b9a1
7098 #define A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__MASK		0xffffffff
7099 #define A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__SHIFT		0
7105 #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_DATA			0x0000b9a3
7107 static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; }  in REG_A6XX_HLSQ_CS_BINDLESS_BASE()
7109 static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000b9c0 + 0x2*i…  in REG_A6XX_HLSQ_CS_BINDLESS_BASE_ADDR()
7111 #define REG_A6XX_HLSQ_CS_UNKNOWN_B9D0				0x0000b9d0
7112 #define A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__MASK		0x0000001f
7113 #define A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__SHIFT		0
7118 #define A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK5				0x00000020
7119 #define A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK6				0x00000040
7121 #define REG_A6XX_HLSQ_DRAW_CMD					0x0000bb00
7122 #define A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK			0x000000ff
7123 #define A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT			0
7129 #define REG_A6XX_HLSQ_DISPATCH_CMD				0x0000bb01
7130 #define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK			0x000000ff
7131 #define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT			0
7137 #define REG_A6XX_HLSQ_EVENT_CMD					0x0000bb02
7138 #define A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK			0x00ff0000
7144 #define A6XX_HLSQ_EVENT_CMD_EVENT__MASK				0x0000007f
7145 #define A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT			0
7151 #define REG_A6XX_HLSQ_INVALIDATE_CMD				0x0000bb08
7152 #define A6XX_HLSQ_INVALIDATE_CMD_VS_STATE			0x00000001
7153 #define A6XX_HLSQ_INVALIDATE_CMD_HS_STATE			0x00000002
7154 #define A6XX_HLSQ_INVALIDATE_CMD_DS_STATE			0x00000004
7155 #define A6XX_HLSQ_INVALIDATE_CMD_GS_STATE			0x00000008
7156 #define A6XX_HLSQ_INVALIDATE_CMD_FS_STATE			0x00000010
7157 #define A6XX_HLSQ_INVALIDATE_CMD_CS_STATE			0x00000020
7158 #define A6XX_HLSQ_INVALIDATE_CMD_CS_IBO				0x00000040
7159 #define A6XX_HLSQ_INVALIDATE_CMD_GFX_IBO			0x00000080
7160 #define A6XX_HLSQ_INVALIDATE_CMD_CS_SHARED_CONST		0x00080000
7161 #define A6XX_HLSQ_INVALIDATE_CMD_GFX_SHARED_CONST		0x00000100
7162 #define A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK		0x00003e00
7168 #define A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK		0x0007c000
7175 #define REG_A6XX_HLSQ_FS_CNTL					0x0000bb10
7176 #define A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK			0x000000ff
7177 #define A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT			0
7182 #define A6XX_HLSQ_FS_CNTL_ENABLED				0x00000100
7184 #define REG_A6XX_HLSQ_SHARED_CONSTS				0x0000bb11
7185 #define A6XX_HLSQ_SHARED_CONSTS_ENABLE				0x00000001
7187 static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE(uint32_t i0) { return 0x0000bb20 + 0x2*i0; }  in REG_A6XX_HLSQ_BINDLESS_BASE()
7189 static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000bb20 + 0x2*i0; }  in REG_A6XX_HLSQ_BINDLESS_BASE_ADDR()
7191 #define REG_A6XX_HLSQ_2D_EVENT_CMD				0x0000bd80
7192 #define A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK			0x0000ff00
7198 #define A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK			0x0000007f
7199 #define A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT			0
7205 #define REG_A6XX_HLSQ_UNKNOWN_BE00				0x0000be00
7207 #define REG_A6XX_HLSQ_UNKNOWN_BE01				0x0000be01
7209 #define REG_A6XX_HLSQ_UNKNOWN_BE04				0x0000be04
7211 #define REG_A6XX_HLSQ_ADDR_MODE_CNTL				0x0000be05
7213 #define REG_A6XX_HLSQ_UNKNOWN_BE08				0x0000be08
7215 static inline uint32_t REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL(uint32_t i0) { return 0x0000be10 + 0x1*i0; }  in REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL()
7217 #define REG_A6XX_HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE	0x0000be22
7219 #define REG_A6XX_CP_EVENT_START					0x0000d600
7220 #define A6XX_CP_EVENT_START_STATE_ID__MASK			0x000000ff
7221 #define A6XX_CP_EVENT_START_STATE_ID__SHIFT			0
7227 #define REG_A6XX_CP_EVENT_END					0x0000d601
7228 #define A6XX_CP_EVENT_END_STATE_ID__MASK			0x000000ff
7229 #define A6XX_CP_EVENT_END_STATE_ID__SHIFT			0
7235 #define REG_A6XX_CP_2D_EVENT_START				0x0000d700
7236 #define A6XX_CP_2D_EVENT_START_STATE_ID__MASK			0x000000ff
7237 #define A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT			0
7243 #define REG_A6XX_CP_2D_EVENT_END				0x0000d701
7244 #define A6XX_CP_2D_EVENT_END_STATE_ID__MASK			0x000000ff
7245 #define A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT			0
7251 #define REG_A6XX_TEX_SAMP_0					0x00000000
7252 #define A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR			0x00000001
7253 #define A6XX_TEX_SAMP_0_XY_MAG__MASK				0x00000006
7259 #define A6XX_TEX_SAMP_0_XY_MIN__MASK				0x00000018
7265 #define A6XX_TEX_SAMP_0_WRAP_S__MASK				0x000000e0
7271 #define A6XX_TEX_SAMP_0_WRAP_T__MASK				0x00000700
7277 #define A6XX_TEX_SAMP_0_WRAP_R__MASK				0x00003800
7283 #define A6XX_TEX_SAMP_0_ANISO__MASK				0x0001c000
7289 #define A6XX_TEX_SAMP_0_LOD_BIAS__MASK				0xfff80000
7296 #define REG_A6XX_TEX_SAMP_1					0x00000001
7297 #define A6XX_TEX_SAMP_1_CLAMPENABLE				0x00000001
7298 #define A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK			0x0000000e
7304 #define A6XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF			0x00000010
7305 #define A6XX_TEX_SAMP_1_UNNORM_COORDS				0x00000020
7306 #define A6XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR			0x00000040
7307 #define A6XX_TEX_SAMP_1_MAX_LOD__MASK				0x000fff00
7313 #define A6XX_TEX_SAMP_1_MIN_LOD__MASK				0xfff00000
7320 #define REG_A6XX_TEX_SAMP_2					0x00000002
7321 #define A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK			0x00000003
7322 #define A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT			0
7327 #define A6XX_TEX_SAMP_2_CHROMA_LINEAR				0x00000020
7328 #define A6XX_TEX_SAMP_2_BCOLOR__MASK				0xffffff80
7335 #define REG_A6XX_TEX_SAMP_3					0x00000003
7337 #define REG_A6XX_TEX_CONST_0					0x00000000
7338 #define A6XX_TEX_CONST_0_TILE_MODE__MASK			0x00000003
7339 #define A6XX_TEX_CONST_0_TILE_MODE__SHIFT			0
7344 #define A6XX_TEX_CONST_0_SRGB					0x00000004
7345 #define A6XX_TEX_CONST_0_SWIZ_X__MASK				0x00000070
7351 #define A6XX_TEX_CONST_0_SWIZ_Y__MASK				0x00000380
7357 #define A6XX_TEX_CONST_0_SWIZ_Z__MASK				0x00001c00
7363 #define A6XX_TEX_CONST_0_SWIZ_W__MASK				0x0000e000
7369 #define A6XX_TEX_CONST_0_MIPLVLS__MASK				0x000f0000
7375 #define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_X			0x00010000
7376 #define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_Y			0x00040000
7377 #define A6XX_TEX_CONST_0_SAMPLES__MASK				0x00300000
7383 #define A6XX_TEX_CONST_0_FMT__MASK				0x3fc00000
7389 #define A6XX_TEX_CONST_0_SWAP__MASK				0xc0000000
7396 #define REG_A6XX_TEX_CONST_1					0x00000001
7397 #define A6XX_TEX_CONST_1_WIDTH__MASK				0x00007fff
7398 #define A6XX_TEX_CONST_1_WIDTH__SHIFT				0
7403 #define A6XX_TEX_CONST_1_HEIGHT__MASK				0x3fff8000
7410 #define REG_A6XX_TEX_CONST_2					0x00000002
7411 #define A6XX_TEX_CONST_2_BUFFER					0x00000010
7412 #define A6XX_TEX_CONST_2_PITCHALIGN__MASK			0x0000000f
7413 #define A6XX_TEX_CONST_2_PITCHALIGN__SHIFT			0
7418 #define A6XX_TEX_CONST_2_PITCH__MASK				0x1fffff80
7424 #define A6XX_TEX_CONST_2_TYPE__MASK				0xe0000000
7431 #define REG_A6XX_TEX_CONST_3					0x00000003
7432 #define A6XX_TEX_CONST_3_ARRAY_PITCH__MASK			0x00003fff
7433 #define A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT			0
7438 #define A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK			0x07800000
7444 #define A6XX_TEX_CONST_3_TILE_ALL				0x08000000
7445 #define A6XX_TEX_CONST_3_FLAG					0x10000000
7447 #define REG_A6XX_TEX_CONST_4					0x00000004
7448 #define A6XX_TEX_CONST_4_BASE_LO__MASK				0xffffffe0
7455 #define REG_A6XX_TEX_CONST_5					0x00000005
7456 #define A6XX_TEX_CONST_5_BASE_HI__MASK				0x0001ffff
7457 #define A6XX_TEX_CONST_5_BASE_HI__SHIFT				0
7462 #define A6XX_TEX_CONST_5_DEPTH__MASK				0x3ffe0000
7469 #define REG_A6XX_TEX_CONST_6					0x00000006
7470 #define A6XX_TEX_CONST_6_PLANE_PITCH__MASK			0xffffff00
7477 #define REG_A6XX_TEX_CONST_7					0x00000007
7478 #define A6XX_TEX_CONST_7_FLAG_LO__MASK				0xffffffe0
7485 #define REG_A6XX_TEX_CONST_8					0x00000008
7486 #define A6XX_TEX_CONST_8_FLAG_HI__MASK				0x0001ffff
7487 #define A6XX_TEX_CONST_8_FLAG_HI__SHIFT				0
7493 #define REG_A6XX_TEX_CONST_9					0x00000009
7494 #define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK		0x0001ffff
7495 #define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT		0
7501 #define REG_A6XX_TEX_CONST_10					0x0000000a
7502 #define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK		0x0000007f
7503 #define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT		0
7508 #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK		0x00000f00
7514 #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK		0x0000f000
7521 #define REG_A6XX_TEX_CONST_11					0x0000000b
7523 #define REG_A6XX_TEX_CONST_12					0x0000000c
7525 #define REG_A6XX_TEX_CONST_13					0x0000000d
7527 #define REG_A6XX_TEX_CONST_14					0x0000000e
7529 #define REG_A6XX_TEX_CONST_15					0x0000000f
7531 #define REG_A6XX_UBO_0						0x00000000
7532 #define A6XX_UBO_0_BASE_LO__MASK				0xffffffff
7533 #define A6XX_UBO_0_BASE_LO__SHIFT				0
7539 #define REG_A6XX_UBO_1						0x00000001
7540 #define A6XX_UBO_1_BASE_HI__MASK				0x0001ffff
7541 #define A6XX_UBO_1_BASE_HI__SHIFT				0
7546 #define A6XX_UBO_1_SIZE__MASK					0xfffe0000
7553 #define REG_A6XX_PDC_GPU_ENABLE_PDC				0x00001140
7555 #define REG_A6XX_PDC_GPU_SEQ_START_ADDR				0x00001148
7557 #define REG_A6XX_PDC_GPU_TCS0_CONTROL				0x00001540
7559 #define REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK			0x00001541
7561 #define REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK		0x00001542
7563 #define REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID			0x00001543
7565 #define REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR				0x00001544
7567 #define REG_A6XX_PDC_GPU_TCS0_CMD0_DATA				0x00001545
7569 #define REG_A6XX_PDC_GPU_TCS1_CONTROL				0x00001572
7571 #define REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK			0x00001573
7573 #define REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK		0x00001574
7575 #define REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID			0x00001575
7577 #define REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR				0x00001576
7579 #define REG_A6XX_PDC_GPU_TCS1_CMD0_DATA				0x00001577
7581 #define REG_A6XX_PDC_GPU_TCS2_CONTROL				0x000015a4
7583 #define REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK			0x000015a5
7585 #define REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK		0x000015a6
7587 #define REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID			0x000015a7
7589 #define REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR				0x000015a8
7591 #define REG_A6XX_PDC_GPU_TCS2_CMD0_DATA				0x000015a9
7593 #define REG_A6XX_PDC_GPU_TCS3_CONTROL				0x000015d6
7595 #define REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK			0x000015d7
7597 #define REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK		0x000015d8
7599 #define REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID			0x000015d9
7601 #define REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR				0x000015da
7603 #define REG_A6XX_PDC_GPU_TCS3_CMD0_DATA				0x000015db
7605 #define REG_A6XX_PDC_GPU_SEQ_MEM_0				0x00000000
7607 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A			0x00000000
7608 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK		0x000000ff
7609 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT		0
7614 #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK	0x0000ff00
7621 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B			0x00000001
7623 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C			0x00000002
7625 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D			0x00000003
7627 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT			0x00000004
7628 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK		0x0000003f
7629 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT		0
7634 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK		0x00007000
7640 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK		0xf0000000
7647 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM			0x00000005
7648 #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK		0x0f000000
7655 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0			0x00000008
7657 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1			0x00000009
7659 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2			0x0000000a
7661 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3			0x0000000b
7663 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0			0x0000000c
7665 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1			0x0000000d
7667 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2			0x0000000e
7669 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3			0x0000000f
7671 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0			0x00000010
7672 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK		0x0000000f
7673 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT		0
7678 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK		0x000000f0
7684 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK		0x00000f00
7690 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK		0x0000f000
7696 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK		0x000f0000
7702 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK		0x00f00000
7708 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK		0x0f000000
7714 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK		0xf0000000
7721 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1			0x00000011
7722 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK		0x0000000f
7723 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT		0
7728 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK		0x000000f0
7734 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK		0x00000f00
7740 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK		0x0000f000
7746 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK		0x000f0000
7752 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK		0x00f00000
7758 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK		0x0f000000
7764 #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK		0xf0000000
7771 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1			0x0000002f
7773 #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2			0x00000030
7775 #define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0			0x00000001
7777 #define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1			0x00000002