1018 			gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(i)));  in a5xx_recover()
1025 	gpu_read(gpu, REG_A5XX_RBBM_SW_RESET_CMD);  in a5xx_recover()
1065 	if (gpu_read(gpu, REG_A5XX_RBBM_STATUS) & ~A5XX_RBBM_STATUS_HI_BUSY)  in _a5xx_check_idle()
1072 	return !(gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS) &  in _a5xx_check_idle()
1093 			gpu_read(gpu, REG_A5XX_RBBM_STATUS),  in a5xx_idle()
1094 			gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS),  in a5xx_idle()
1095 			gpu_read(gpu, REG_A5XX_CP_RB_RPTR),  in a5xx_idle()
1096 			gpu_read(gpu, REG_A5XX_CP_RB_WPTR));  in a5xx_idle()
1108 			gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(4)),  in a5xx_fault_handler()
1109 			gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(5)),  in a5xx_fault_handler()
1110 			gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(6)),  in a5xx_fault_handler()
1111 			gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(7)));  in a5xx_fault_handler()
1118 	u32 status = gpu_read(gpu, REG_A5XX_CP_INTERRUPT_STATUS);  in a5xx_cp_err_irq()
1130 		gpu_read(gpu, REG_A5XX_CP_PFP_STAT_DATA);  in a5xx_cp_err_irq()
1131 		val = gpu_read(gpu, REG_A5XX_CP_PFP_STAT_DATA);  in a5xx_cp_err_irq()
1139 			gpu_read(gpu, REG_A5XX_CP_HW_FAULT));  in a5xx_cp_err_irq()
1145 		u32 val = gpu_read(gpu, REG_A5XX_CP_PROTECT_STATUS);  in a5xx_cp_err_irq()
1154 		u32 status = gpu_read(gpu, REG_A5XX_CP_AHB_FAULT);  in a5xx_cp_err_irq()
1170 		u32 val = gpu_read(gpu, REG_A5XX_RBBM_AHB_ERROR_STATUS);  in a5xx_rbbm_err_irq()
1191 			gpu_read(gpu, REG_A5XX_RBBM_AHB_ME_SPLIT_STATUS));  in a5xx_rbbm_err_irq()
1195 			gpu_read(gpu, REG_A5XX_RBBM_AHB_PFP_SPLIT_STATUS));  in a5xx_rbbm_err_irq()
1199 			gpu_read(gpu, REG_A5XX_RBBM_AHB_ETS_SPLIT_STATUS));  in a5xx_rbbm_err_irq()
1210 	uint64_t addr = (uint64_t) gpu_read(gpu, REG_A5XX_UCHE_TRAP_LOG_HI);  in a5xx_uche_err_irq()
1212 	addr |= gpu_read(gpu, REG_A5XX_UCHE_TRAP_LOG_LO);  in a5xx_uche_err_irq()
1234 	if (gpu_read(gpu, REG_A5XX_RBBM_STATUS3) & BIT(24))  in a5xx_fault_detect_irq()
1239 		gpu_read(gpu, REG_A5XX_RBBM_STATUS),  in a5xx_fault_detect_irq()
1240 		gpu_read(gpu, REG_A5XX_CP_RB_RPTR),  in a5xx_fault_detect_irq()
1241 		gpu_read(gpu, REG_A5XX_CP_RB_WPTR),  in a5xx_fault_detect_irq()
1243 		gpu_read(gpu, REG_A5XX_CP_IB1_BUFSZ),  in a5xx_fault_detect_irq()
1245 		gpu_read(gpu, REG_A5XX_CP_IB2_BUFSZ));  in a5xx_fault_detect_irq()
1264 	u32 status = gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS);  in a5xx_irq()
1339 		gpu_read(gpu, REG_A5XX_RBBM_STATUS));  in a5xx_dump()
1374 			gpu_read(gpu, REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS));  in a5xx_pm_resume()
1403 	spin_until((gpu_read(gpu, REG_A5XX_VBIF_XIN_HALT_CTRL1) &  in a5xx_pm_suspend()
1567 	bool stalled = !!(gpu_read(gpu, REG_A5XX_RBBM_STATUS3) & BIT(24));  in a5xx_gpu_state_get()
1578 	a5xx_state->base.rbbm_status = gpu_read(gpu, REG_A5XX_RBBM_STATUS);  in a5xx_gpu_state_get()
1684 	return ring->memptrs->rptr = gpu_read(gpu, REG_A5XX_CP_RB_RPTR);  in a5xx_get_rptr()