28 		OUT_RING(ring, lower_32_bits(shadowptr(a5xx_gpu, ring)));  in update_shadow_rptr()
29 		OUT_RING(ring, upper_32_bits(shadowptr(a5xx_gpu, ring)));  in update_shadow_rptr()
103 				OUT_RING(ring, ptr[i]);  in a5xx_submit_in_rb()
138 	OUT_RING(ring, 0x02);  in a5xx_submit()
142 	OUT_RING(ring, 0);  in a5xx_submit()
146 	OUT_RING(ring, lower_32_bits(a5xx_gpu->preempt_iova[submit->ring->id]));  in a5xx_submit()
147 	OUT_RING(ring, upper_32_bits(a5xx_gpu->preempt_iova[submit->ring->id]));  in a5xx_submit()
151 	OUT_RING(ring, 1);  in a5xx_submit()
155 	OUT_RING(ring, 0x02);  in a5xx_submit()
159 	OUT_RING(ring, 0x02);  in a5xx_submit()
172 			OUT_RING(ring, lower_32_bits(submit->cmd[i].iova));  in a5xx_submit()
173 			OUT_RING(ring, upper_32_bits(submit->cmd[i].iova));  in a5xx_submit()
174 			OUT_RING(ring, submit->cmd[i].size);  in a5xx_submit()
196 	OUT_RING(ring, 0);  in a5xx_submit()
197 	OUT_RING(ring, 0);  in a5xx_submit()
198 	OUT_RING(ring, 0);  in a5xx_submit()
199 	OUT_RING(ring, 0);  in a5xx_submit()
200 	OUT_RING(ring, 0);  in a5xx_submit()
204 	OUT_RING(ring, 0x01);  in a5xx_submit()
208 	OUT_RING(ring, submit->seqno);  in a5xx_submit()
215 	OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(CACHE_FLUSH_TS) |  in a5xx_submit()
217 	OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence)));  in a5xx_submit()
218 	OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence)));  in a5xx_submit()
219 	OUT_RING(ring, submit->seqno);  in a5xx_submit()
228 	OUT_RING(ring, 0x00);  in a5xx_submit()
229 	OUT_RING(ring, 0x00);  in a5xx_submit()
231 	OUT_RING(ring, 0x01);  in a5xx_submit()
233 	OUT_RING(ring, 0x01);  in a5xx_submit()
473 	OUT_RING(ring, 0x0000002F);  in a5xx_me_init()
476 	OUT_RING(ring, 0x00000003);  in a5xx_me_init()
479 	OUT_RING(ring, 0x20000000);  in a5xx_me_init()
482 	OUT_RING(ring, 0x00000000);  in a5xx_me_init()
483 	OUT_RING(ring, 0x00000000);  in a5xx_me_init()
491 		OUT_RING(ring, 0x0000000B);  in a5xx_me_init()
494 		OUT_RING(ring, 0x00000001);  in a5xx_me_init()
497 		OUT_RING(ring, 0x00000000);  in a5xx_me_init()
500 	OUT_RING(ring, 0x00000000);  in a5xx_me_init()
501 	OUT_RING(ring, 0x00000000);  in a5xx_me_init()
518 	OUT_RING(ring, 0);  in a5xx_preempt_start()
522 	OUT_RING(ring, lower_32_bits(a5xx_gpu->preempt_iova[ring->id]));  in a5xx_preempt_start()
523 	OUT_RING(ring, upper_32_bits(a5xx_gpu->preempt_iova[ring->id]));  in a5xx_preempt_start()
527 	OUT_RING(ring, 1);  in a5xx_preempt_start()
530 	OUT_RING(ring, 0x00);  in a5xx_preempt_start()
533 	OUT_RING(ring, 0x01);  in a5xx_preempt_start()
536 	OUT_RING(ring, 0x01);  in a5xx_preempt_start()
540 	OUT_RING(ring, 0x00);  in a5xx_preempt_start()
541 	OUT_RING(ring, 0x00);  in a5xx_preempt_start()
542 	OUT_RING(ring, 0x01);  in a5xx_preempt_start()
543 	OUT_RING(ring, 0x01);  in a5xx_preempt_start()
967 		OUT_RING(gpu->rb[0], CP_EVENT_WRITE_0_EVENT(STAT_EVENT));  in a5xx_hw_init()
985 		OUT_RING(gpu->rb[0], 0x00000000);  in a5xx_hw_init()