100 	TILE5_LINEAR = 0,
261 	DEPTH5_NONE = 0,
268 	BLIT_MRT0 = 0,
281 	PERF_CP_ALWAYS_COUNT = 0,
315 	PERF_RBBM_ALWAYS_COUNT = 0,
332 	PERF_PC_BUSY_CYCLES = 0,
372 	PERF_VFD_BUSY_CYCLES = 0,
406 	PERF_HLSQ_BUSY_CYCLES = 0,
424 	PERF_VPC_BUSY_CYCLES = 0,
444 	PERF_TSE_BUSY_CYCLES = 0,
466 	PERF_RAS_BUSY_CYCLES = 0,
479 	PERF_LRZ_BUSY_CYCLES = 0,
501 	PERF_UCHE_BUSY_CYCLES = 0,
535 	PERF_TP_BUSY_CYCLES = 0,
580 	PERF_SP_BUSY_CYCLES = 0,
648 	PERF_RB_BUSY_CYCLES = 0,
681 	TOTAL_SAMPLES = 0,
688 	PERF_VSC_BUSY_CYCLES = 0,
695 	PERF_CCU_BUSY_CYCLES = 0,
724 	PERF_CMPDECMP_STALL_CYCLES_VBIF = 0,
751 	AXI_READ_REQUESTS_ID_0 = 0,
840 	A5XX_TEX_NEAREST = 0,
846 	A5XX_TEX_REPEAT = 0,
854 	A5XX_TEX_ANISO_1 = 0,
862 	A5XX_TEX_X = 0,
871 	A5XX_TEX_1D = 0,
878 #define A5XX_INT0_RBBM_GPU_IDLE					0x00000001
879 #define A5XX_INT0_RBBM_AHB_ERROR				0x00000002
880 #define A5XX_INT0_RBBM_TRANSFER_TIMEOUT				0x00000004
881 #define A5XX_INT0_RBBM_ME_MS_TIMEOUT				0x00000008
882 #define A5XX_INT0_RBBM_PFP_MS_TIMEOUT				0x00000010
883 #define A5XX_INT0_RBBM_ETS_MS_TIMEOUT				0x00000020
884 #define A5XX_INT0_RBBM_ATB_ASYNC_OVERFLOW			0x00000040
885 #define A5XX_INT0_RBBM_GPC_ERROR				0x00000080
886 #define A5XX_INT0_CP_SW						0x00000100
887 #define A5XX_INT0_CP_HW_ERROR					0x00000200
888 #define A5XX_INT0_CP_CCU_FLUSH_DEPTH_TS				0x00000400
889 #define A5XX_INT0_CP_CCU_FLUSH_COLOR_TS				0x00000800
890 #define A5XX_INT0_CP_CCU_RESOLVE_TS				0x00001000
891 #define A5XX_INT0_CP_IB2					0x00002000
892 #define A5XX_INT0_CP_IB1					0x00004000
893 #define A5XX_INT0_CP_RB						0x00008000
894 #define A5XX_INT0_CP_UNUSED_1					0x00010000
895 #define A5XX_INT0_CP_RB_DONE_TS					0x00020000
896 #define A5XX_INT0_CP_WT_DONE_TS					0x00040000
897 #define A5XX_INT0_UNKNOWN_1					0x00080000
898 #define A5XX_INT0_CP_CACHE_FLUSH_TS				0x00100000
899 #define A5XX_INT0_UNUSED_2					0x00200000
900 #define A5XX_INT0_RBBM_ATB_BUS_OVERFLOW				0x00400000
901 #define A5XX_INT0_MISC_HANG_DETECT				0x00800000
902 #define A5XX_INT0_UCHE_OOB_ACCESS				0x01000000
903 #define A5XX_INT0_UCHE_TRAP_INTR				0x02000000
904 #define A5XX_INT0_DEBBUS_INTR_0					0x04000000
905 #define A5XX_INT0_DEBBUS_INTR_1					0x08000000
906 #define A5XX_INT0_GPMU_VOLTAGE_DROOP				0x10000000
907 #define A5XX_INT0_GPMU_FIRMWARE					0x20000000
908 #define A5XX_INT0_ISDB_CPU_IRQ					0x40000000
909 #define A5XX_INT0_ISDB_UNDER_DEBUG				0x80000000
910 #define A5XX_CP_INT_CP_OPCODE_ERROR				0x00000001
911 #define A5XX_CP_INT_CP_RESERVED_BIT_ERROR			0x00000002
912 #define A5XX_CP_INT_CP_HW_FAULT_ERROR				0x00000004
913 #define A5XX_CP_INT_CP_DMA_ERROR				0x00000008
914 #define A5XX_CP_INT_CP_REGISTER_PROTECTION_ERROR		0x00000010
915 #define A5XX_CP_INT_CP_AHB_ERROR				0x00000020
916 #define REG_A5XX_CP_RB_BASE					0x00000800
918 #define REG_A5XX_CP_RB_BASE_HI					0x00000801
920 #define REG_A5XX_CP_RB_CNTL					0x00000802
922 #define REG_A5XX_CP_RB_RPTR_ADDR				0x00000804
924 #define REG_A5XX_CP_RB_RPTR_ADDR_HI				0x00000805
926 #define REG_A5XX_CP_RB_RPTR					0x00000806
928 #define REG_A5XX_CP_RB_WPTR					0x00000807
930 #define REG_A5XX_CP_PFP_STAT_ADDR				0x00000808
932 #define REG_A5XX_CP_PFP_STAT_DATA				0x00000809
934 #define REG_A5XX_CP_DRAW_STATE_ADDR				0x0000080b
936 #define REG_A5XX_CP_DRAW_STATE_DATA				0x0000080c
938 #define REG_A5XX_CP_ME_NRT_ADDR_LO				0x0000080d
940 #define REG_A5XX_CP_ME_NRT_ADDR_HI				0x0000080e
942 #define REG_A5XX_CP_ME_NRT_DATA					0x00000810
944 #define REG_A5XX_CP_CRASH_SCRIPT_BASE_LO			0x00000817
946 #define REG_A5XX_CP_CRASH_SCRIPT_BASE_HI			0x00000818
948 #define REG_A5XX_CP_CRASH_DUMP_CNTL				0x00000819
950 #define REG_A5XX_CP_ME_STAT_ADDR				0x0000081a
952 #define REG_A5XX_CP_ROQ_THRESHOLDS_1				0x0000081f
954 #define REG_A5XX_CP_ROQ_THRESHOLDS_2				0x00000820
956 #define REG_A5XX_CP_ROQ_DBG_ADDR				0x00000821
958 #define REG_A5XX_CP_ROQ_DBG_DATA				0x00000822
960 #define REG_A5XX_CP_MEQ_DBG_ADDR				0x00000823
962 #define REG_A5XX_CP_MEQ_DBG_DATA				0x00000824
964 #define REG_A5XX_CP_MEQ_THRESHOLDS				0x00000825
966 #define REG_A5XX_CP_MERCIU_SIZE					0x00000826
968 #define REG_A5XX_CP_MERCIU_DBG_ADDR				0x00000827
970 #define REG_A5XX_CP_MERCIU_DBG_DATA_1				0x00000828
972 #define REG_A5XX_CP_MERCIU_DBG_DATA_2				0x00000829
974 #define REG_A5XX_CP_PFP_UCODE_DBG_ADDR				0x0000082a
976 #define REG_A5XX_CP_PFP_UCODE_DBG_DATA				0x0000082b
978 #define REG_A5XX_CP_ME_UCODE_DBG_ADDR				0x0000082f
980 #define REG_A5XX_CP_ME_UCODE_DBG_DATA				0x00000830
982 #define REG_A5XX_CP_CNTL					0x00000831
984 #define REG_A5XX_CP_PFP_ME_CNTL					0x00000832
986 #define REG_A5XX_CP_CHICKEN_DBG					0x00000833
988 #define REG_A5XX_CP_PFP_INSTR_BASE_LO				0x00000835
990 #define REG_A5XX_CP_PFP_INSTR_BASE_HI				0x00000836
992 #define REG_A5XX_CP_ME_INSTR_BASE_LO				0x00000838
994 #define REG_A5XX_CP_ME_INSTR_BASE_HI				0x00000839
996 #define REG_A5XX_CP_CONTEXT_SWITCH_CNTL				0x0000083b
998 #define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_LO		0x0000083c
1000 #define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_HI		0x0000083d
1002 #define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_LO			0x0000083e
1004 #define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_HI			0x0000083f
1006 #define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO			0x00000840
1008 #define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI			0x00000841
1010 #define REG_A5XX_CP_ADDR_MODE_CNTL				0x00000860
1012 #define REG_A5XX_CP_ME_STAT_DATA				0x00000b14
1014 #define REG_A5XX_CP_WFI_PEND_CTR				0x00000b15
1016 #define REG_A5XX_CP_INTERRUPT_STATUS				0x00000b18
1018 #define REG_A5XX_CP_HW_FAULT					0x00000b1a
1020 #define REG_A5XX_CP_PROTECT_STATUS				0x00000b1c
1022 #define REG_A5XX_CP_IB1_BASE					0x00000b1f
1024 #define REG_A5XX_CP_IB1_BASE_HI					0x00000b20
1026 #define REG_A5XX_CP_IB1_BUFSZ					0x00000b21
1028 #define REG_A5XX_CP_IB2_BASE					0x00000b22
1030 #define REG_A5XX_CP_IB2_BASE_HI					0x00000b23
1032 #define REG_A5XX_CP_IB2_BUFSZ					0x00000b24
1034 static inline uint32_t REG_A5XX_CP_SCRATCH(uint32_t i0) { return 0x00000b78 + 0x1*i0; }  in REG_A5XX_CP_SCRATCH()
1036 static inline uint32_t REG_A5XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000b78 + 0x1*i0; }  in REG_A5XX_CP_SCRATCH_REG()
1038 static inline uint32_t REG_A5XX_CP_PROTECT(uint32_t i0) { return 0x00000880 + 0x1*i0; }  in REG_A5XX_CP_PROTECT()
1040 static inline uint32_t REG_A5XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000880 + 0x1*i0; }  in REG_A5XX_CP_PROTECT_REG()
1041 #define A5XX_CP_PROTECT_REG_BASE_ADDR__MASK			0x0001ffff
1042 #define A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT			0
1047 #define A5XX_CP_PROTECT_REG_MASK_LEN__MASK			0x1f000000
1053 #define A5XX_CP_PROTECT_REG_TRAP_WRITE__MASK			0x20000000
1059 #define A5XX_CP_PROTECT_REG_TRAP_READ__MASK			0x40000000
1066 #define REG_A5XX_CP_PROTECT_CNTL				0x000008a0
1068 #define REG_A5XX_CP_AHB_FAULT					0x00000b1b
1070 #define REG_A5XX_CP_PERFCTR_CP_SEL_0				0x00000bb0
1072 #define REG_A5XX_CP_PERFCTR_CP_SEL_1				0x00000bb1
1074 #define REG_A5XX_CP_PERFCTR_CP_SEL_2				0x00000bb2
1076 #define REG_A5XX_CP_PERFCTR_CP_SEL_3				0x00000bb3
1078 #define REG_A5XX_CP_PERFCTR_CP_SEL_4				0x00000bb4
1080 #define REG_A5XX_CP_PERFCTR_CP_SEL_5				0x00000bb5
1082 #define REG_A5XX_CP_PERFCTR_CP_SEL_6				0x00000bb6
1084 #define REG_A5XX_CP_PERFCTR_CP_SEL_7				0x00000bb7
1086 #define REG_A5XX_VSC_ADDR_MODE_CNTL				0x00000bc1
1088 #define REG_A5XX_CP_POWERCTR_CP_SEL_0				0x00000bba
1090 #define REG_A5XX_CP_POWERCTR_CP_SEL_1				0x00000bbb
1092 #define REG_A5XX_CP_POWERCTR_CP_SEL_2				0x00000bbc
1094 #define REG_A5XX_CP_POWERCTR_CP_SEL_3				0x00000bbd
1096 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_A				0x00000004
1098 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_B				0x00000005
1100 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_C				0x00000006
1102 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_D				0x00000007
1104 #define REG_A5XX_RBBM_CFG_DBGBUS_CNTLT				0x00000008
1106 #define REG_A5XX_RBBM_CFG_DBGBUS_CNTLM				0x00000009
1108 #define REG_A5XX_RBBM_CFG_DEBBUS_CTLTM_ENABLE_SHIFT		0x00000018
1110 #define REG_A5XX_RBBM_CFG_DBGBUS_OPL				0x0000000a
1112 #define REG_A5XX_RBBM_CFG_DBGBUS_OPE				0x0000000b
1114 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_0				0x0000000c
1116 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_1				0x0000000d
1118 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_2				0x0000000e
1120 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_3				0x0000000f
1122 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_0			0x00000010
1124 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_1			0x00000011
1126 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_2			0x00000012
1128 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_3			0x00000013
1130 #define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_0			0x00000014
1132 #define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_1			0x00000015
1134 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_0				0x00000016
1136 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_1				0x00000017
1138 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_2				0x00000018
1140 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_3				0x00000019
1142 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_0			0x0000001a
1144 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_1			0x0000001b
1146 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_2			0x0000001c
1148 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_3			0x0000001d
1150 #define REG_A5XX_RBBM_CFG_DBGBUS_NIBBLEE			0x0000001e
1152 #define REG_A5XX_RBBM_CFG_DBGBUS_PTRC0				0x0000001f
1154 #define REG_A5XX_RBBM_CFG_DBGBUS_PTRC1				0x00000020
1156 #define REG_A5XX_RBBM_CFG_DBGBUS_LOADREG			0x00000021
1158 #define REG_A5XX_RBBM_CFG_DBGBUS_IDX				0x00000022
1160 #define REG_A5XX_RBBM_CFG_DBGBUS_CLRC				0x00000023
1162 #define REG_A5XX_RBBM_CFG_DBGBUS_LOADIVT			0x00000024
1164 #define REG_A5XX_RBBM_INTERFACE_HANG_INT_CNTL			0x0000002f
1166 #define REG_A5XX_RBBM_INT_CLEAR_CMD				0x00000037
1168 #define REG_A5XX_RBBM_INT_0_MASK				0x00000038
1169 #define A5XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE			0x00000001
1170 #define A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR			0x00000002
1171 #define A5XX_RBBM_INT_0_MASK_RBBM_TRANSFER_TIMEOUT		0x00000004
1172 #define A5XX_RBBM_INT_0_MASK_RBBM_ME_MS_TIMEOUT			0x00000008
1173 #define A5XX_RBBM_INT_0_MASK_RBBM_PFP_MS_TIMEOUT		0x00000010
1174 #define A5XX_RBBM_INT_0_MASK_RBBM_ETS_MS_TIMEOUT		0x00000020
1175 #define A5XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNC_OVERFLOW		0x00000040
1176 #define A5XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR			0x00000080
1177 #define A5XX_RBBM_INT_0_MASK_CP_SW				0x00000100
1178 #define A5XX_RBBM_INT_0_MASK_CP_HW_ERROR			0x00000200
1179 #define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS		0x00000400
1180 #define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS		0x00000800
1181 #define A5XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS			0x00001000
1182 #define A5XX_RBBM_INT_0_MASK_CP_IB2				0x00002000
1183 #define A5XX_RBBM_INT_0_MASK_CP_IB1				0x00004000
1184 #define A5XX_RBBM_INT_0_MASK_CP_RB				0x00008000
1185 #define A5XX_RBBM_INT_0_MASK_CP_RB_DONE_TS			0x00020000
1186 #define A5XX_RBBM_INT_0_MASK_CP_WT_DONE_TS			0x00040000
1187 #define A5XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS			0x00100000
1188 #define A5XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW		0x00400000
1189 #define A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT			0x00800000
1190 #define A5XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS			0x01000000
1191 #define A5XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR			0x02000000
1192 #define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_0			0x04000000
1193 #define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_1			0x08000000
1194 #define A5XX_RBBM_INT_0_MASK_GPMU_VOLTAGE_DROOP			0x10000000
1195 #define A5XX_RBBM_INT_0_MASK_GPMU_FIRMWARE			0x20000000
1196 #define A5XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ			0x40000000
1197 #define A5XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG			0x80000000
1199 #define REG_A5XX_RBBM_AHB_DBG_CNTL				0x0000003f
1201 #define REG_A5XX_RBBM_EXT_VBIF_DBG_CNTL				0x00000041
1203 #define REG_A5XX_RBBM_SW_RESET_CMD				0x00000043
1205 #define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD			0x00000045
1207 #define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD2			0x00000046
1209 #define REG_A5XX_RBBM_DBG_LO_HI_GPIO				0x00000048
1211 #define REG_A5XX_RBBM_EXT_TRACE_BUS_CNTL			0x00000049
1213 #define REG_A5XX_RBBM_CLOCK_CNTL_TP0				0x0000004a
1215 #define REG_A5XX_RBBM_CLOCK_CNTL_TP1				0x0000004b
1217 #define REG_A5XX_RBBM_CLOCK_CNTL_TP2				0x0000004c
1219 #define REG_A5XX_RBBM_CLOCK_CNTL_TP3				0x0000004d
1221 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP0				0x0000004e
1223 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP1				0x0000004f
1225 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP2				0x00000050
1227 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP3				0x00000051
1229 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP0				0x00000052
1231 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP1				0x00000053
1233 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP2				0x00000054
1235 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP3				0x00000055
1237 #define REG_A5XX_RBBM_READ_AHB_THROUGH_DBG			0x00000059
1239 #define REG_A5XX_RBBM_CLOCK_CNTL_UCHE				0x0000005a
1241 #define REG_A5XX_RBBM_CLOCK_CNTL2_UCHE				0x0000005b
1243 #define REG_A5XX_RBBM_CLOCK_CNTL3_UCHE				0x0000005c
1245 #define REG_A5XX_RBBM_CLOCK_CNTL4_UCHE				0x0000005d
1247 #define REG_A5XX_RBBM_CLOCK_HYST_UCHE				0x0000005e
1249 #define REG_A5XX_RBBM_CLOCK_DELAY_UCHE				0x0000005f
1251 #define REG_A5XX_RBBM_CLOCK_MODE_GPC				0x00000060
1253 #define REG_A5XX_RBBM_CLOCK_DELAY_GPC				0x00000061
1255 #define REG_A5XX_RBBM_CLOCK_HYST_GPC				0x00000062
1257 #define REG_A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM			0x00000063
1259 #define REG_A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM			0x00000064
1261 #define REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM			0x00000065
1263 #define REG_A5XX_RBBM_CLOCK_DELAY_HLSQ				0x00000066
1265 #define REG_A5XX_RBBM_CLOCK_CNTL				0x00000067
1267 #define REG_A5XX_RBBM_CLOCK_CNTL_SP0				0x00000068
1269 #define REG_A5XX_RBBM_CLOCK_CNTL_SP1				0x00000069
1271 #define REG_A5XX_RBBM_CLOCK_CNTL_SP2				0x0000006a
1273 #define REG_A5XX_RBBM_CLOCK_CNTL_SP3				0x0000006b
1275 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP0				0x0000006c
1277 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP1				0x0000006d
1279 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP2				0x0000006e
1281 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP3				0x0000006f
1283 #define REG_A5XX_RBBM_CLOCK_HYST_SP0				0x00000070
1285 #define REG_A5XX_RBBM_CLOCK_HYST_SP1				0x00000071
1287 #define REG_A5XX_RBBM_CLOCK_HYST_SP2				0x00000072
1289 #define REG_A5XX_RBBM_CLOCK_HYST_SP3				0x00000073
1291 #define REG_A5XX_RBBM_CLOCK_DELAY_SP0				0x00000074
1293 #define REG_A5XX_RBBM_CLOCK_DELAY_SP1				0x00000075
1295 #define REG_A5XX_RBBM_CLOCK_DELAY_SP2				0x00000076
1297 #define REG_A5XX_RBBM_CLOCK_DELAY_SP3				0x00000077
1299 #define REG_A5XX_RBBM_CLOCK_CNTL_RB0				0x00000078
1301 #define REG_A5XX_RBBM_CLOCK_CNTL_RB1				0x00000079
1303 #define REG_A5XX_RBBM_CLOCK_CNTL_RB2				0x0000007a
1305 #define REG_A5XX_RBBM_CLOCK_CNTL_RB3				0x0000007b
1307 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB0				0x0000007c
1309 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB1				0x0000007d
1311 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB2				0x0000007e
1313 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB3				0x0000007f
1315 #define REG_A5XX_RBBM_CLOCK_HYST_RAC				0x00000080
1317 #define REG_A5XX_RBBM_CLOCK_DELAY_RAC				0x00000081
1319 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU0				0x00000082
1321 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU1				0x00000083
1323 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU2				0x00000084
1325 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU3				0x00000085
1327 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU0			0x00000086
1329 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU1			0x00000087
1331 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU2			0x00000088
1333 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU3			0x00000089
1335 #define REG_A5XX_RBBM_CLOCK_CNTL_RAC				0x0000008a
1337 #define REG_A5XX_RBBM_CLOCK_CNTL2_RAC				0x0000008b
1339 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0			0x0000008c
1341 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_1			0x0000008d
1343 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_2			0x0000008e
1345 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_3			0x0000008f
1347 #define REG_A5XX_RBBM_CLOCK_HYST_VFD				0x00000090
1349 #define REG_A5XX_RBBM_CLOCK_MODE_VFD				0x00000091
1351 #define REG_A5XX_RBBM_CLOCK_DELAY_VFD				0x00000092
1353 #define REG_A5XX_RBBM_AHB_CNTL0					0x00000093
1355 #define REG_A5XX_RBBM_AHB_CNTL1					0x00000094
1357 #define REG_A5XX_RBBM_AHB_CNTL2					0x00000095
1359 #define REG_A5XX_RBBM_AHB_CMD					0x00000096
1361 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL11		0x0000009c
1363 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL12		0x0000009d
1365 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL13		0x0000009e
1367 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL14		0x0000009f
1369 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL15		0x000000a0
1371 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL16		0x000000a1
1373 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL17		0x000000a2
1375 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL18		0x000000a3
1377 #define REG_A5XX_RBBM_CLOCK_DELAY_TP0				0x000000a4
1379 #define REG_A5XX_RBBM_CLOCK_DELAY_TP1				0x000000a5
1381 #define REG_A5XX_RBBM_CLOCK_DELAY_TP2				0x000000a6
1383 #define REG_A5XX_RBBM_CLOCK_DELAY_TP3				0x000000a7
1385 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP0				0x000000a8
1387 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP1				0x000000a9
1389 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP2				0x000000aa
1391 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP3				0x000000ab
1393 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP0				0x000000ac
1395 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP1				0x000000ad
1397 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP2				0x000000ae
1399 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP3				0x000000af
1401 #define REG_A5XX_RBBM_CLOCK_HYST_TP0				0x000000b0
1403 #define REG_A5XX_RBBM_CLOCK_HYST_TP1				0x000000b1
1405 #define REG_A5XX_RBBM_CLOCK_HYST_TP2				0x000000b2
1407 #define REG_A5XX_RBBM_CLOCK_HYST_TP3				0x000000b3
1409 #define REG_A5XX_RBBM_CLOCK_HYST2_TP0				0x000000b4
1411 #define REG_A5XX_RBBM_CLOCK_HYST2_TP1				0x000000b5
1413 #define REG_A5XX_RBBM_CLOCK_HYST2_TP2				0x000000b6
1415 #define REG_A5XX_RBBM_CLOCK_HYST2_TP3				0x000000b7
1417 #define REG_A5XX_RBBM_CLOCK_HYST3_TP0				0x000000b8
1419 #define REG_A5XX_RBBM_CLOCK_HYST3_TP1				0x000000b9
1421 #define REG_A5XX_RBBM_CLOCK_HYST3_TP2				0x000000ba
1423 #define REG_A5XX_RBBM_CLOCK_HYST3_TP3				0x000000bb
1425 #define REG_A5XX_RBBM_CLOCK_CNTL_GPMU				0x000000c8
1427 #define REG_A5XX_RBBM_CLOCK_DELAY_GPMU				0x000000c9
1429 #define REG_A5XX_RBBM_CLOCK_HYST_GPMU				0x000000ca
1431 #define REG_A5XX_RBBM_PERFCTR_CP_0_LO				0x000003a0
1433 #define REG_A5XX_RBBM_PERFCTR_CP_0_HI				0x000003a1
1435 #define REG_A5XX_RBBM_PERFCTR_CP_1_LO				0x000003a2
1437 #define REG_A5XX_RBBM_PERFCTR_CP_1_HI				0x000003a3
1439 #define REG_A5XX_RBBM_PERFCTR_CP_2_LO				0x000003a4
1441 #define REG_A5XX_RBBM_PERFCTR_CP_2_HI				0x000003a5
1443 #define REG_A5XX_RBBM_PERFCTR_CP_3_LO				0x000003a6
1445 #define REG_A5XX_RBBM_PERFCTR_CP_3_HI				0x000003a7
1447 #define REG_A5XX_RBBM_PERFCTR_CP_4_LO				0x000003a8
1449 #define REG_A5XX_RBBM_PERFCTR_CP_4_HI				0x000003a9
1451 #define REG_A5XX_RBBM_PERFCTR_CP_5_LO				0x000003aa
1453 #define REG_A5XX_RBBM_PERFCTR_CP_5_HI				0x000003ab
1455 #define REG_A5XX_RBBM_PERFCTR_CP_6_LO				0x000003ac
1457 #define REG_A5XX_RBBM_PERFCTR_CP_6_HI				0x000003ad
1459 #define REG_A5XX_RBBM_PERFCTR_CP_7_LO				0x000003ae
1461 #define REG_A5XX_RBBM_PERFCTR_CP_7_HI				0x000003af
1463 #define REG_A5XX_RBBM_PERFCTR_RBBM_0_LO				0x000003b0
1465 #define REG_A5XX_RBBM_PERFCTR_RBBM_0_HI				0x000003b1
1467 #define REG_A5XX_RBBM_PERFCTR_RBBM_1_LO				0x000003b2
1469 #define REG_A5XX_RBBM_PERFCTR_RBBM_1_HI				0x000003b3
1471 #define REG_A5XX_RBBM_PERFCTR_RBBM_2_LO				0x000003b4
1473 #define REG_A5XX_RBBM_PERFCTR_RBBM_2_HI				0x000003b5
1475 #define REG_A5XX_RBBM_PERFCTR_RBBM_3_LO				0x000003b6
1477 #define REG_A5XX_RBBM_PERFCTR_RBBM_3_HI				0x000003b7
1479 #define REG_A5XX_RBBM_PERFCTR_PC_0_LO				0x000003b8
1481 #define REG_A5XX_RBBM_PERFCTR_PC_0_HI				0x000003b9
1483 #define REG_A5XX_RBBM_PERFCTR_PC_1_LO				0x000003ba
1485 #define REG_A5XX_RBBM_PERFCTR_PC_1_HI				0x000003bb
1487 #define REG_A5XX_RBBM_PERFCTR_PC_2_LO				0x000003bc
1489 #define REG_A5XX_RBBM_PERFCTR_PC_2_HI				0x000003bd
1491 #define REG_A5XX_RBBM_PERFCTR_PC_3_LO				0x000003be
1493 #define REG_A5XX_RBBM_PERFCTR_PC_3_HI				0x000003bf
1495 #define REG_A5XX_RBBM_PERFCTR_PC_4_LO				0x000003c0
1497 #define REG_A5XX_RBBM_PERFCTR_PC_4_HI				0x000003c1
1499 #define REG_A5XX_RBBM_PERFCTR_PC_5_LO				0x000003c2
1501 #define REG_A5XX_RBBM_PERFCTR_PC_5_HI				0x000003c3
1503 #define REG_A5XX_RBBM_PERFCTR_PC_6_LO				0x000003c4
1505 #define REG_A5XX_RBBM_PERFCTR_PC_6_HI				0x000003c5
1507 #define REG_A5XX_RBBM_PERFCTR_PC_7_LO				0x000003c6
1509 #define REG_A5XX_RBBM_PERFCTR_PC_7_HI				0x000003c7
1511 #define REG_A5XX_RBBM_PERFCTR_VFD_0_LO				0x000003c8
1513 #define REG_A5XX_RBBM_PERFCTR_VFD_0_HI				0x000003c9
1515 #define REG_A5XX_RBBM_PERFCTR_VFD_1_LO				0x000003ca
1517 #define REG_A5XX_RBBM_PERFCTR_VFD_1_HI				0x000003cb
1519 #define REG_A5XX_RBBM_PERFCTR_VFD_2_LO				0x000003cc
1521 #define REG_A5XX_RBBM_PERFCTR_VFD_2_HI				0x000003cd
1523 #define REG_A5XX_RBBM_PERFCTR_VFD_3_LO				0x000003ce
1525 #define REG_A5XX_RBBM_PERFCTR_VFD_3_HI				0x000003cf
1527 #define REG_A5XX_RBBM_PERFCTR_VFD_4_LO				0x000003d0
1529 #define REG_A5XX_RBBM_PERFCTR_VFD_4_HI				0x000003d1
1531 #define REG_A5XX_RBBM_PERFCTR_VFD_5_LO				0x000003d2
1533 #define REG_A5XX_RBBM_PERFCTR_VFD_5_HI				0x000003d3
1535 #define REG_A5XX_RBBM_PERFCTR_VFD_6_LO				0x000003d4
1537 #define REG_A5XX_RBBM_PERFCTR_VFD_6_HI				0x000003d5
1539 #define REG_A5XX_RBBM_PERFCTR_VFD_7_LO				0x000003d6
1541 #define REG_A5XX_RBBM_PERFCTR_VFD_7_HI				0x000003d7
1543 #define REG_A5XX_RBBM_PERFCTR_HLSQ_0_LO				0x000003d8
1545 #define REG_A5XX_RBBM_PERFCTR_HLSQ_0_HI				0x000003d9
1547 #define REG_A5XX_RBBM_PERFCTR_HLSQ_1_LO				0x000003da
1549 #define REG_A5XX_RBBM_PERFCTR_HLSQ_1_HI				0x000003db
1551 #define REG_A5XX_RBBM_PERFCTR_HLSQ_2_LO				0x000003dc
1553 #define REG_A5XX_RBBM_PERFCTR_HLSQ_2_HI				0x000003dd
1555 #define REG_A5XX_RBBM_PERFCTR_HLSQ_3_LO				0x000003de
1557 #define REG_A5XX_RBBM_PERFCTR_HLSQ_3_HI				0x000003df
1559 #define REG_A5XX_RBBM_PERFCTR_HLSQ_4_LO				0x000003e0
1561 #define REG_A5XX_RBBM_PERFCTR_HLSQ_4_HI				0x000003e1
1563 #define REG_A5XX_RBBM_PERFCTR_HLSQ_5_LO				0x000003e2
1565 #define REG_A5XX_RBBM_PERFCTR_HLSQ_5_HI				0x000003e3
1567 #define REG_A5XX_RBBM_PERFCTR_HLSQ_6_LO				0x000003e4
1569 #define REG_A5XX_RBBM_PERFCTR_HLSQ_6_HI				0x000003e5
1571 #define REG_A5XX_RBBM_PERFCTR_HLSQ_7_LO				0x000003e6
1573 #define REG_A5XX_RBBM_PERFCTR_HLSQ_7_HI				0x000003e7
1575 #define REG_A5XX_RBBM_PERFCTR_VPC_0_LO				0x000003e8
1577 #define REG_A5XX_RBBM_PERFCTR_VPC_0_HI				0x000003e9
1579 #define REG_A5XX_RBBM_PERFCTR_VPC_1_LO				0x000003ea
1581 #define REG_A5XX_RBBM_PERFCTR_VPC_1_HI				0x000003eb
1583 #define REG_A5XX_RBBM_PERFCTR_VPC_2_LO				0x000003ec
1585 #define REG_A5XX_RBBM_PERFCTR_VPC_2_HI				0x000003ed
1587 #define REG_A5XX_RBBM_PERFCTR_VPC_3_LO				0x000003ee
1589 #define REG_A5XX_RBBM_PERFCTR_VPC_3_HI				0x000003ef
1591 #define REG_A5XX_RBBM_PERFCTR_CCU_0_LO				0x000003f0
1593 #define REG_A5XX_RBBM_PERFCTR_CCU_0_HI				0x000003f1
1595 #define REG_A5XX_RBBM_PERFCTR_CCU_1_LO				0x000003f2
1597 #define REG_A5XX_RBBM_PERFCTR_CCU_1_HI				0x000003f3
1599 #define REG_A5XX_RBBM_PERFCTR_CCU_2_LO				0x000003f4
1601 #define REG_A5XX_RBBM_PERFCTR_CCU_2_HI				0x000003f5
1603 #define REG_A5XX_RBBM_PERFCTR_CCU_3_LO				0x000003f6
1605 #define REG_A5XX_RBBM_PERFCTR_CCU_3_HI				0x000003f7
1607 #define REG_A5XX_RBBM_PERFCTR_TSE_0_LO				0x000003f8
1609 #define REG_A5XX_RBBM_PERFCTR_TSE_0_HI				0x000003f9
1611 #define REG_A5XX_RBBM_PERFCTR_TSE_1_LO				0x000003fa
1613 #define REG_A5XX_RBBM_PERFCTR_TSE_1_HI				0x000003fb
1615 #define REG_A5XX_RBBM_PERFCTR_TSE_2_LO				0x000003fc
1617 #define REG_A5XX_RBBM_PERFCTR_TSE_2_HI				0x000003fd
1619 #define REG_A5XX_RBBM_PERFCTR_TSE_3_LO				0x000003fe
1621 #define REG_A5XX_RBBM_PERFCTR_TSE_3_HI				0x000003ff
1623 #define REG_A5XX_RBBM_PERFCTR_RAS_0_LO				0x00000400
1625 #define REG_A5XX_RBBM_PERFCTR_RAS_0_HI				0x00000401
1627 #define REG_A5XX_RBBM_PERFCTR_RAS_1_LO				0x00000402
1629 #define REG_A5XX_RBBM_PERFCTR_RAS_1_HI				0x00000403
1631 #define REG_A5XX_RBBM_PERFCTR_RAS_2_LO				0x00000404
1633 #define REG_A5XX_RBBM_PERFCTR_RAS_2_HI				0x00000405
1635 #define REG_A5XX_RBBM_PERFCTR_RAS_3_LO				0x00000406
1637 #define REG_A5XX_RBBM_PERFCTR_RAS_3_HI				0x00000407
1639 #define REG_A5XX_RBBM_PERFCTR_UCHE_0_LO				0x00000408
1641 #define REG_A5XX_RBBM_PERFCTR_UCHE_0_HI				0x00000409
1643 #define REG_A5XX_RBBM_PERFCTR_UCHE_1_LO				0x0000040a
1645 #define REG_A5XX_RBBM_PERFCTR_UCHE_1_HI				0x0000040b
1647 #define REG_A5XX_RBBM_PERFCTR_UCHE_2_LO				0x0000040c
1649 #define REG_A5XX_RBBM_PERFCTR_UCHE_2_HI				0x0000040d
1651 #define REG_A5XX_RBBM_PERFCTR_UCHE_3_LO				0x0000040e
1653 #define REG_A5XX_RBBM_PERFCTR_UCHE_3_HI				0x0000040f
1655 #define REG_A5XX_RBBM_PERFCTR_UCHE_4_LO				0x00000410
1657 #define REG_A5XX_RBBM_PERFCTR_UCHE_4_HI				0x00000411
1659 #define REG_A5XX_RBBM_PERFCTR_UCHE_5_LO				0x00000412
1661 #define REG_A5XX_RBBM_PERFCTR_UCHE_5_HI				0x00000413
1663 #define REG_A5XX_RBBM_PERFCTR_UCHE_6_LO				0x00000414
1665 #define REG_A5XX_RBBM_PERFCTR_UCHE_6_HI				0x00000415
1667 #define REG_A5XX_RBBM_PERFCTR_UCHE_7_LO				0x00000416
1669 #define REG_A5XX_RBBM_PERFCTR_UCHE_7_HI				0x00000417
1671 #define REG_A5XX_RBBM_PERFCTR_TP_0_LO				0x00000418
1673 #define REG_A5XX_RBBM_PERFCTR_TP_0_HI				0x00000419
1675 #define REG_A5XX_RBBM_PERFCTR_TP_1_LO				0x0000041a
1677 #define REG_A5XX_RBBM_PERFCTR_TP_1_HI				0x0000041b
1679 #define REG_A5XX_RBBM_PERFCTR_TP_2_LO				0x0000041c
1681 #define REG_A5XX_RBBM_PERFCTR_TP_2_HI				0x0000041d
1683 #define REG_A5XX_RBBM_PERFCTR_TP_3_LO				0x0000041e
1685 #define REG_A5XX_RBBM_PERFCTR_TP_3_HI				0x0000041f
1687 #define REG_A5XX_RBBM_PERFCTR_TP_4_LO				0x00000420
1689 #define REG_A5XX_RBBM_PERFCTR_TP_4_HI				0x00000421
1691 #define REG_A5XX_RBBM_PERFCTR_TP_5_LO				0x00000422
1693 #define REG_A5XX_RBBM_PERFCTR_TP_5_HI				0x00000423
1695 #define REG_A5XX_RBBM_PERFCTR_TP_6_LO				0x00000424
1697 #define REG_A5XX_RBBM_PERFCTR_TP_6_HI				0x00000425
1699 #define REG_A5XX_RBBM_PERFCTR_TP_7_LO				0x00000426
1701 #define REG_A5XX_RBBM_PERFCTR_TP_7_HI				0x00000427
1703 #define REG_A5XX_RBBM_PERFCTR_SP_0_LO				0x00000428
1705 #define REG_A5XX_RBBM_PERFCTR_SP_0_HI				0x00000429
1707 #define REG_A5XX_RBBM_PERFCTR_SP_1_LO				0x0000042a
1709 #define REG_A5XX_RBBM_PERFCTR_SP_1_HI				0x0000042b
1711 #define REG_A5XX_RBBM_PERFCTR_SP_2_LO				0x0000042c
1713 #define REG_A5XX_RBBM_PERFCTR_SP_2_HI				0x0000042d
1715 #define REG_A5XX_RBBM_PERFCTR_SP_3_LO				0x0000042e
1717 #define REG_A5XX_RBBM_PERFCTR_SP_3_HI				0x0000042f
1719 #define REG_A5XX_RBBM_PERFCTR_SP_4_LO				0x00000430
1721 #define REG_A5XX_RBBM_PERFCTR_SP_4_HI				0x00000431
1723 #define REG_A5XX_RBBM_PERFCTR_SP_5_LO				0x00000432
1725 #define REG_A5XX_RBBM_PERFCTR_SP_5_HI				0x00000433
1727 #define REG_A5XX_RBBM_PERFCTR_SP_6_LO				0x00000434
1729 #define REG_A5XX_RBBM_PERFCTR_SP_6_HI				0x00000435
1731 #define REG_A5XX_RBBM_PERFCTR_SP_7_LO				0x00000436
1733 #define REG_A5XX_RBBM_PERFCTR_SP_7_HI				0x00000437
1735 #define REG_A5XX_RBBM_PERFCTR_SP_8_LO				0x00000438
1737 #define REG_A5XX_RBBM_PERFCTR_SP_8_HI				0x00000439
1739 #define REG_A5XX_RBBM_PERFCTR_SP_9_LO				0x0000043a
1741 #define REG_A5XX_RBBM_PERFCTR_SP_9_HI				0x0000043b
1743 #define REG_A5XX_RBBM_PERFCTR_SP_10_LO				0x0000043c
1745 #define REG_A5XX_RBBM_PERFCTR_SP_10_HI				0x0000043d
1747 #define REG_A5XX_RBBM_PERFCTR_SP_11_LO				0x0000043e
1749 #define REG_A5XX_RBBM_PERFCTR_SP_11_HI				0x0000043f
1751 #define REG_A5XX_RBBM_PERFCTR_RB_0_LO				0x00000440
1753 #define REG_A5XX_RBBM_PERFCTR_RB_0_HI				0x00000441
1755 #define REG_A5XX_RBBM_PERFCTR_RB_1_LO				0x00000442
1757 #define REG_A5XX_RBBM_PERFCTR_RB_1_HI				0x00000443
1759 #define REG_A5XX_RBBM_PERFCTR_RB_2_LO				0x00000444
1761 #define REG_A5XX_RBBM_PERFCTR_RB_2_HI				0x00000445
1763 #define REG_A5XX_RBBM_PERFCTR_RB_3_LO				0x00000446
1765 #define REG_A5XX_RBBM_PERFCTR_RB_3_HI				0x00000447
1767 #define REG_A5XX_RBBM_PERFCTR_RB_4_LO				0x00000448
1769 #define REG_A5XX_RBBM_PERFCTR_RB_4_HI				0x00000449
1771 #define REG_A5XX_RBBM_PERFCTR_RB_5_LO				0x0000044a
1773 #define REG_A5XX_RBBM_PERFCTR_RB_5_HI				0x0000044b
1775 #define REG_A5XX_RBBM_PERFCTR_RB_6_LO				0x0000044c
1777 #define REG_A5XX_RBBM_PERFCTR_RB_6_HI				0x0000044d
1779 #define REG_A5XX_RBBM_PERFCTR_RB_7_LO				0x0000044e
1781 #define REG_A5XX_RBBM_PERFCTR_RB_7_HI				0x0000044f
1783 #define REG_A5XX_RBBM_PERFCTR_VSC_0_LO				0x00000450
1785 #define REG_A5XX_RBBM_PERFCTR_VSC_0_HI				0x00000451
1787 #define REG_A5XX_RBBM_PERFCTR_VSC_1_LO				0x00000452
1789 #define REG_A5XX_RBBM_PERFCTR_VSC_1_HI				0x00000453
1791 #define REG_A5XX_RBBM_PERFCTR_LRZ_0_LO				0x00000454
1793 #define REG_A5XX_RBBM_PERFCTR_LRZ_0_HI				0x00000455
1795 #define REG_A5XX_RBBM_PERFCTR_LRZ_1_LO				0x00000456
1797 #define REG_A5XX_RBBM_PERFCTR_LRZ_1_HI				0x00000457
1799 #define REG_A5XX_RBBM_PERFCTR_LRZ_2_LO				0x00000458
1801 #define REG_A5XX_RBBM_PERFCTR_LRZ_2_HI				0x00000459
1803 #define REG_A5XX_RBBM_PERFCTR_LRZ_3_LO				0x0000045a
1805 #define REG_A5XX_RBBM_PERFCTR_LRZ_3_HI				0x0000045b
1807 #define REG_A5XX_RBBM_PERFCTR_CMP_0_LO				0x0000045c
1809 #define REG_A5XX_RBBM_PERFCTR_CMP_0_HI				0x0000045d
1811 #define REG_A5XX_RBBM_PERFCTR_CMP_1_LO				0x0000045e
1813 #define REG_A5XX_RBBM_PERFCTR_CMP_1_HI				0x0000045f
1815 #define REG_A5XX_RBBM_PERFCTR_CMP_2_LO				0x00000460
1817 #define REG_A5XX_RBBM_PERFCTR_CMP_2_HI				0x00000461
1819 #define REG_A5XX_RBBM_PERFCTR_CMP_3_LO				0x00000462
1821 #define REG_A5XX_RBBM_PERFCTR_CMP_3_HI				0x00000463
1823 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0			0x0000046b
1825 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_1			0x0000046c
1827 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_2			0x0000046d
1829 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_3			0x0000046e
1831 #define REG_A5XX_RBBM_ALWAYSON_COUNTER_LO			0x000004d2
1833 #define REG_A5XX_RBBM_ALWAYSON_COUNTER_HI			0x000004d3
1835 #define REG_A5XX_RBBM_STATUS					0x000004f5
1836 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__MASK			0x80000000
1842 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP__MASK		0x40000000
1848 #define A5XX_RBBM_STATUS_HLSQ_BUSY__MASK			0x20000000
1854 #define A5XX_RBBM_STATUS_VSC_BUSY__MASK				0x10000000
1860 #define A5XX_RBBM_STATUS_TPL1_BUSY__MASK			0x08000000
1866 #define A5XX_RBBM_STATUS_SP_BUSY__MASK				0x04000000
1872 #define A5XX_RBBM_STATUS_UCHE_BUSY__MASK			0x02000000
1878 #define A5XX_RBBM_STATUS_VPC_BUSY__MASK				0x01000000
1884 #define A5XX_RBBM_STATUS_VFDP_BUSY__MASK			0x00800000
1890 #define A5XX_RBBM_STATUS_VFD_BUSY__MASK				0x00400000
1896 #define A5XX_RBBM_STATUS_TESS_BUSY__MASK			0x00200000
1902 #define A5XX_RBBM_STATUS_PC_VSD_BUSY__MASK			0x00100000
1908 #define A5XX_RBBM_STATUS_PC_DCALL_BUSY__MASK			0x00080000
1914 #define A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY__MASK			0x00040000
1920 #define A5XX_RBBM_STATUS_DCOM_BUSY__MASK			0x00020000
1926 #define A5XX_RBBM_STATUS_COM_BUSY__MASK				0x00010000
1932 #define A5XX_RBBM_STATUS_LRZ_BUZY__MASK				0x00008000
1938 #define A5XX_RBBM_STATUS_A2D_DSP_BUSY__MASK			0x00004000
1944 #define A5XX_RBBM_STATUS_CCUFCHE_BUSY__MASK			0x00002000
1950 #define A5XX_RBBM_STATUS_RB_BUSY__MASK				0x00001000
1956 #define A5XX_RBBM_STATUS_RAS_BUSY__MASK				0x00000800
1962 #define A5XX_RBBM_STATUS_TSE_BUSY__MASK				0x00000400
1968 #define A5XX_RBBM_STATUS_VBIF_BUSY__MASK			0x00000200
1974 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST__MASK		0x00000100
1980 #define A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST__MASK			0x00000080
1986 #define A5XX_RBBM_STATUS_CP_BUSY__MASK				0x00000040
1992 #define A5XX_RBBM_STATUS_GPMU_MASTER_BUSY__MASK			0x00000020
1998 #define A5XX_RBBM_STATUS_CP_CRASH_BUSY__MASK			0x00000010
2004 #define A5XX_RBBM_STATUS_CP_ETS_BUSY__MASK			0x00000008
2010 #define A5XX_RBBM_STATUS_CP_PFP_BUSY__MASK			0x00000004
2016 #define A5XX_RBBM_STATUS_CP_ME_BUSY__MASK			0x00000002
2022 #define A5XX_RBBM_STATUS_HI_BUSY				0x00000001
2024 #define REG_A5XX_RBBM_STATUS3					0x00000530
2025 #define A5XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT			0x01000000
2027 #define REG_A5XX_RBBM_INT_0_STATUS				0x000004e1
2029 #define REG_A5XX_RBBM_AHB_ME_SPLIT_STATUS			0x000004f0
2031 #define REG_A5XX_RBBM_AHB_PFP_SPLIT_STATUS			0x000004f1
2033 #define REG_A5XX_RBBM_AHB_ETS_SPLIT_STATUS			0x000004f3
2035 #define REG_A5XX_RBBM_AHB_ERROR_STATUS				0x000004f4
2037 #define REG_A5XX_RBBM_PERFCTR_CNTL				0x00000464
2039 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD0				0x00000465
2041 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD1				0x00000466
2043 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD2				0x00000467
2045 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD3				0x00000468
2047 #define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_LO			0x00000469
2049 #define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_HI			0x0000046a
2051 #define REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED			0x0000046f
2053 #define REG_A5XX_RBBM_AHB_ERROR					0x000004ed
2055 #define REG_A5XX_RBBM_CFG_DBGBUS_EVENT_LOGIC			0x00000504
2057 #define REG_A5XX_RBBM_CFG_DBGBUS_OVER				0x00000505
2059 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT0				0x00000506
2061 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT1				0x00000507
2063 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT2				0x00000508
2065 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT3				0x00000509
2067 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT4				0x0000050a
2069 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT5				0x0000050b
2071 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_ADDR			0x0000050c
2073 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF0			0x0000050d
2075 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF1			0x0000050e
2077 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF2			0x0000050f
2079 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF3			0x00000510
2081 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF4			0x00000511
2083 #define REG_A5XX_RBBM_CFG_DBGBUS_MISR0				0x00000512
2085 #define REG_A5XX_RBBM_CFG_DBGBUS_MISR1				0x00000513
2087 #define REG_A5XX_RBBM_ISDB_CNT					0x00000533
2089 #define REG_A5XX_RBBM_SECVID_TRUST_CONFIG			0x0000f000
2091 #define REG_A5XX_RBBM_SECVID_TRUST_CNTL				0x0000f400
2093 #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO		0x0000f800
2095 #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI		0x0000f801
2097 #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE			0x0000f802
2099 #define REG_A5XX_RBBM_SECVID_TSB_CNTL				0x0000f803
2101 #define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_LO			0x0000f804
2103 #define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_HI			0x0000f805
2105 #define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_LO			0x0000f806
2107 #define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_HI			0x0000f807
2109 #define REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL			0x0000f810
2111 #define REG_A5XX_VSC_BIN_SIZE					0x00000bc2
2112 #define A5XX_VSC_BIN_SIZE_WIDTH__MASK				0x000000ff
2113 #define A5XX_VSC_BIN_SIZE_WIDTH__SHIFT				0
2118 #define A5XX_VSC_BIN_SIZE_HEIGHT__MASK				0x0001fe00
2125 #define REG_A5XX_VSC_SIZE_ADDRESS_LO				0x00000bc3
2127 #define REG_A5XX_VSC_SIZE_ADDRESS_HI				0x00000bc4
2129 #define REG_A5XX_UNKNOWN_0BC5					0x00000bc5
2131 #define REG_A5XX_UNKNOWN_0BC6					0x00000bc6
2133 static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; }  in REG_A5XX_VSC_PIPE_CONFIG()
2135 static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; }  in REG_A5XX_VSC_PIPE_CONFIG_REG()
2136 #define A5XX_VSC_PIPE_CONFIG_REG_X__MASK			0x000003ff
2137 #define A5XX_VSC_PIPE_CONFIG_REG_X__SHIFT			0
2142 #define A5XX_VSC_PIPE_CONFIG_REG_Y__MASK			0x000ffc00
2148 #define A5XX_VSC_PIPE_CONFIG_REG_W__MASK			0x00f00000
2154 #define A5XX_VSC_PIPE_CONFIG_REG_H__MASK			0x0f000000
2161 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000be0 + 0x2*i0; }  in REG_A5XX_VSC_PIPE_DATA_ADDRESS()
2163 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO(uint32_t i0) { return 0x00000be0 + 0x2*i0;…  in REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO()
2165 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_HI(uint32_t i0) { return 0x00000be1 + 0x2*i0;…  in REG_A5XX_VSC_PIPE_DATA_ADDRESS_HI()
2167 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c00 + 0x1*i0; }  in REG_A5XX_VSC_PIPE_DATA_LENGTH()
2169 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c00 + 0x1*i0;…  in REG_A5XX_VSC_PIPE_DATA_LENGTH_REG()
2171 #define REG_A5XX_VSC_PERFCTR_VSC_SEL_0				0x00000c60
2173 #define REG_A5XX_VSC_PERFCTR_VSC_SEL_1				0x00000c61
2175 #define REG_A5XX_VSC_RESOLVE_CNTL				0x00000cdd
2176 #define A5XX_VSC_RESOLVE_CNTL_WINDOW_OFFSET_DISABLE		0x80000000
2177 #define A5XX_VSC_RESOLVE_CNTL_X__MASK				0x00007fff
2178 #define A5XX_VSC_RESOLVE_CNTL_X__SHIFT				0
2183 #define A5XX_VSC_RESOLVE_CNTL_Y__MASK				0x7fff0000
2190 #define REG_A5XX_GRAS_ADDR_MODE_CNTL				0x00000c81
2192 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_0				0x00000c90
2194 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_1				0x00000c91
2196 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_2				0x00000c92
2198 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_3				0x00000c93
2200 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_0				0x00000c94
2202 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_1				0x00000c95
2204 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_2				0x00000c96
2206 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_3				0x00000c97
2208 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_0				0x00000c98
2210 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_1				0x00000c99
2212 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_2				0x00000c9a
2214 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_3				0x00000c9b
2216 #define REG_A5XX_RB_DBG_ECO_CNTL				0x00000cc4
2218 #define REG_A5XX_RB_ADDR_MODE_CNTL				0x00000cc5
2220 #define REG_A5XX_RB_MODE_CNTL					0x00000cc6
2222 #define REG_A5XX_RB_CCU_CNTL					0x00000cc7
2224 #define REG_A5XX_RB_PERFCTR_RB_SEL_0				0x00000cd0
2226 #define REG_A5XX_RB_PERFCTR_RB_SEL_1				0x00000cd1
2228 #define REG_A5XX_RB_PERFCTR_RB_SEL_2				0x00000cd2
2230 #define REG_A5XX_RB_PERFCTR_RB_SEL_3				0x00000cd3
2232 #define REG_A5XX_RB_PERFCTR_RB_SEL_4				0x00000cd4
2234 #define REG_A5XX_RB_PERFCTR_RB_SEL_5				0x00000cd5
2236 #define REG_A5XX_RB_PERFCTR_RB_SEL_6				0x00000cd6
2238 #define REG_A5XX_RB_PERFCTR_RB_SEL_7				0x00000cd7
2240 #define REG_A5XX_RB_PERFCTR_CCU_SEL_0				0x00000cd8
2242 #define REG_A5XX_RB_PERFCTR_CCU_SEL_1				0x00000cd9
2244 #define REG_A5XX_RB_PERFCTR_CCU_SEL_2				0x00000cda
2246 #define REG_A5XX_RB_PERFCTR_CCU_SEL_3				0x00000cdb
2248 #define REG_A5XX_RB_POWERCTR_RB_SEL_0				0x00000ce0
2250 #define REG_A5XX_RB_POWERCTR_RB_SEL_1				0x00000ce1
2252 #define REG_A5XX_RB_POWERCTR_RB_SEL_2				0x00000ce2
2254 #define REG_A5XX_RB_POWERCTR_RB_SEL_3				0x00000ce3
2256 #define REG_A5XX_RB_POWERCTR_CCU_SEL_0				0x00000ce4
2258 #define REG_A5XX_RB_POWERCTR_CCU_SEL_1				0x00000ce5
2260 #define REG_A5XX_RB_PERFCTR_CMP_SEL_0				0x00000cec
2262 #define REG_A5XX_RB_PERFCTR_CMP_SEL_1				0x00000ced
2264 #define REG_A5XX_RB_PERFCTR_CMP_SEL_2				0x00000cee
2266 #define REG_A5XX_RB_PERFCTR_CMP_SEL_3				0x00000cef
2268 #define REG_A5XX_PC_DBG_ECO_CNTL				0x00000d00
2269 #define A5XX_PC_DBG_ECO_CNTL_TWOPASSUSEWFI			0x00000100
2271 #define REG_A5XX_PC_ADDR_MODE_CNTL				0x00000d01
2273 #define REG_A5XX_PC_MODE_CNTL					0x00000d02
2275 #define REG_A5XX_PC_INDEX_BUF_LO				0x00000d04
2277 #define REG_A5XX_PC_INDEX_BUF_HI				0x00000d05
2279 #define REG_A5XX_PC_START_INDEX					0x00000d06
2281 #define REG_A5XX_PC_MAX_INDEX					0x00000d07
2283 #define REG_A5XX_PC_TESSFACTOR_ADDR_LO				0x00000d08
2285 #define REG_A5XX_PC_TESSFACTOR_ADDR_HI				0x00000d09
2287 #define REG_A5XX_PC_PERFCTR_PC_SEL_0				0x00000d10
2289 #define REG_A5XX_PC_PERFCTR_PC_SEL_1				0x00000d11
2291 #define REG_A5XX_PC_PERFCTR_PC_SEL_2				0x00000d12
2293 #define REG_A5XX_PC_PERFCTR_PC_SEL_3				0x00000d13
2295 #define REG_A5XX_PC_PERFCTR_PC_SEL_4				0x00000d14
2297 #define REG_A5XX_PC_PERFCTR_PC_SEL_5				0x00000d15
2299 #define REG_A5XX_PC_PERFCTR_PC_SEL_6				0x00000d16
2301 #define REG_A5XX_PC_PERFCTR_PC_SEL_7				0x00000d17
2303 #define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0			0x00000e00
2305 #define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_1			0x00000e01
2307 #define REG_A5XX_HLSQ_DBG_ECO_CNTL				0x00000e04
2309 #define REG_A5XX_HLSQ_ADDR_MODE_CNTL				0x00000e05
2311 #define REG_A5XX_HLSQ_MODE_CNTL					0x00000e06
2313 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_0			0x00000e10
2315 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_1			0x00000e11
2317 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_2			0x00000e12
2319 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_3			0x00000e13
2321 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_4			0x00000e14
2323 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_5			0x00000e15
2325 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_6			0x00000e16
2327 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_7			0x00000e17
2329 #define REG_A5XX_HLSQ_SPTP_RDSEL				0x00000f08
2331 #define REG_A5XX_HLSQ_DBG_READ_SEL				0x0000bc00
2333 #define REG_A5XX_HLSQ_DBG_AHB_READ_APERTURE			0x0000a000
2335 #define REG_A5XX_VFD_ADDR_MODE_CNTL				0x00000e41
2337 #define REG_A5XX_VFD_MODE_CNTL					0x00000e42
2339 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_0				0x00000e50
2341 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_1				0x00000e51
2343 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_2				0x00000e52
2345 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_3				0x00000e53
2347 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_4				0x00000e54
2349 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_5				0x00000e55
2351 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_6				0x00000e56
2353 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_7				0x00000e57
2355 #define REG_A5XX_VPC_DBG_ECO_CNTL				0x00000e60
2356 #define A5XX_VPC_DBG_ECO_CNTL_ALLFLATOPTDIS			0x00000400
2358 #define REG_A5XX_VPC_ADDR_MODE_CNTL				0x00000e61
2360 #define REG_A5XX_VPC_MODE_CNTL					0x00000e62
2361 #define A5XX_VPC_MODE_CNTL_BINNING_PASS				0x00000001
2363 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_0				0x00000e64
2365 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_1				0x00000e65
2367 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_2				0x00000e66
2369 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_3				0x00000e67
2371 #define REG_A5XX_UCHE_ADDR_MODE_CNTL				0x00000e80
2373 #define REG_A5XX_UCHE_MODE_CNTL					0x00000e81
2375 #define REG_A5XX_UCHE_SVM_CNTL					0x00000e82
2377 #define REG_A5XX_UCHE_WRITE_THRU_BASE_LO			0x00000e87
2379 #define REG_A5XX_UCHE_WRITE_THRU_BASE_HI			0x00000e88
2381 #define REG_A5XX_UCHE_TRAP_BASE_LO				0x00000e89
2383 #define REG_A5XX_UCHE_TRAP_BASE_HI				0x00000e8a
2385 #define REG_A5XX_UCHE_GMEM_RANGE_MIN_LO				0x00000e8b
2387 #define REG_A5XX_UCHE_GMEM_RANGE_MIN_HI				0x00000e8c
2389 #define REG_A5XX_UCHE_GMEM_RANGE_MAX_LO				0x00000e8d
2391 #define REG_A5XX_UCHE_GMEM_RANGE_MAX_HI				0x00000e8e
2393 #define REG_A5XX_UCHE_DBG_ECO_CNTL_2				0x00000e8f
2395 #define REG_A5XX_UCHE_DBG_ECO_CNTL				0x00000e90
2397 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_LO			0x00000e91
2399 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_HI			0x00000e92
2401 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_LO			0x00000e93
2403 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_HI			0x00000e94
2405 #define REG_A5XX_UCHE_CACHE_INVALIDATE				0x00000e95
2407 #define REG_A5XX_UCHE_CACHE_WAYS				0x00000e96
2409 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_0			0x00000ea0
2411 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_1			0x00000ea1
2413 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_2			0x00000ea2
2415 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_3			0x00000ea3
2417 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_4			0x00000ea4
2419 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_5			0x00000ea5
2421 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_6			0x00000ea6
2423 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_7			0x00000ea7
2425 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_0			0x00000ea8
2427 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_1			0x00000ea9
2429 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_2			0x00000eaa
2431 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_3			0x00000eab
2433 #define REG_A5XX_UCHE_TRAP_LOG_LO				0x00000eb1
2435 #define REG_A5XX_UCHE_TRAP_LOG_HI				0x00000eb2
2437 #define REG_A5XX_SP_DBG_ECO_CNTL				0x00000ec0
2439 #define REG_A5XX_SP_ADDR_MODE_CNTL				0x00000ec1
2441 #define REG_A5XX_SP_MODE_CNTL					0x00000ec2
2443 #define REG_A5XX_SP_PERFCTR_SP_SEL_0				0x00000ed0
2445 #define REG_A5XX_SP_PERFCTR_SP_SEL_1				0x00000ed1
2447 #define REG_A5XX_SP_PERFCTR_SP_SEL_2				0x00000ed2
2449 #define REG_A5XX_SP_PERFCTR_SP_SEL_3				0x00000ed3
2451 #define REG_A5XX_SP_PERFCTR_SP_SEL_4				0x00000ed4
2453 #define REG_A5XX_SP_PERFCTR_SP_SEL_5				0x00000ed5
2455 #define REG_A5XX_SP_PERFCTR_SP_SEL_6				0x00000ed6
2457 #define REG_A5XX_SP_PERFCTR_SP_SEL_7				0x00000ed7
2459 #define REG_A5XX_SP_PERFCTR_SP_SEL_8				0x00000ed8
2461 #define REG_A5XX_SP_PERFCTR_SP_SEL_9				0x00000ed9
2463 #define REG_A5XX_SP_PERFCTR_SP_SEL_10				0x00000eda
2465 #define REG_A5XX_SP_PERFCTR_SP_SEL_11				0x00000edb
2467 #define REG_A5XX_SP_POWERCTR_SP_SEL_0				0x00000edc
2469 #define REG_A5XX_SP_POWERCTR_SP_SEL_1				0x00000edd
2471 #define REG_A5XX_SP_POWERCTR_SP_SEL_2				0x00000ede
2473 #define REG_A5XX_SP_POWERCTR_SP_SEL_3				0x00000edf
2475 #define REG_A5XX_TPL1_ADDR_MODE_CNTL				0x00000f01
2477 #define REG_A5XX_TPL1_MODE_CNTL					0x00000f02
2479 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_0				0x00000f10
2481 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_1				0x00000f11
2483 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_2				0x00000f12
2485 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_3				0x00000f13
2487 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_4				0x00000f14
2489 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_5				0x00000f15
2491 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_6				0x00000f16
2493 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_7				0x00000f17
2495 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_0				0x00000f18
2497 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_1				0x00000f19
2499 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_2				0x00000f1a
2501 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_3				0x00000f1b
2503 #define REG_A5XX_VBIF_VERSION					0x00003000
2505 #define REG_A5XX_VBIF_CLKON					0x00003001
2507 #define REG_A5XX_VBIF_ABIT_SORT					0x00003028
2509 #define REG_A5XX_VBIF_ABIT_SORT_CONF				0x00003029
2511 #define REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB			0x00003049
2513 #define REG_A5XX_VBIF_GATE_OFF_WRREQ_EN				0x0000302a
2515 #define REG_A5XX_VBIF_IN_RD_LIM_CONF0				0x0000302c
2517 #define REG_A5XX_VBIF_IN_RD_LIM_CONF1				0x0000302d
2519 #define REG_A5XX_VBIF_XIN_HALT_CTRL0				0x00003080
2521 #define REG_A5XX_VBIF_XIN_HALT_CTRL1				0x00003081
2523 #define REG_A5XX_VBIF_TEST_BUS_OUT_CTRL				0x00003084
2525 #define REG_A5XX_VBIF_TEST_BUS1_CTRL0				0x00003085
2527 #define REG_A5XX_VBIF_TEST_BUS1_CTRL1				0x00003086
2529 #define REG_A5XX_VBIF_TEST_BUS2_CTRL0				0x00003087
2531 #define REG_A5XX_VBIF_TEST_BUS2_CTRL1				0x00003088
2533 #define REG_A5XX_VBIF_TEST_BUS_OUT				0x0000308c
2535 #define REG_A5XX_VBIF_PERF_CNT_EN0				0x000030c0
2537 #define REG_A5XX_VBIF_PERF_CNT_EN1				0x000030c1
2539 #define REG_A5XX_VBIF_PERF_CNT_EN2				0x000030c2
2541 #define REG_A5XX_VBIF_PERF_CNT_EN3				0x000030c3
2543 #define REG_A5XX_VBIF_PERF_CNT_CLR0				0x000030c8
2545 #define REG_A5XX_VBIF_PERF_CNT_CLR1				0x000030c9
2547 #define REG_A5XX_VBIF_PERF_CNT_CLR2				0x000030ca
2549 #define REG_A5XX_VBIF_PERF_CNT_CLR3				0x000030cb
2551 #define REG_A5XX_VBIF_PERF_CNT_SEL0				0x000030d0
2553 #define REG_A5XX_VBIF_PERF_CNT_SEL1				0x000030d1
2555 #define REG_A5XX_VBIF_PERF_CNT_SEL2				0x000030d2
2557 #define REG_A5XX_VBIF_PERF_CNT_SEL3				0x000030d3
2559 #define REG_A5XX_VBIF_PERF_CNT_LOW0				0x000030d8
2561 #define REG_A5XX_VBIF_PERF_CNT_LOW1				0x000030d9
2563 #define REG_A5XX_VBIF_PERF_CNT_LOW2				0x000030da
2565 #define REG_A5XX_VBIF_PERF_CNT_LOW3				0x000030db
2567 #define REG_A5XX_VBIF_PERF_CNT_HIGH0				0x000030e0
2569 #define REG_A5XX_VBIF_PERF_CNT_HIGH1				0x000030e1
2571 #define REG_A5XX_VBIF_PERF_CNT_HIGH2				0x000030e2
2573 #define REG_A5XX_VBIF_PERF_CNT_HIGH3				0x000030e3
2575 #define REG_A5XX_VBIF_PERF_PWR_CNT_EN0				0x00003100
2577 #define REG_A5XX_VBIF_PERF_PWR_CNT_EN1				0x00003101
2579 #define REG_A5XX_VBIF_PERF_PWR_CNT_EN2				0x00003102
2581 #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW0				0x00003110
2583 #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW1				0x00003111
2585 #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW2				0x00003112
2587 #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH0			0x00003118
2589 #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH1			0x00003119
2591 #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH2			0x0000311a
2593 #define REG_A5XX_GPMU_INST_RAM_BASE				0x00008800
2595 #define REG_A5XX_GPMU_DATA_RAM_BASE				0x00009800
2597 #define REG_A5XX_GPMU_SP_POWER_CNTL				0x0000a881
2599 #define REG_A5XX_GPMU_RBCCU_CLOCK_CNTL				0x0000a886
2601 #define REG_A5XX_GPMU_RBCCU_POWER_CNTL				0x0000a887
2603 #define REG_A5XX_GPMU_SP_PWR_CLK_STATUS				0x0000a88b
2604 #define A5XX_GPMU_SP_PWR_CLK_STATUS_PWR_ON			0x00100000
2606 #define REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS			0x0000a88d
2607 #define A5XX_GPMU_RBCCU_PWR_CLK_STATUS_PWR_ON			0x00100000
2609 #define REG_A5XX_GPMU_PWR_COL_STAGGER_DELAY			0x0000a891
2611 #define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_CTRL			0x0000a892
2613 #define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_HYST			0x0000a893
2615 #define REG_A5XX_GPMU_PWR_COL_BINNING_CTRL			0x0000a894
2617 #define REG_A5XX_GPMU_WFI_CONFIG				0x0000a8c1
2619 #define REG_A5XX_GPMU_RBBM_INTR_INFO				0x0000a8d6
2621 #define REG_A5XX_GPMU_CM3_SYSRESET				0x0000a8d8
2623 #define REG_A5XX_GPMU_GENERAL_0					0x0000a8e0
2625 #define REG_A5XX_GPMU_GENERAL_1					0x0000a8e1
2627 #define REG_A5XX_SP_POWER_COUNTER_0_LO				0x0000a840
2629 #define REG_A5XX_SP_POWER_COUNTER_0_HI				0x0000a841
2631 #define REG_A5XX_SP_POWER_COUNTER_1_LO				0x0000a842
2633 #define REG_A5XX_SP_POWER_COUNTER_1_HI				0x0000a843
2635 #define REG_A5XX_SP_POWER_COUNTER_2_LO				0x0000a844
2637 #define REG_A5XX_SP_POWER_COUNTER_2_HI				0x0000a845
2639 #define REG_A5XX_SP_POWER_COUNTER_3_LO				0x0000a846
2641 #define REG_A5XX_SP_POWER_COUNTER_3_HI				0x0000a847
2643 #define REG_A5XX_TP_POWER_COUNTER_0_LO				0x0000a848
2645 #define REG_A5XX_TP_POWER_COUNTER_0_HI				0x0000a849
2647 #define REG_A5XX_TP_POWER_COUNTER_1_LO				0x0000a84a
2649 #define REG_A5XX_TP_POWER_COUNTER_1_HI				0x0000a84b
2651 #define REG_A5XX_TP_POWER_COUNTER_2_LO				0x0000a84c
2653 #define REG_A5XX_TP_POWER_COUNTER_2_HI				0x0000a84d
2655 #define REG_A5XX_TP_POWER_COUNTER_3_LO				0x0000a84e
2657 #define REG_A5XX_TP_POWER_COUNTER_3_HI				0x0000a84f
2659 #define REG_A5XX_RB_POWER_COUNTER_0_LO				0x0000a850
2661 #define REG_A5XX_RB_POWER_COUNTER_0_HI				0x0000a851
2663 #define REG_A5XX_RB_POWER_COUNTER_1_LO				0x0000a852
2665 #define REG_A5XX_RB_POWER_COUNTER_1_HI				0x0000a853
2667 #define REG_A5XX_RB_POWER_COUNTER_2_LO				0x0000a854
2669 #define REG_A5XX_RB_POWER_COUNTER_2_HI				0x0000a855
2671 #define REG_A5XX_RB_POWER_COUNTER_3_LO				0x0000a856
2673 #define REG_A5XX_RB_POWER_COUNTER_3_HI				0x0000a857
2675 #define REG_A5XX_CCU_POWER_COUNTER_0_LO				0x0000a858
2677 #define REG_A5XX_CCU_POWER_COUNTER_0_HI				0x0000a859
2679 #define REG_A5XX_CCU_POWER_COUNTER_1_LO				0x0000a85a
2681 #define REG_A5XX_CCU_POWER_COUNTER_1_HI				0x0000a85b
2683 #define REG_A5XX_UCHE_POWER_COUNTER_0_LO			0x0000a85c
2685 #define REG_A5XX_UCHE_POWER_COUNTER_0_HI			0x0000a85d
2687 #define REG_A5XX_UCHE_POWER_COUNTER_1_LO			0x0000a85e
2689 #define REG_A5XX_UCHE_POWER_COUNTER_1_HI			0x0000a85f
2691 #define REG_A5XX_UCHE_POWER_COUNTER_2_LO			0x0000a860
2693 #define REG_A5XX_UCHE_POWER_COUNTER_2_HI			0x0000a861
2695 #define REG_A5XX_UCHE_POWER_COUNTER_3_LO			0x0000a862
2697 #define REG_A5XX_UCHE_POWER_COUNTER_3_HI			0x0000a863
2699 #define REG_A5XX_CP_POWER_COUNTER_0_LO				0x0000a864
2701 #define REG_A5XX_CP_POWER_COUNTER_0_HI				0x0000a865
2703 #define REG_A5XX_CP_POWER_COUNTER_1_LO				0x0000a866
2705 #define REG_A5XX_CP_POWER_COUNTER_1_HI				0x0000a867
2707 #define REG_A5XX_CP_POWER_COUNTER_2_LO				0x0000a868
2709 #define REG_A5XX_CP_POWER_COUNTER_2_HI				0x0000a869
2711 #define REG_A5XX_CP_POWER_COUNTER_3_LO				0x0000a86a
2713 #define REG_A5XX_CP_POWER_COUNTER_3_HI				0x0000a86b
2715 #define REG_A5XX_GPMU_POWER_COUNTER_0_LO			0x0000a86c
2717 #define REG_A5XX_GPMU_POWER_COUNTER_0_HI			0x0000a86d
2719 #define REG_A5XX_GPMU_POWER_COUNTER_1_LO			0x0000a86e
2721 #define REG_A5XX_GPMU_POWER_COUNTER_1_HI			0x0000a86f
2723 #define REG_A5XX_GPMU_POWER_COUNTER_2_LO			0x0000a870
2725 #define REG_A5XX_GPMU_POWER_COUNTER_2_HI			0x0000a871
2727 #define REG_A5XX_GPMU_POWER_COUNTER_3_LO			0x0000a872
2729 #define REG_A5XX_GPMU_POWER_COUNTER_3_HI			0x0000a873
2731 #define REG_A5XX_GPMU_POWER_COUNTER_4_LO			0x0000a874
2733 #define REG_A5XX_GPMU_POWER_COUNTER_4_HI			0x0000a875
2735 #define REG_A5XX_GPMU_POWER_COUNTER_5_LO			0x0000a876
2737 #define REG_A5XX_GPMU_POWER_COUNTER_5_HI			0x0000a877
2739 #define REG_A5XX_GPMU_POWER_COUNTER_ENABLE			0x0000a878
2741 #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_LO			0x0000a879
2743 #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_HI			0x0000a87a
2745 #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_RESET			0x0000a87b
2747 #define REG_A5XX_GPMU_POWER_COUNTER_SELECT_0			0x0000a87c
2749 #define REG_A5XX_GPMU_POWER_COUNTER_SELECT_1			0x0000a87d
2751 #define REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL			0x0000a8a3
2753 #define REG_A5XX_GPMU_THROTTLE_UNMASK_FORCE_CTRL		0x0000a8a8
2755 #define REG_A5XX_GPMU_TEMP_SENSOR_ID				0x0000ac00
2757 #define REG_A5XX_GPMU_TEMP_SENSOR_CONFIG			0x0000ac01
2759 #define REG_A5XX_GPMU_TEMP_VAL					0x0000ac02
2761 #define REG_A5XX_GPMU_DELTA_TEMP_THRESHOLD			0x0000ac03
2763 #define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_STATUS		0x0000ac05
2765 #define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_EN_MASK		0x0000ac06
2767 #define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_0_1			0x0000ac40
2769 #define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_2_3			0x0000ac41
2771 #define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_0_1			0x0000ac42
2773 #define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_2_3			0x0000ac43
2775 #define REG_A5XX_GPMU_BASE_LEAKAGE				0x0000ac46
2777 #define REG_A5XX_GPMU_GPMU_VOLTAGE				0x0000ac60
2779 #define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_STATUS			0x0000ac61
2781 #define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_EN_MASK			0x0000ac62
2783 #define REG_A5XX_GPMU_GPMU_PWR_THRESHOLD			0x0000ac80
2785 #define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_CTRL			0x0000acc4
2787 #define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_STATUS			0x0000acc5
2789 #define REG_A5XX_GDPM_CONFIG1					0x0000b80c
2791 #define REG_A5XX_GDPM_CONFIG2					0x0000b80d
2793 #define REG_A5XX_GDPM_INT_EN					0x0000b80f
2795 #define REG_A5XX_GDPM_INT_MASK					0x0000b811
2797 #define REG_A5XX_GPMU_BEC_ENABLE				0x0000b9a0
2799 #define REG_A5XX_GPU_CS_SENSOR_GENERAL_STATUS			0x0000c41a
2801 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_0		0x0000c41d
2803 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_2		0x0000c41f
2805 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_4		0x0000c421
2807 #define REG_A5XX_GPU_CS_ENABLE_REG				0x0000c520
2809 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_CONTROL1		0x0000c557
2811 #define REG_A5XX_GRAS_CL_CNTL					0x0000e000
2812 #define A5XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z			0x00000040
2814 #define REG_A5XX_GRAS_VS_CL_CNTL				0x0000e001
2815 #define A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK			0x000000ff
2816 #define A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT			0
2821 #define A5XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK			0x0000ff00
2828 #define REG_A5XX_UNKNOWN_E004					0x0000e004
2830 #define REG_A5XX_GRAS_CNTL					0x0000e005
2831 #define A5XX_GRAS_CNTL_IJ_PERSP_PIXEL				0x00000001
2832 #define A5XX_GRAS_CNTL_IJ_PERSP_CENTROID			0x00000002
2833 #define A5XX_GRAS_CNTL_IJ_PERSP_SAMPLE				0x00000004
2834 #define A5XX_GRAS_CNTL_IJ_LINEAR_PIXEL				0x00000008
2835 #define A5XX_GRAS_CNTL_IJ_LINEAR_CENTROID			0x00000010
2836 #define A5XX_GRAS_CNTL_IJ_LINEAR_SAMPLE				0x00000020
2837 #define A5XX_GRAS_CNTL_COORD_MASK__MASK				0x000003c0
2844 #define REG_A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ			0x0000e006
2845 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK		0x000003ff
2846 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT		0
2851 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK		0x000ffc00
2858 #define REG_A5XX_GRAS_CL_VPORT_XOFFSET_0			0x0000e010
2859 #define A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK			0xffffffff
2860 #define A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT			0
2866 #define REG_A5XX_GRAS_CL_VPORT_XSCALE_0				0x0000e011
2867 #define A5XX_GRAS_CL_VPORT_XSCALE_0__MASK			0xffffffff
2868 #define A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT			0
2874 #define REG_A5XX_GRAS_CL_VPORT_YOFFSET_0			0x0000e012
2875 #define A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK			0xffffffff
2876 #define A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT			0
2882 #define REG_A5XX_GRAS_CL_VPORT_YSCALE_0				0x0000e013
2883 #define A5XX_GRAS_CL_VPORT_YSCALE_0__MASK			0xffffffff
2884 #define A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT			0
2890 #define REG_A5XX_GRAS_CL_VPORT_ZOFFSET_0			0x0000e014
2891 #define A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK			0xffffffff
2892 #define A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT			0
2898 #define REG_A5XX_GRAS_CL_VPORT_ZSCALE_0				0x0000e015
2899 #define A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK			0xffffffff
2900 #define A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT			0
2906 #define REG_A5XX_GRAS_SU_CNTL					0x0000e090
2907 #define A5XX_GRAS_SU_CNTL_CULL_FRONT				0x00000001
2908 #define A5XX_GRAS_SU_CNTL_CULL_BACK				0x00000002
2909 #define A5XX_GRAS_SU_CNTL_FRONT_CW				0x00000004
2910 #define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK			0x000007f8
2916 #define A5XX_GRAS_SU_CNTL_POLY_OFFSET				0x00000800
2917 #define A5XX_GRAS_SU_CNTL_LINE_MODE__MASK			0x00002000
2924 #define REG_A5XX_GRAS_SU_POINT_MINMAX				0x0000e091
2925 #define A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK			0x0000ffff
2926 #define A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT			0
2931 #define A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK			0xffff0000
2938 #define REG_A5XX_GRAS_SU_POINT_SIZE				0x0000e092
2939 #define A5XX_GRAS_SU_POINT_SIZE__MASK				0xffffffff
2940 #define A5XX_GRAS_SU_POINT_SIZE__SHIFT				0
2946 #define REG_A5XX_GRAS_SU_LAYERED				0x0000e093
2948 #define REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL			0x0000e094
2949 #define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z		0x00000001
2950 #define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_UNK1			0x00000002
2952 #define REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE			0x0000e095
2953 #define A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK			0xffffffff
2954 #define A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT			0
2960 #define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET			0x0000e096
2961 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK			0xffffffff
2962 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT			0
2968 #define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP		0x0000e097
2969 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK		0xffffffff
2970 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT		0
2976 #define REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO			0x0000e098
2977 #define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK	0x00000007
2978 #define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT	0
2984 #define REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL			0x0000e099
2986 #define REG_A5XX_GRAS_SC_CNTL					0x0000e0a0
2987 #define A5XX_GRAS_SC_CNTL_BINNING_PASS				0x00000001
2988 #define A5XX_GRAS_SC_CNTL_SAMPLES_PASSED			0x00008000
2990 #define REG_A5XX_GRAS_SC_BIN_CNTL				0x0000e0a1
2992 #define REG_A5XX_GRAS_SC_RAS_MSAA_CNTL				0x0000e0a2
2993 #define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK		0x00000003
2994 #define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT		0
3000 #define REG_A5XX_GRAS_SC_DEST_MSAA_CNTL				0x0000e0a3
3001 #define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK		0x00000003
3002 #define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT		0
3007 #define A5XX_GRAS_SC_DEST_MSAA_CNTL_MSAA_DISABLE		0x00000004
3009 #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL			0x0000e0a4
3011 #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0			0x0000e0aa
3012 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE	0x80000000
3013 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK		0x00007fff
3014 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT		0
3019 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK		0x7fff0000
3026 #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0			0x0000e0ab
3027 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE	0x80000000
3028 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK		0x00007fff
3029 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT		0
3034 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK		0x7fff0000
3041 #define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0			0x0000e0ca
3042 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE	0x80000000
3043 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK		0x00007fff
3044 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT		0
3049 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK		0x7fff0000
3056 #define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0			0x0000e0cb
3057 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE	0x80000000
3058 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK		0x00007fff
3059 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT		0
3064 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK		0x7fff0000
3071 #define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL			0x0000e0ea
3072 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE	0x80000000
3073 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK			0x00007fff
3074 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT			0
3079 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK			0x7fff0000
3086 #define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_BR			0x0000e0eb
3087 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE	0x80000000
3088 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK			0x00007fff
3089 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT			0
3094 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK			0x7fff0000
3101 #define REG_A5XX_GRAS_LRZ_CNTL					0x0000e100
3102 #define A5XX_GRAS_LRZ_CNTL_ENABLE				0x00000001
3103 #define A5XX_GRAS_LRZ_CNTL_LRZ_WRITE				0x00000002
3104 #define A5XX_GRAS_LRZ_CNTL_GREATER				0x00000004
3106 #define REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO			0x0000e101
3108 #define REG_A5XX_GRAS_LRZ_BUFFER_BASE_HI			0x0000e102
3110 #define REG_A5XX_GRAS_LRZ_BUFFER_PITCH				0x0000e103
3111 #define A5XX_GRAS_LRZ_BUFFER_PITCH__MASK			0xffffffff
3112 #define A5XX_GRAS_LRZ_BUFFER_PITCH__SHIFT			0
3118 #define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO		0x0000e104
3120 #define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI		0x0000e105
3122 #define REG_A5XX_RB_CNTL					0x0000e140
3123 #define A5XX_RB_CNTL_WIDTH__MASK				0x000000ff
3124 #define A5XX_RB_CNTL_WIDTH__SHIFT				0
3129 #define A5XX_RB_CNTL_HEIGHT__MASK				0x0001fe00
3135 #define A5XX_RB_CNTL_BYPASS					0x00020000
3137 #define REG_A5XX_RB_RENDER_CNTL					0x0000e141
3138 #define A5XX_RB_RENDER_CNTL_BINNING_PASS			0x00000001
3139 #define A5XX_RB_RENDER_CNTL_SAMPLES_PASSED			0x00000040
3140 #define A5XX_RB_RENDER_CNTL_DISABLE_COLOR_PIPE			0x00000080
3141 #define A5XX_RB_RENDER_CNTL_FLAG_DEPTH				0x00004000
3142 #define A5XX_RB_RENDER_CNTL_FLAG_DEPTH2				0x00008000
3143 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK			0x00ff0000
3149 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS2__MASK			0xff000000
3156 #define REG_A5XX_RB_RAS_MSAA_CNTL				0x0000e142
3157 #define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK			0x00000003
3158 #define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT			0
3164 #define REG_A5XX_RB_DEST_MSAA_CNTL				0x0000e143
3165 #define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK			0x00000003
3166 #define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT			0
3171 #define A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE			0x00000004
3173 #define REG_A5XX_RB_RENDER_CONTROL0				0x0000e144
3174 #define A5XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL			0x00000001
3175 #define A5XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID		0x00000002
3176 #define A5XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE			0x00000004
3177 #define A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL			0x00000008
3178 #define A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_CENTROID		0x00000010
3179 #define A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_SAMPLE		0x00000020
3180 #define A5XX_RB_RENDER_CONTROL0_COORD_MASK__MASK		0x000003c0
3187 #define REG_A5XX_RB_RENDER_CONTROL1				0x0000e145
3188 #define A5XX_RB_RENDER_CONTROL1_SAMPLEMASK			0x00000001
3189 #define A5XX_RB_RENDER_CONTROL1_FACENESS			0x00000002
3190 #define A5XX_RB_RENDER_CONTROL1_SAMPLEID			0x00000004
3192 #define REG_A5XX_RB_FS_OUTPUT_CNTL				0x0000e146
3193 #define A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK			0x0000000f
3194 #define A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT			0
3199 #define A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z			0x00000020
3201 #define REG_A5XX_RB_RENDER_COMPONENTS				0x0000e147
3202 #define A5XX_RB_RENDER_COMPONENTS_RT0__MASK			0x0000000f
3203 #define A5XX_RB_RENDER_COMPONENTS_RT0__SHIFT			0
3208 #define A5XX_RB_RENDER_COMPONENTS_RT1__MASK			0x000000f0
3214 #define A5XX_RB_RENDER_COMPONENTS_RT2__MASK			0x00000f00
3220 #define A5XX_RB_RENDER_COMPONENTS_RT3__MASK			0x0000f000
3226 #define A5XX_RB_RENDER_COMPONENTS_RT4__MASK			0x000f0000
3232 #define A5XX_RB_RENDER_COMPONENTS_RT5__MASK			0x00f00000
3238 #define A5XX_RB_RENDER_COMPONENTS_RT6__MASK			0x0f000000
3244 #define A5XX_RB_RENDER_COMPONENTS_RT7__MASK			0xf0000000
3251 static inline uint32_t REG_A5XX_RB_MRT(uint32_t i0) { return 0x0000e150 + 0x7*i0; }  in REG_A5XX_RB_MRT()
3253 static inline uint32_t REG_A5XX_RB_MRT_CONTROL(uint32_t i0) { return 0x0000e150 + 0x7*i0; }  in REG_A5XX_RB_MRT_CONTROL()
3254 #define A5XX_RB_MRT_CONTROL_BLEND				0x00000001
3255 #define A5XX_RB_MRT_CONTROL_BLEND2				0x00000002
3256 #define A5XX_RB_MRT_CONTROL_ROP_ENABLE				0x00000004
3257 #define A5XX_RB_MRT_CONTROL_ROP_CODE__MASK			0x00000078
3263 #define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK		0x00000780
3270 static inline uint32_t REG_A5XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x0000e151 + 0x7*i0; }  in REG_A5XX_RB_MRT_BLEND_CONTROL()
3271 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK		0x0000001f
3272 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT		0
3277 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK	0x000000e0
3283 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK		0x00001f00
3289 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK	0x001f0000
3295 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK	0x00e00000
3301 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK	0x1f000000
3308 static inline uint32_t REG_A5XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x0000e152 + 0x7*i0; }  in REG_A5XX_RB_MRT_BUF_INFO()
3309 #define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK			0x000000ff
3310 #define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT		0
3315 #define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK		0x00000300
3321 #define A5XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK			0x00001800
3327 #define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK			0x00006000
3333 #define A5XX_RB_MRT_BUF_INFO_COLOR_SRGB				0x00008000
3335 static inline uint32_t REG_A5XX_RB_MRT_PITCH(uint32_t i0) { return 0x0000e153 + 0x7*i0; }  in REG_A5XX_RB_MRT_PITCH()
3336 #define A5XX_RB_MRT_PITCH__MASK					0xffffffff
3337 #define A5XX_RB_MRT_PITCH__SHIFT				0
3343 static inline uint32_t REG_A5XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x0000e154 + 0x7*i0; }  in REG_A5XX_RB_MRT_ARRAY_PITCH()
3344 #define A5XX_RB_MRT_ARRAY_PITCH__MASK				0xffffffff
3345 #define A5XX_RB_MRT_ARRAY_PITCH__SHIFT				0
3351 static inline uint32_t REG_A5XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x0000e155 + 0x7*i0; }  in REG_A5XX_RB_MRT_BASE_LO()
3353 static inline uint32_t REG_A5XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x0000e156 + 0x7*i0; }  in REG_A5XX_RB_MRT_BASE_HI()
3355 #define REG_A5XX_RB_BLEND_RED					0x0000e1a0
3356 #define A5XX_RB_BLEND_RED_UINT__MASK				0x000000ff
3357 #define A5XX_RB_BLEND_RED_UINT__SHIFT				0
3362 #define A5XX_RB_BLEND_RED_SINT__MASK				0x0000ff00
3368 #define A5XX_RB_BLEND_RED_FLOAT__MASK				0xffff0000
3375 #define REG_A5XX_RB_BLEND_RED_F32				0x0000e1a1
3376 #define A5XX_RB_BLEND_RED_F32__MASK				0xffffffff
3377 #define A5XX_RB_BLEND_RED_F32__SHIFT				0
3383 #define REG_A5XX_RB_BLEND_GREEN					0x0000e1a2
3384 #define A5XX_RB_BLEND_GREEN_UINT__MASK				0x000000ff
3385 #define A5XX_RB_BLEND_GREEN_UINT__SHIFT				0
3390 #define A5XX_RB_BLEND_GREEN_SINT__MASK				0x0000ff00
3396 #define A5XX_RB_BLEND_GREEN_FLOAT__MASK				0xffff0000
3403 #define REG_A5XX_RB_BLEND_GREEN_F32				0x0000e1a3
3404 #define A5XX_RB_BLEND_GREEN_F32__MASK				0xffffffff
3405 #define A5XX_RB_BLEND_GREEN_F32__SHIFT				0
3411 #define REG_A5XX_RB_BLEND_BLUE					0x0000e1a4
3412 #define A5XX_RB_BLEND_BLUE_UINT__MASK				0x000000ff
3413 #define A5XX_RB_BLEND_BLUE_UINT__SHIFT				0
3418 #define A5XX_RB_BLEND_BLUE_SINT__MASK				0x0000ff00
3424 #define A5XX_RB_BLEND_BLUE_FLOAT__MASK				0xffff0000
3431 #define REG_A5XX_RB_BLEND_BLUE_F32				0x0000e1a5
3432 #define A5XX_RB_BLEND_BLUE_F32__MASK				0xffffffff
3433 #define A5XX_RB_BLEND_BLUE_F32__SHIFT				0
3439 #define REG_A5XX_RB_BLEND_ALPHA					0x0000e1a6
3440 #define A5XX_RB_BLEND_ALPHA_UINT__MASK				0x000000ff
3441 #define A5XX_RB_BLEND_ALPHA_UINT__SHIFT				0
3446 #define A5XX_RB_BLEND_ALPHA_SINT__MASK				0x0000ff00
3452 #define A5XX_RB_BLEND_ALPHA_FLOAT__MASK				0xffff0000
3459 #define REG_A5XX_RB_BLEND_ALPHA_F32				0x0000e1a7
3460 #define A5XX_RB_BLEND_ALPHA_F32__MASK				0xffffffff
3461 #define A5XX_RB_BLEND_ALPHA_F32__SHIFT				0
3467 #define REG_A5XX_RB_ALPHA_CONTROL				0x0000e1a8
3468 #define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK			0x000000ff
3469 #define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT			0
3474 #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST			0x00000100
3475 #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK		0x00000e00
3482 #define REG_A5XX_RB_BLEND_CNTL					0x0000e1a9
3483 #define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK			0x000000ff
3484 #define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT			0
3489 #define A5XX_RB_BLEND_CNTL_INDEPENDENT_BLEND			0x00000100
3490 #define A5XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE			0x00000400
3491 #define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK			0xffff0000
3498 #define REG_A5XX_RB_DEPTH_PLANE_CNTL				0x0000e1b0
3499 #define A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z			0x00000001
3500 #define A5XX_RB_DEPTH_PLANE_CNTL_UNK1				0x00000002
3502 #define REG_A5XX_RB_DEPTH_CNTL					0x0000e1b1
3503 #define A5XX_RB_DEPTH_CNTL_Z_TEST_ENABLE			0x00000001
3504 #define A5XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE			0x00000002
3505 #define A5XX_RB_DEPTH_CNTL_ZFUNC__MASK				0x0000001c
3511 #define A5XX_RB_DEPTH_CNTL_Z_READ_ENABLE			0x00000040
3513 #define REG_A5XX_RB_DEPTH_BUFFER_INFO				0x0000e1b2
3514 #define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK		0x00000007
3515 #define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT		0
3521 #define REG_A5XX_RB_DEPTH_BUFFER_BASE_LO			0x0000e1b3
3523 #define REG_A5XX_RB_DEPTH_BUFFER_BASE_HI			0x0000e1b4
3525 #define REG_A5XX_RB_DEPTH_BUFFER_PITCH				0x0000e1b5
3526 #define A5XX_RB_DEPTH_BUFFER_PITCH__MASK			0xffffffff
3527 #define A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT			0
3533 #define REG_A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH			0x0000e1b6
3534 #define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK			0xffffffff
3535 #define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT			0
3541 #define REG_A5XX_RB_STENCIL_CONTROL				0x0000e1c0
3542 #define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE			0x00000001
3543 #define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF		0x00000002
3544 #define A5XX_RB_STENCIL_CONTROL_STENCIL_READ			0x00000004
3545 #define A5XX_RB_STENCIL_CONTROL_FUNC__MASK			0x00000700
3551 #define A5XX_RB_STENCIL_CONTROL_FAIL__MASK			0x00003800
3557 #define A5XX_RB_STENCIL_CONTROL_ZPASS__MASK			0x0001c000
3563 #define A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK			0x000e0000
3569 #define A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK			0x00700000
3575 #define A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK			0x03800000
3581 #define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK			0x1c000000
3587 #define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK			0xe0000000
3594 #define REG_A5XX_RB_STENCIL_INFO				0x0000e1c1
3595 #define A5XX_RB_STENCIL_INFO_SEPARATE_STENCIL			0x00000001
3597 #define REG_A5XX_RB_STENCIL_BASE_LO				0x0000e1c2
3599 #define REG_A5XX_RB_STENCIL_BASE_HI				0x0000e1c3
3601 #define REG_A5XX_RB_STENCIL_PITCH				0x0000e1c4
3602 #define A5XX_RB_STENCIL_PITCH__MASK				0xffffffff
3603 #define A5XX_RB_STENCIL_PITCH__SHIFT				0
3609 #define REG_A5XX_RB_STENCIL_ARRAY_PITCH				0x0000e1c5
3610 #define A5XX_RB_STENCIL_ARRAY_PITCH__MASK			0xffffffff
3611 #define A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT			0
3617 #define REG_A5XX_RB_STENCILREFMASK				0x0000e1c6
3618 #define A5XX_RB_STENCILREFMASK_STENCILREF__MASK			0x000000ff
3619 #define A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT		0
3624 #define A5XX_RB_STENCILREFMASK_STENCILMASK__MASK		0x0000ff00
3630 #define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK		0x00ff0000
3637 #define REG_A5XX_RB_STENCILREFMASK_BF				0x0000e1c7
3638 #define A5XX_RB_STENCILREFMASK_BF_STENCILREF__MASK		0x000000ff
3639 #define A5XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT		0
3644 #define A5XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK		0x0000ff00
3650 #define A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK	0x00ff0000
3657 #define REG_A5XX_RB_WINDOW_OFFSET				0x0000e1d0
3658 #define A5XX_RB_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE		0x80000000
3659 #define A5XX_RB_WINDOW_OFFSET_X__MASK				0x00007fff
3660 #define A5XX_RB_WINDOW_OFFSET_X__SHIFT				0
3665 #define A5XX_RB_WINDOW_OFFSET_Y__MASK				0x7fff0000
3672 #define REG_A5XX_RB_SAMPLE_COUNT_CONTROL			0x0000e1d1
3673 #define A5XX_RB_SAMPLE_COUNT_CONTROL_COPY			0x00000002
3675 #define REG_A5XX_RB_BLIT_CNTL					0x0000e210
3676 #define A5XX_RB_BLIT_CNTL_BUF__MASK				0x0000000f
3677 #define A5XX_RB_BLIT_CNTL_BUF__SHIFT				0
3683 #define REG_A5XX_RB_RESOLVE_CNTL_1				0x0000e211
3684 #define A5XX_RB_RESOLVE_CNTL_1_WINDOW_OFFSET_DISABLE		0x80000000
3685 #define A5XX_RB_RESOLVE_CNTL_1_X__MASK				0x00007fff
3686 #define A5XX_RB_RESOLVE_CNTL_1_X__SHIFT				0
3691 #define A5XX_RB_RESOLVE_CNTL_1_Y__MASK				0x7fff0000
3698 #define REG_A5XX_RB_RESOLVE_CNTL_2				0x0000e212
3699 #define A5XX_RB_RESOLVE_CNTL_2_WINDOW_OFFSET_DISABLE		0x80000000
3700 #define A5XX_RB_RESOLVE_CNTL_2_X__MASK				0x00007fff
3701 #define A5XX_RB_RESOLVE_CNTL_2_X__SHIFT				0
3706 #define A5XX_RB_RESOLVE_CNTL_2_Y__MASK				0x7fff0000
3713 #define REG_A5XX_RB_RESOLVE_CNTL_3				0x0000e213
3714 #define A5XX_RB_RESOLVE_CNTL_3_TILED				0x00000001
3716 #define REG_A5XX_RB_BLIT_DST_LO					0x0000e214
3718 #define REG_A5XX_RB_BLIT_DST_HI					0x0000e215
3720 #define REG_A5XX_RB_BLIT_DST_PITCH				0x0000e216
3721 #define A5XX_RB_BLIT_DST_PITCH__MASK				0xffffffff
3722 #define A5XX_RB_BLIT_DST_PITCH__SHIFT				0
3728 #define REG_A5XX_RB_BLIT_DST_ARRAY_PITCH			0x0000e217
3729 #define A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK			0xffffffff
3730 #define A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT			0
3736 #define REG_A5XX_RB_CLEAR_COLOR_DW0				0x0000e218
3738 #define REG_A5XX_RB_CLEAR_COLOR_DW1				0x0000e219
3740 #define REG_A5XX_RB_CLEAR_COLOR_DW2				0x0000e21a
3742 #define REG_A5XX_RB_CLEAR_COLOR_DW3				0x0000e21b
3744 #define REG_A5XX_RB_CLEAR_CNTL					0x0000e21c
3745 #define A5XX_RB_CLEAR_CNTL_FAST_CLEAR				0x00000002
3746 #define A5XX_RB_CLEAR_CNTL_MSAA_RESOLVE				0x00000004
3747 #define A5XX_RB_CLEAR_CNTL_MASK__MASK				0x000000f0
3754 #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_LO			0x0000e240
3756 #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_HI			0x0000e241
3758 #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_PITCH			0x0000e242
3760 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x0000e243 + 0x4*i0; }  in REG_A5XX_RB_MRT_FLAG_BUFFER()
3762 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x0000e243 + 0x4*i…  in REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_LO()
3764 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x0000e244 + 0x4*i…  in REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_HI()
3766 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x0000e245 + 0x4*i0;…  in REG_A5XX_RB_MRT_FLAG_BUFFER_PITCH()
3767 #define A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK			0xffffffff
3768 #define A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT			0
3774 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t i0) { return 0x0000e246 + 0…  in REG_A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH()
3775 #define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK		0xffffffff
3776 #define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT		0
3782 #define REG_A5XX_RB_BLIT_FLAG_DST_LO				0x0000e263
3784 #define REG_A5XX_RB_BLIT_FLAG_DST_HI				0x0000e264
3786 #define REG_A5XX_RB_BLIT_FLAG_DST_PITCH				0x0000e265
3787 #define A5XX_RB_BLIT_FLAG_DST_PITCH__MASK			0xffffffff
3788 #define A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT			0
3794 #define REG_A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH			0x0000e266
3795 #define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK			0xffffffff
3796 #define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT		0
3802 #define REG_A5XX_RB_SAMPLE_COUNT_ADDR_LO			0x0000e267
3804 #define REG_A5XX_RB_SAMPLE_COUNT_ADDR_HI			0x0000e268
3806 #define REG_A5XX_VPC_CNTL_0					0x0000e280
3807 #define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK			0x0000007f
3808 #define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT			0
3813 #define A5XX_VPC_CNTL_0_VARYING					0x00000800
3815 static inline uint32_t REG_A5XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x0000e282 + 0x1*i0; }  in REG_A5XX_VPC_VARYING_INTERP()
3817 static inline uint32_t REG_A5XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x0000e282 + 0x1*i0; }  in REG_A5XX_VPC_VARYING_INTERP_MODE()
3819 static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000e28a + 0x1*i0; }  in REG_A5XX_VPC_VARYING_PS_REPL()
3821 static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000e28a + 0x1*i0;…  in REG_A5XX_VPC_VARYING_PS_REPL_MODE()
3823 #define REG_A5XX_UNKNOWN_E292					0x0000e292
3825 #define REG_A5XX_UNKNOWN_E293					0x0000e293
3827 static inline uint32_t REG_A5XX_VPC_VAR(uint32_t i0) { return 0x0000e294 + 0x1*i0; }  in REG_A5XX_VPC_VAR()
3829 static inline uint32_t REG_A5XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x0000e294 + 0x1*i0; }  in REG_A5XX_VPC_VAR_DISABLE()
3831 #define REG_A5XX_VPC_GS_SIV_CNTL				0x0000e298
3833 #define REG_A5XX_VPC_CLIP_CNTL					0x0000e29a
3834 #define A5XX_VPC_CLIP_CNTL_CLIP_MASK__MASK			0x000000ff
3835 #define A5XX_VPC_CLIP_CNTL_CLIP_MASK__SHIFT			0
3840 #define A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__MASK		0x0000ff00
3846 #define A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__MASK		0x00ff0000
3853 #define REG_A5XX_VPC_PACK					0x0000e29d
3854 #define A5XX_VPC_PACK_NUMNONPOSVAR__MASK			0x000000ff
3855 #define A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT			0
3860 #define A5XX_VPC_PACK_PSIZELOC__MASK				0x0000ff00
3867 #define REG_A5XX_VPC_FS_PRIMITIVEID_CNTL			0x0000e2a0
3869 #define REG_A5XX_VPC_SO_BUF_CNTL				0x0000e2a1
3870 #define A5XX_VPC_SO_BUF_CNTL_BUF0				0x00000001
3871 #define A5XX_VPC_SO_BUF_CNTL_BUF1				0x00000008
3872 #define A5XX_VPC_SO_BUF_CNTL_BUF2				0x00000040
3873 #define A5XX_VPC_SO_BUF_CNTL_BUF3				0x00000200
3874 #define A5XX_VPC_SO_BUF_CNTL_ENABLE				0x00008000
3876 #define REG_A5XX_VPC_SO_OVERRIDE				0x0000e2a2
3877 #define A5XX_VPC_SO_OVERRIDE_SO_DISABLE				0x00000001
3879 #define REG_A5XX_VPC_SO_CNTL					0x0000e2a3
3880 #define A5XX_VPC_SO_CNTL_ENABLE					0x00010000
3882 #define REG_A5XX_VPC_SO_PROG					0x0000e2a4
3883 #define A5XX_VPC_SO_PROG_A_BUF__MASK				0x00000003
3884 #define A5XX_VPC_SO_PROG_A_BUF__SHIFT				0
3889 #define A5XX_VPC_SO_PROG_A_OFF__MASK				0x000007fc
3895 #define A5XX_VPC_SO_PROG_A_EN					0x00000800
3896 #define A5XX_VPC_SO_PROG_B_BUF__MASK				0x00003000
3902 #define A5XX_VPC_SO_PROG_B_OFF__MASK				0x007fc000
3908 #define A5XX_VPC_SO_PROG_B_EN					0x00800000
3910 static inline uint32_t REG_A5XX_VPC_SO(uint32_t i0) { return 0x0000e2a7 + 0x7*i0; }  in REG_A5XX_VPC_SO()
3912 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { return 0x0000e2a7 + 0x7*i0; }  in REG_A5XX_VPC_SO_BUFFER_BASE_LO()
3914 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0) { return 0x0000e2a8 + 0x7*i0; }  in REG_A5XX_VPC_SO_BUFFER_BASE_HI()
3916 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000e2a9 + 0x7*i0; }  in REG_A5XX_VPC_SO_BUFFER_SIZE()
3918 static inline uint32_t REG_A5XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000e2aa + 0x7*i0; }  in REG_A5XX_VPC_SO_NCOMP()
3920 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000e2ab + 0x7*i0; }  in REG_A5XX_VPC_SO_BUFFER_OFFSET()
3922 static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) { return 0x0000e2ac + 0x7*i0; }  in REG_A5XX_VPC_SO_FLUSH_BASE_LO()
3924 static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) { return 0x0000e2ad + 0x7*i0; }  in REG_A5XX_VPC_SO_FLUSH_BASE_HI()
3926 #define REG_A5XX_PC_PRIMITIVE_CNTL				0x0000e384
3927 #define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK		0x0000007f
3928 #define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT		0
3933 #define A5XX_PC_PRIMITIVE_CNTL_PRIMITIVE_RESTART		0x00000100
3934 #define A5XX_PC_PRIMITIVE_CNTL_COUNT_PRIMITIVES			0x00000200
3935 #define A5XX_PC_PRIMITIVE_CNTL_PROVOKING_VTX_LAST		0x00000400
3937 #define REG_A5XX_PC_PRIM_VTX_CNTL				0x0000e385
3938 #define A5XX_PC_PRIM_VTX_CNTL_PSIZE				0x00000800
3940 #define REG_A5XX_PC_RASTER_CNTL					0x0000e388
3941 #define A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__MASK		0x00000007
3942 #define A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__SHIFT		0
3947 #define A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__MASK		0x00000038
3953 #define A5XX_PC_RASTER_CNTL_POLYMODE_ENABLE			0x00000040
3955 #define REG_A5XX_PC_CLIP_CNTL					0x0000e389
3956 #define A5XX_PC_CLIP_CNTL_CLIP_MASK__MASK			0x000000ff
3957 #define A5XX_PC_CLIP_CNTL_CLIP_MASK__SHIFT			0
3963 #define REG_A5XX_PC_RESTART_INDEX				0x0000e38c
3965 #define REG_A5XX_PC_GS_LAYERED					0x0000e38d
3967 #define REG_A5XX_PC_GS_PARAM					0x0000e38e
3968 #define A5XX_PC_GS_PARAM_MAX_VERTICES__MASK			0x000003ff
3969 #define A5XX_PC_GS_PARAM_MAX_VERTICES__SHIFT			0
3974 #define A5XX_PC_GS_PARAM_INVOCATIONS__MASK			0x0000f800
3980 #define A5XX_PC_GS_PARAM_PRIMTYPE__MASK				0x01800000
3987 #define REG_A5XX_PC_HS_PARAM					0x0000e38f
3988 #define A5XX_PC_HS_PARAM_VERTICES_OUT__MASK			0x0000003f
3989 #define A5XX_PC_HS_PARAM_VERTICES_OUT__SHIFT			0
3994 #define A5XX_PC_HS_PARAM_SPACING__MASK				0x00600000
4000 #define A5XX_PC_HS_PARAM_CW					0x00800000
4001 #define A5XX_PC_HS_PARAM_CONNECTED				0x01000000
4003 #define REG_A5XX_PC_POWER_CNTL					0x0000e3b0
4005 #define REG_A5XX_VFD_CONTROL_0					0x0000e400
4006 #define A5XX_VFD_CONTROL_0_VTXCNT__MASK				0x0000003f
4007 #define A5XX_VFD_CONTROL_0_VTXCNT__SHIFT			0
4013 #define REG_A5XX_VFD_CONTROL_1					0x0000e401
4014 #define A5XX_VFD_CONTROL_1_REGID4VTX__MASK			0x000000ff
4015 #define A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT			0
4020 #define A5XX_VFD_CONTROL_1_REGID4INST__MASK			0x0000ff00
4026 #define A5XX_VFD_CONTROL_1_REGID4PRIMID__MASK			0x00ff0000
4033 #define REG_A5XX_VFD_CONTROL_2					0x0000e402
4034 #define A5XX_VFD_CONTROL_2_REGID_PATCHID__MASK			0x000000ff
4035 #define A5XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT			0
4041 #define REG_A5XX_VFD_CONTROL_3					0x0000e403
4042 #define A5XX_VFD_CONTROL_3_REGID_PATCHID__MASK			0x0000ff00
4048 #define A5XX_VFD_CONTROL_3_REGID_TESSX__MASK			0x00ff0000
4054 #define A5XX_VFD_CONTROL_3_REGID_TESSY__MASK			0xff000000
4061 #define REG_A5XX_VFD_CONTROL_4					0x0000e404
4063 #define REG_A5XX_VFD_CONTROL_5					0x0000e405
4065 #define REG_A5XX_VFD_INDEX_OFFSET				0x0000e408
4067 #define REG_A5XX_VFD_INSTANCE_START_OFFSET			0x0000e409
4069 static inline uint32_t REG_A5XX_VFD_FETCH(uint32_t i0) { return 0x0000e40a + 0x4*i0; }  in REG_A5XX_VFD_FETCH()
4071 static inline uint32_t REG_A5XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000e40a + 0x4*i0; }  in REG_A5XX_VFD_FETCH_BASE_LO()
4073 static inline uint32_t REG_A5XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000e40b + 0x4*i0; }  in REG_A5XX_VFD_FETCH_BASE_HI()
4075 static inline uint32_t REG_A5XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000e40c + 0x4*i0; }  in REG_A5XX_VFD_FETCH_SIZE()
4077 static inline uint32_t REG_A5XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000e40d + 0x4*i0; }  in REG_A5XX_VFD_FETCH_STRIDE()
4079 static inline uint32_t REG_A5XX_VFD_DECODE(uint32_t i0) { return 0x0000e48a + 0x2*i0; }  in REG_A5XX_VFD_DECODE()
4081 static inline uint32_t REG_A5XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000e48a + 0x2*i0; }  in REG_A5XX_VFD_DECODE_INSTR()
4082 #define A5XX_VFD_DECODE_INSTR_IDX__MASK				0x0000001f
4083 #define A5XX_VFD_DECODE_INSTR_IDX__SHIFT			0
4088 #define A5XX_VFD_DECODE_INSTR_INSTANCED				0x00020000
4089 #define A5XX_VFD_DECODE_INSTR_FORMAT__MASK			0x0ff00000
4095 #define A5XX_VFD_DECODE_INSTR_SWAP__MASK			0x30000000
4101 #define A5XX_VFD_DECODE_INSTR_UNK30				0x40000000
4102 #define A5XX_VFD_DECODE_INSTR_FLOAT				0x80000000
4104 static inline uint32_t REG_A5XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000e48b + 0x2*i0; }  in REG_A5XX_VFD_DECODE_STEP_RATE()
4106 static inline uint32_t REG_A5XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000e4ca + 0x1*i0; }  in REG_A5XX_VFD_DEST_CNTL()
4108 static inline uint32_t REG_A5XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000e4ca + 0x1*i0; }  in REG_A5XX_VFD_DEST_CNTL_INSTR()
4109 #define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK		0x0000000f
4110 #define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT		0
4115 #define A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK			0x00000ff0
4122 #define REG_A5XX_VFD_POWER_CNTL					0x0000e4f0
4124 #define REG_A5XX_SP_SP_CNTL					0x0000e580
4126 #define REG_A5XX_SP_VS_CONFIG					0x0000e584
4127 #define A5XX_SP_VS_CONFIG_ENABLED				0x00000001
4128 #define A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__MASK		0x000000fe
4134 #define A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__MASK			0x00007f00
4141 #define REG_A5XX_SP_FS_CONFIG					0x0000e585
4142 #define A5XX_SP_FS_CONFIG_ENABLED				0x00000001
4143 #define A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__MASK		0x000000fe
4149 #define A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__MASK			0x00007f00
4156 #define REG_A5XX_SP_HS_CONFIG					0x0000e586
4157 #define A5XX_SP_HS_CONFIG_ENABLED				0x00000001
4158 #define A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__MASK		0x000000fe
4164 #define A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__MASK			0x00007f00
4171 #define REG_A5XX_SP_DS_CONFIG					0x0000e587
4172 #define A5XX_SP_DS_CONFIG_ENABLED				0x00000001
4173 #define A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__MASK		0x000000fe
4179 #define A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__MASK			0x00007f00
4186 #define REG_A5XX_SP_GS_CONFIG					0x0000e588
4187 #define A5XX_SP_GS_CONFIG_ENABLED				0x00000001
4188 #define A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__MASK		0x000000fe
4194 #define A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__MASK			0x00007f00
4201 #define REG_A5XX_SP_CS_CONFIG					0x0000e589
4202 #define A5XX_SP_CS_CONFIG_ENABLED				0x00000001
4203 #define A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__MASK		0x000000fe
4209 #define A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__MASK			0x00007f00
4216 #define REG_A5XX_SP_VS_CONFIG_MAX_CONST				0x0000e58a
4218 #define REG_A5XX_SP_FS_CONFIG_MAX_CONST				0x0000e58b
4220 #define REG_A5XX_SP_VS_CTRL_REG0				0x0000e590
4221 #define A5XX_SP_VS_CTRL_REG0_THREADSIZE__MASK			0x00000008
4227 #define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x000003f0
4233 #define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x0000fc00
4239 #define A5XX_SP_VS_CTRL_REG0_VARYING				0x00010000
4240 #define A5XX_SP_VS_CTRL_REG0_PIXLODENABLE			0x00100000
4241 #define A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK			0xfe000000
4248 #define REG_A5XX_SP_PRIMITIVE_CNTL				0x0000e592
4249 #define A5XX_SP_PRIMITIVE_CNTL_VSOUT__MASK			0x0000001f
4250 #define A5XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT			0
4256 static inline uint32_t REG_A5XX_SP_VS_OUT(uint32_t i0) { return 0x0000e593 + 0x1*i0; }  in REG_A5XX_SP_VS_OUT()
4258 static inline uint32_t REG_A5XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000e593 + 0x1*i0; }  in REG_A5XX_SP_VS_OUT_REG()
4259 #define A5XX_SP_VS_OUT_REG_A_REGID__MASK			0x000000ff
4260 #define A5XX_SP_VS_OUT_REG_A_REGID__SHIFT			0
4265 #define A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK			0x00000f00
4271 #define A5XX_SP_VS_OUT_REG_B_REGID__MASK			0x00ff0000
4277 #define A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK			0x0f000000
4284 static inline uint32_t REG_A5XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; }  in REG_A5XX_SP_VS_VPC_DST()
4286 static inline uint32_t REG_A5XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; }  in REG_A5XX_SP_VS_VPC_DST_REG()
4287 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK			0x000000ff
4288 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT			0
4293 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK			0x0000ff00
4299 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK			0x00ff0000
4305 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK			0xff000000
4312 #define REG_A5XX_UNKNOWN_E5AB					0x0000e5ab
4314 #define REG_A5XX_SP_VS_OBJ_START_LO				0x0000e5ac
4316 #define REG_A5XX_SP_VS_OBJ_START_HI				0x0000e5ad
4318 #define REG_A5XX_SP_FS_CTRL_REG0				0x0000e5c0
4319 #define A5XX_SP_FS_CTRL_REG0_THREADSIZE__MASK			0x00000008
4325 #define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x000003f0
4331 #define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x0000fc00
4337 #define A5XX_SP_FS_CTRL_REG0_VARYING				0x00010000
4338 #define A5XX_SP_FS_CTRL_REG0_PIXLODENABLE			0x00100000
4339 #define A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK			0xfe000000
4346 #define REG_A5XX_UNKNOWN_E5C2					0x0000e5c2
4348 #define REG_A5XX_SP_FS_OBJ_START_LO				0x0000e5c3
4350 #define REG_A5XX_SP_FS_OBJ_START_HI				0x0000e5c4
4352 #define REG_A5XX_SP_BLEND_CNTL					0x0000e5c9
4353 #define A5XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK			0x000000ff
4354 #define A5XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT			0
4359 #define A5XX_SP_BLEND_CNTL_UNK8					0x00000100
4360 #define A5XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE			0x00000400
4362 #define REG_A5XX_SP_FS_OUTPUT_CNTL				0x0000e5ca
4363 #define A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK			0x0000000f
4364 #define A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT			0
4369 #define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK		0x00001fe0
4375 #define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK		0x001fe000
4382 static inline uint32_t REG_A5XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000e5cb + 0x1*i0; }  in REG_A5XX_SP_FS_OUTPUT()
4384 static inline uint32_t REG_A5XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000e5cb + 0x1*i0; }  in REG_A5XX_SP_FS_OUTPUT_REG()
4385 #define A5XX_SP_FS_OUTPUT_REG_REGID__MASK			0x000000ff
4386 #define A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT			0
4391 #define A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION			0x00000100
4393 static inline uint32_t REG_A5XX_SP_FS_MRT(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; }  in REG_A5XX_SP_FS_MRT()
4395 static inline uint32_t REG_A5XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; }  in REG_A5XX_SP_FS_MRT_REG()
4396 #define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK			0x000000ff
4397 #define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT			0
4402 #define A5XX_SP_FS_MRT_REG_COLOR_SINT				0x00000100
4403 #define A5XX_SP_FS_MRT_REG_COLOR_UINT				0x00000200
4404 #define A5XX_SP_FS_MRT_REG_COLOR_SRGB				0x00000400
4406 #define REG_A5XX_UNKNOWN_E5DB					0x0000e5db
4408 #define REG_A5XX_SP_CS_CTRL_REG0				0x0000e5f0
4409 #define A5XX_SP_CS_CTRL_REG0_THREADSIZE__MASK			0x00000008
4415 #define A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x000003f0
4421 #define A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x0000fc00
4427 #define A5XX_SP_CS_CTRL_REG0_VARYING				0x00010000
4428 #define A5XX_SP_CS_CTRL_REG0_PIXLODENABLE			0x00100000
4429 #define A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK			0xfe000000
4436 #define REG_A5XX_UNKNOWN_E5F2					0x0000e5f2
4438 #define REG_A5XX_SP_CS_OBJ_START_LO				0x0000e5f3
4440 #define REG_A5XX_SP_CS_OBJ_START_HI				0x0000e5f4
4442 #define REG_A5XX_SP_HS_CTRL_REG0				0x0000e600
4443 #define A5XX_SP_HS_CTRL_REG0_THREADSIZE__MASK			0x00000008
4449 #define A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x000003f0
4455 #define A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x0000fc00
4461 #define A5XX_SP_HS_CTRL_REG0_VARYING				0x00010000
4462 #define A5XX_SP_HS_CTRL_REG0_PIXLODENABLE			0x00100000
4463 #define A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK			0xfe000000
4470 #define REG_A5XX_UNKNOWN_E602					0x0000e602
4472 #define REG_A5XX_SP_HS_OBJ_START_LO				0x0000e603
4474 #define REG_A5XX_SP_HS_OBJ_START_HI				0x0000e604
4476 #define REG_A5XX_SP_DS_CTRL_REG0				0x0000e610
4477 #define A5XX_SP_DS_CTRL_REG0_THREADSIZE__MASK			0x00000008
4483 #define A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x000003f0
4489 #define A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x0000fc00
4495 #define A5XX_SP_DS_CTRL_REG0_VARYING				0x00010000
4496 #define A5XX_SP_DS_CTRL_REG0_PIXLODENABLE			0x00100000
4497 #define A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK			0xfe000000
4504 #define REG_A5XX_UNKNOWN_E62B					0x0000e62b
4506 #define REG_A5XX_SP_DS_OBJ_START_LO				0x0000e62c
4508 #define REG_A5XX_SP_DS_OBJ_START_HI				0x0000e62d
4510 #define REG_A5XX_SP_GS_CTRL_REG0				0x0000e640
4511 #define A5XX_SP_GS_CTRL_REG0_THREADSIZE__MASK			0x00000008
4517 #define A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK		0x000003f0
4523 #define A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK		0x0000fc00
4529 #define A5XX_SP_GS_CTRL_REG0_VARYING				0x00010000
4530 #define A5XX_SP_GS_CTRL_REG0_PIXLODENABLE			0x00100000
4531 #define A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK			0xfe000000
4538 #define REG_A5XX_UNKNOWN_E65B					0x0000e65b
4540 #define REG_A5XX_SP_GS_OBJ_START_LO				0x0000e65c
4542 #define REG_A5XX_SP_GS_OBJ_START_HI				0x0000e65d
4544 #define REG_A5XX_TPL1_TP_RAS_MSAA_CNTL				0x0000e704
4545 #define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK		0x00000003
4546 #define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT		0
4552 #define REG_A5XX_TPL1_TP_DEST_MSAA_CNTL				0x0000e705
4553 #define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__MASK		0x00000003
4554 #define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT		0
4559 #define A5XX_TPL1_TP_DEST_MSAA_CNTL_MSAA_DISABLE		0x00000004
4561 #define REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO		0x0000e706
4563 #define REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_HI		0x0000e707
4565 #define REG_A5XX_TPL1_VS_TEX_COUNT				0x0000e700
4567 #define REG_A5XX_TPL1_HS_TEX_COUNT				0x0000e701
4569 #define REG_A5XX_TPL1_DS_TEX_COUNT				0x0000e702
4571 #define REG_A5XX_TPL1_GS_TEX_COUNT				0x0000e703
4573 #define REG_A5XX_TPL1_VS_TEX_SAMP_LO				0x0000e722
4575 #define REG_A5XX_TPL1_VS_TEX_SAMP_HI				0x0000e723
4577 #define REG_A5XX_TPL1_HS_TEX_SAMP_LO				0x0000e724
4579 #define REG_A5XX_TPL1_HS_TEX_SAMP_HI				0x0000e725
4581 #define REG_A5XX_TPL1_DS_TEX_SAMP_LO				0x0000e726
4583 #define REG_A5XX_TPL1_DS_TEX_SAMP_HI				0x0000e727
4585 #define REG_A5XX_TPL1_GS_TEX_SAMP_LO				0x0000e728
4587 #define REG_A5XX_TPL1_GS_TEX_SAMP_HI				0x0000e729
4589 #define REG_A5XX_TPL1_VS_TEX_CONST_LO				0x0000e72a
4591 #define REG_A5XX_TPL1_VS_TEX_CONST_HI				0x0000e72b
4593 #define REG_A5XX_TPL1_HS_TEX_CONST_LO				0x0000e72c
4595 #define REG_A5XX_TPL1_HS_TEX_CONST_HI				0x0000e72d
4597 #define REG_A5XX_TPL1_DS_TEX_CONST_LO				0x0000e72e
4599 #define REG_A5XX_TPL1_DS_TEX_CONST_HI				0x0000e72f
4601 #define REG_A5XX_TPL1_GS_TEX_CONST_LO				0x0000e730
4603 #define REG_A5XX_TPL1_GS_TEX_CONST_HI				0x0000e731
4605 #define REG_A5XX_TPL1_FS_TEX_COUNT				0x0000e750
4607 #define REG_A5XX_TPL1_CS_TEX_COUNT				0x0000e751
4609 #define REG_A5XX_TPL1_FS_TEX_SAMP_LO				0x0000e75a
4611 #define REG_A5XX_TPL1_FS_TEX_SAMP_HI				0x0000e75b
4613 #define REG_A5XX_TPL1_CS_TEX_SAMP_LO				0x0000e75c
4615 #define REG_A5XX_TPL1_CS_TEX_SAMP_HI				0x0000e75d
4617 #define REG_A5XX_TPL1_FS_TEX_CONST_LO				0x0000e75e
4619 #define REG_A5XX_TPL1_FS_TEX_CONST_HI				0x0000e75f
4621 #define REG_A5XX_TPL1_CS_TEX_CONST_LO				0x0000e760
4623 #define REG_A5XX_TPL1_CS_TEX_CONST_HI				0x0000e761
4625 #define REG_A5XX_TPL1_TP_FS_ROTATION_CNTL			0x0000e764
4627 #define REG_A5XX_HLSQ_CONTROL_0_REG				0x0000e784
4628 #define A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK		0x00000001
4629 #define A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT		0
4634 #define A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__MASK		0x00000004
4641 #define REG_A5XX_HLSQ_CONTROL_1_REG				0x0000e785
4642 #define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK	0x0000003f
4643 #define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT	0
4649 #define REG_A5XX_HLSQ_CONTROL_2_REG				0x0000e786
4650 #define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK			0x000000ff
4651 #define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT		0
4656 #define A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK			0x0000ff00
4662 #define A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK		0x00ff0000
4668 #define A5XX_HLSQ_CONTROL_2_REG_SIZE__MASK			0xff000000
4675 #define REG_A5XX_HLSQ_CONTROL_3_REG				0x0000e787
4676 #define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK		0x000000ff
4677 #define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT		0
4682 #define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK		0x0000ff00
4688 #define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK		0x00ff0000
4694 #define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK	0xff000000
4701 #define REG_A5XX_HLSQ_CONTROL_4_REG				0x0000e788
4702 #define A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK		0x000000ff
4703 #define A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT		0
4708 #define A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK		0x0000ff00
4714 #define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK		0x00ff0000
4720 #define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK		0xff000000
4727 #define REG_A5XX_HLSQ_UPDATE_CNTL				0x0000e78a
4729 #define REG_A5XX_HLSQ_VS_CONFIG					0x0000e78b
4730 #define A5XX_HLSQ_VS_CONFIG_ENABLED				0x00000001
4731 #define A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__MASK		0x000000fe
4737 #define A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__MASK		0x00007f00
4744 #define REG_A5XX_HLSQ_FS_CONFIG					0x0000e78c
4745 #define A5XX_HLSQ_FS_CONFIG_ENABLED				0x00000001
4746 #define A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__MASK		0x000000fe
4752 #define A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__MASK		0x00007f00
4759 #define REG_A5XX_HLSQ_HS_CONFIG					0x0000e78d
4760 #define A5XX_HLSQ_HS_CONFIG_ENABLED				0x00000001
4761 #define A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__MASK		0x000000fe
4767 #define A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__MASK		0x00007f00
4774 #define REG_A5XX_HLSQ_DS_CONFIG					0x0000e78e
4775 #define A5XX_HLSQ_DS_CONFIG_ENABLED				0x00000001
4776 #define A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__MASK		0x000000fe
4782 #define A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__MASK		0x00007f00
4789 #define REG_A5XX_HLSQ_GS_CONFIG					0x0000e78f
4790 #define A5XX_HLSQ_GS_CONFIG_ENABLED				0x00000001
4791 #define A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__MASK		0x000000fe
4797 #define A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__MASK		0x00007f00
4804 #define REG_A5XX_HLSQ_CS_CONFIG					0x0000e790
4805 #define A5XX_HLSQ_CS_CONFIG_ENABLED				0x00000001
4806 #define A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__MASK		0x000000fe
4812 #define A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__MASK		0x00007f00
4819 #define REG_A5XX_HLSQ_VS_CNTL					0x0000e791
4820 #define A5XX_HLSQ_VS_CNTL_SSBO_ENABLE				0x00000001
4821 #define A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK			0xfffffffe
4828 #define REG_A5XX_HLSQ_FS_CNTL					0x0000e792
4829 #define A5XX_HLSQ_FS_CNTL_SSBO_ENABLE				0x00000001
4830 #define A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK			0xfffffffe
4837 #define REG_A5XX_HLSQ_HS_CNTL					0x0000e793
4838 #define A5XX_HLSQ_HS_CNTL_SSBO_ENABLE				0x00000001
4839 #define A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK			0xfffffffe
4846 #define REG_A5XX_HLSQ_DS_CNTL					0x0000e794
4847 #define A5XX_HLSQ_DS_CNTL_SSBO_ENABLE				0x00000001
4848 #define A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK			0xfffffffe
4855 #define REG_A5XX_HLSQ_GS_CNTL					0x0000e795
4856 #define A5XX_HLSQ_GS_CNTL_SSBO_ENABLE				0x00000001
4857 #define A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK			0xfffffffe
4864 #define REG_A5XX_HLSQ_CS_CNTL					0x0000e796
4865 #define A5XX_HLSQ_CS_CNTL_SSBO_ENABLE				0x00000001
4866 #define A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK			0xfffffffe
4873 #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_X				0x0000e7b9
4875 #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Y				0x0000e7ba
4877 #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Z				0x0000e7bb
4879 #define REG_A5XX_HLSQ_CS_NDRANGE_0				0x0000e7b0
4880 #define A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK			0x00000003
4881 #define A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT			0
4886 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK			0x00000ffc
4892 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK			0x003ff000
4898 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK			0xffc00000
4905 #define REG_A5XX_HLSQ_CS_NDRANGE_1				0x0000e7b1
4906 #define A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK		0xffffffff
4907 #define A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT		0
4913 #define REG_A5XX_HLSQ_CS_NDRANGE_2				0x0000e7b2
4914 #define A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK		0xffffffff
4915 #define A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT		0
4921 #define REG_A5XX_HLSQ_CS_NDRANGE_3				0x0000e7b3
4922 #define A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK		0xffffffff
4923 #define A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT		0
4929 #define REG_A5XX_HLSQ_CS_NDRANGE_4				0x0000e7b4
4930 #define A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK		0xffffffff
4931 #define A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT		0
4937 #define REG_A5XX_HLSQ_CS_NDRANGE_5				0x0000e7b5
4938 #define A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK		0xffffffff
4939 #define A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT		0
4945 #define REG_A5XX_HLSQ_CS_NDRANGE_6				0x0000e7b6
4946 #define A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK		0xffffffff
4947 #define A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT		0
4953 #define REG_A5XX_HLSQ_CS_CNTL_0					0x0000e7b7
4954 #define A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK			0x000000ff
4955 #define A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT			0
4960 #define A5XX_HLSQ_CS_CNTL_0_UNK0__MASK				0x0000ff00
4966 #define A5XX_HLSQ_CS_CNTL_0_UNK1__MASK				0x00ff0000
4972 #define A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK			0xff000000
4979 #define REG_A5XX_HLSQ_CS_CNTL_1					0x0000e7b8
4981 #define REG_A5XX_UNKNOWN_E7C0					0x0000e7c0
4983 #define REG_A5XX_HLSQ_VS_CONSTLEN				0x0000e7c3
4985 #define REG_A5XX_HLSQ_VS_INSTRLEN				0x0000e7c4
4987 #define REG_A5XX_UNKNOWN_E7C5					0x0000e7c5
4989 #define REG_A5XX_HLSQ_HS_CONSTLEN				0x0000e7c8
4991 #define REG_A5XX_HLSQ_HS_INSTRLEN				0x0000e7c9
4993 #define REG_A5XX_UNKNOWN_E7CA					0x0000e7ca
4995 #define REG_A5XX_HLSQ_DS_CONSTLEN				0x0000e7cd
4997 #define REG_A5XX_HLSQ_DS_INSTRLEN				0x0000e7ce
4999 #define REG_A5XX_UNKNOWN_E7CF					0x0000e7cf
5001 #define REG_A5XX_HLSQ_GS_CONSTLEN				0x0000e7d2
5003 #define REG_A5XX_HLSQ_GS_INSTRLEN				0x0000e7d3
5005 #define REG_A5XX_UNKNOWN_E7D4					0x0000e7d4
5007 #define REG_A5XX_HLSQ_FS_CONSTLEN				0x0000e7d7
5009 #define REG_A5XX_HLSQ_FS_INSTRLEN				0x0000e7d8
5011 #define REG_A5XX_UNKNOWN_E7D9					0x0000e7d9
5013 #define REG_A5XX_HLSQ_CS_CONSTLEN				0x0000e7dc
5015 #define REG_A5XX_HLSQ_CS_INSTRLEN				0x0000e7dd
5017 #define REG_A5XX_RB_2D_BLIT_CNTL				0x00002100
5019 #define REG_A5XX_RB_2D_SRC_SOLID_DW0				0x00002101
5021 #define REG_A5XX_RB_2D_SRC_SOLID_DW1				0x00002102
5023 #define REG_A5XX_RB_2D_SRC_SOLID_DW2				0x00002103
5025 #define REG_A5XX_RB_2D_SRC_SOLID_DW3				0x00002104
5027 #define REG_A5XX_RB_2D_SRC_INFO					0x00002107
5028 #define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK			0x000000ff
5029 #define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT			0
5034 #define A5XX_RB_2D_SRC_INFO_TILE_MODE__MASK			0x00000300
5040 #define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK			0x00000c00
5046 #define A5XX_RB_2D_SRC_INFO_FLAGS				0x00001000
5047 #define A5XX_RB_2D_SRC_INFO_SRGB				0x00002000
5049 #define REG_A5XX_RB_2D_SRC_LO					0x00002108
5051 #define REG_A5XX_RB_2D_SRC_HI					0x00002109
5053 #define REG_A5XX_RB_2D_SRC_SIZE					0x0000210a
5054 #define A5XX_RB_2D_SRC_SIZE_PITCH__MASK				0x0000ffff
5055 #define A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT			0
5060 #define A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK			0xffff0000
5067 #define REG_A5XX_RB_2D_DST_INFO					0x00002110
5068 #define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK			0x000000ff
5069 #define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT			0
5074 #define A5XX_RB_2D_DST_INFO_TILE_MODE__MASK			0x00000300
5080 #define A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK			0x00000c00
5086 #define A5XX_RB_2D_DST_INFO_FLAGS				0x00001000
5087 #define A5XX_RB_2D_DST_INFO_SRGB				0x00002000
5089 #define REG_A5XX_RB_2D_DST_LO					0x00002111
5091 #define REG_A5XX_RB_2D_DST_HI					0x00002112
5093 #define REG_A5XX_RB_2D_DST_SIZE					0x00002113
5094 #define A5XX_RB_2D_DST_SIZE_PITCH__MASK				0x0000ffff
5095 #define A5XX_RB_2D_DST_SIZE_PITCH__SHIFT			0
5100 #define A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK			0xffff0000
5107 #define REG_A5XX_RB_2D_SRC_FLAGS_LO				0x00002140
5109 #define REG_A5XX_RB_2D_SRC_FLAGS_HI				0x00002141
5111 #define REG_A5XX_RB_2D_SRC_FLAGS_PITCH				0x00002142
5112 #define A5XX_RB_2D_SRC_FLAGS_PITCH__MASK			0xffffffff
5113 #define A5XX_RB_2D_SRC_FLAGS_PITCH__SHIFT			0
5119 #define REG_A5XX_RB_2D_DST_FLAGS_LO				0x00002143
5121 #define REG_A5XX_RB_2D_DST_FLAGS_HI				0x00002144
5123 #define REG_A5XX_RB_2D_DST_FLAGS_PITCH				0x00002145
5124 #define A5XX_RB_2D_DST_FLAGS_PITCH__MASK			0xffffffff
5125 #define A5XX_RB_2D_DST_FLAGS_PITCH__SHIFT			0
5131 #define REG_A5XX_GRAS_2D_BLIT_CNTL				0x00002180
5133 #define REG_A5XX_GRAS_2D_SRC_INFO				0x00002181
5134 #define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK		0x000000ff
5135 #define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT		0
5140 #define A5XX_GRAS_2D_SRC_INFO_TILE_MODE__MASK			0x00000300
5146 #define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK			0x00000c00
5152 #define A5XX_GRAS_2D_SRC_INFO_FLAGS				0x00001000
5153 #define A5XX_GRAS_2D_SRC_INFO_SRGB				0x00002000
5155 #define REG_A5XX_GRAS_2D_DST_INFO				0x00002182
5156 #define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK		0x000000ff
5157 #define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT		0
5162 #define A5XX_GRAS_2D_DST_INFO_TILE_MODE__MASK			0x00000300
5168 #define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK			0x00000c00
5174 #define A5XX_GRAS_2D_DST_INFO_FLAGS				0x00001000
5175 #define A5XX_GRAS_2D_DST_INFO_SRGB				0x00002000
5177 #define REG_A5XX_UNKNOWN_2184					0x00002184
5179 #define REG_A5XX_TEX_SAMP_0					0x00000000
5180 #define A5XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR			0x00000001
5181 #define A5XX_TEX_SAMP_0_XY_MAG__MASK				0x00000006
5187 #define A5XX_TEX_SAMP_0_XY_MIN__MASK				0x00000018
5193 #define A5XX_TEX_SAMP_0_WRAP_S__MASK				0x000000e0
5199 #define A5XX_TEX_SAMP_0_WRAP_T__MASK				0x00000700
5205 #define A5XX_TEX_SAMP_0_WRAP_R__MASK				0x00003800
5211 #define A5XX_TEX_SAMP_0_ANISO__MASK				0x0001c000
5217 #define A5XX_TEX_SAMP_0_LOD_BIAS__MASK				0xfff80000
5224 #define REG_A5XX_TEX_SAMP_1					0x00000001
5225 #define A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK			0x0000000e
5231 #define A5XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF			0x00000010
5232 #define A5XX_TEX_SAMP_1_UNNORM_COORDS				0x00000020
5233 #define A5XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR			0x00000040
5234 #define A5XX_TEX_SAMP_1_MAX_LOD__MASK				0x000fff00
5240 #define A5XX_TEX_SAMP_1_MIN_LOD__MASK				0xfff00000
5247 #define REG_A5XX_TEX_SAMP_2					0x00000002
5248 #define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK			0xffffff80
5255 #define REG_A5XX_TEX_SAMP_3					0x00000003
5257 #define REG_A5XX_TEX_CONST_0					0x00000000
5258 #define A5XX_TEX_CONST_0_TILE_MODE__MASK			0x00000003
5259 #define A5XX_TEX_CONST_0_TILE_MODE__SHIFT			0
5264 #define A5XX_TEX_CONST_0_SRGB					0x00000004
5265 #define A5XX_TEX_CONST_0_SWIZ_X__MASK				0x00000070
5271 #define A5XX_TEX_CONST_0_SWIZ_Y__MASK				0x00000380
5277 #define A5XX_TEX_CONST_0_SWIZ_Z__MASK				0x00001c00
5283 #define A5XX_TEX_CONST_0_SWIZ_W__MASK				0x0000e000
5289 #define A5XX_TEX_CONST_0_MIPLVLS__MASK				0x000f0000
5295 #define A5XX_TEX_CONST_0_SAMPLES__MASK				0x00300000
5301 #define A5XX_TEX_CONST_0_FMT__MASK				0x3fc00000
5307 #define A5XX_TEX_CONST_0_SWAP__MASK				0xc0000000
5314 #define REG_A5XX_TEX_CONST_1					0x00000001
5315 #define A5XX_TEX_CONST_1_WIDTH__MASK				0x00007fff
5316 #define A5XX_TEX_CONST_1_WIDTH__SHIFT				0
5321 #define A5XX_TEX_CONST_1_HEIGHT__MASK				0x3fff8000
5328 #define REG_A5XX_TEX_CONST_2					0x00000002
5329 #define A5XX_TEX_CONST_2_BUFFER					0x00000010
5330 #define A5XX_TEX_CONST_2_PITCHALIGN__MASK			0x0000000f
5331 #define A5XX_TEX_CONST_2_PITCHALIGN__SHIFT			0
5336 #define A5XX_TEX_CONST_2_PITCH__MASK				0x1fffff80
5342 #define A5XX_TEX_CONST_2_TYPE__MASK				0xe0000000
5349 #define REG_A5XX_TEX_CONST_3					0x00000003
5350 #define A5XX_TEX_CONST_3_ARRAY_PITCH__MASK			0x00003fff
5351 #define A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT			0
5356 #define A5XX_TEX_CONST_3_MIN_LAYERSZ__MASK			0x07800000
5362 #define A5XX_TEX_CONST_3_TILE_ALL				0x08000000
5363 #define A5XX_TEX_CONST_3_FLAG					0x10000000
5365 #define REG_A5XX_TEX_CONST_4					0x00000004
5366 #define A5XX_TEX_CONST_4_BASE_LO__MASK				0xffffffe0
5373 #define REG_A5XX_TEX_CONST_5					0x00000005
5374 #define A5XX_TEX_CONST_5_BASE_HI__MASK				0x0001ffff
5375 #define A5XX_TEX_CONST_5_BASE_HI__SHIFT				0
5380 #define A5XX_TEX_CONST_5_DEPTH__MASK				0x3ffe0000
5387 #define REG_A5XX_TEX_CONST_6					0x00000006
5389 #define REG_A5XX_TEX_CONST_7					0x00000007
5391 #define REG_A5XX_TEX_CONST_8					0x00000008
5393 #define REG_A5XX_TEX_CONST_9					0x00000009
5395 #define REG_A5XX_TEX_CONST_10					0x0000000a
5397 #define REG_A5XX_TEX_CONST_11					0x0000000b
5399 #define REG_A5XX_SSBO_0_0					0x00000000
5400 #define A5XX_SSBO_0_0_BASE_LO__MASK				0xffffffe0
5407 #define REG_A5XX_SSBO_0_1					0x00000001
5408 #define A5XX_SSBO_0_1_PITCH__MASK				0x003fffff
5409 #define A5XX_SSBO_0_1_PITCH__SHIFT				0
5415 #define REG_A5XX_SSBO_0_2					0x00000002
5416 #define A5XX_SSBO_0_2_ARRAY_PITCH__MASK				0x03fff000
5423 #define REG_A5XX_SSBO_0_3					0x00000003
5424 #define A5XX_SSBO_0_3_CPP__MASK					0x0000003f
5425 #define A5XX_SSBO_0_3_CPP__SHIFT				0
5431 #define REG_A5XX_SSBO_1_0					0x00000000
5432 #define A5XX_SSBO_1_0_FMT__MASK					0x0000ff00
5438 #define A5XX_SSBO_1_0_WIDTH__MASK				0xffff0000
5445 #define REG_A5XX_SSBO_1_1					0x00000001
5446 #define A5XX_SSBO_1_1_HEIGHT__MASK				0x0000ffff
5447 #define A5XX_SSBO_1_1_HEIGHT__SHIFT				0
5452 #define A5XX_SSBO_1_1_DEPTH__MASK				0xffff0000
5459 #define REG_A5XX_SSBO_2_0					0x00000000
5460 #define A5XX_SSBO_2_0_BASE_LO__MASK				0xffffffff
5461 #define A5XX_SSBO_2_0_BASE_LO__SHIFT				0
5467 #define REG_A5XX_SSBO_2_1					0x00000001
5468 #define A5XX_SSBO_2_1_BASE_HI__MASK				0xffffffff
5469 #define A5XX_SSBO_2_1_BASE_HI__SHIFT				0
5475 #define REG_A5XX_UBO_0						0x00000000
5476 #define A5XX_UBO_0_BASE_LO__MASK				0xffffffff
5477 #define A5XX_UBO_0_BASE_LO__SHIFT				0
5483 #define REG_A5XX_UBO_1						0x00000001
5484 #define A5XX_UBO_1_BASE_HI__MASK				0x0001ffff
5485 #define A5XX_UBO_1_BASE_HI__SHIFT				0