Lines Matching +full:invert +full:- +full:interrupt

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12  * Bit 15-10: RW Reserved. Default 1 starting from G12A
20  * Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset;
34  * Bit 12 RW i2s_ws_inv:1=Invert i2s_ws; 0=No invert. Default 0.
35  * Bit 11 RW i2s_clk_inv: 1=Invert i2s_clk; 0=No invert. Default 0.
36  * Bit 10 RW spdif_clk_inv: 1=Invert spdif_clk; 0=No invert. Default 0.
37  * Bit 9 RW tmds_clk_inv: 1=Invert tmds_clk; 0=No invert. Default 0.
38  * Bit 8 RW pixel_clk_inv: 1=Invert pixel_clk; 0=No invert. Default 0.
59  * intr_maskn: MASK_N, one bit per interrupt source.
60  *     1=Enable interrupt source; 0=Disable interrupt source. Default 0.
73  * Bit 30: 0 RW intr_stat: For each bit, write 1 to manually set the interrupt
74  *     bit, read back the interrupt status.
75  * Bit    31 R  IP interrupt status
81  * Bit     0 RW IP interrupt
111  * Bit 2: 1 RW prbs_pttn_width: 0=idle; 1=output 8-bit pattern;
112  *     2=Output 1-bit pattern; 3=output 10-bit pattern. Default 0.