1 // SPDX-License-Identifier: GPL-2.0-only
17 #include <linux/soc/mediatek/mtk-cmdq.h>
42 #define DISP_REG_OVL_ADDR(ovl, n)		((ovl)->data->addr + 0x20 * (n))
55 #define OVL_CON_CLRFMT_RGB565(ovl)	((ovl)->data->fmt_rgb565_is_0 ? \
57 #define OVL_CON_CLRFMT_RGB888(ovl)	((ovl)->data->fmt_rgb565_is_0 ? \
73  * struct mtk_disp_ovl - DISP_OVL driver structure
74  * @crtc: associated crtc to report vblank events to
92 	writel(0x0, priv->regs + DISP_REG_OVL_INTSTA);  in mtk_disp_ovl_irq_handler()
94 	if (!priv->vblank_cb)  in mtk_disp_ovl_irq_handler()
97 	priv->vblank_cb(priv->vblank_cb_data);  in mtk_disp_ovl_irq_handler()
108 	ovl->vblank_cb = vblank_cb;  in mtk_ovl_register_vblank_cb()
109 	ovl->vblank_cb_data = vblank_cb_data;  in mtk_ovl_register_vblank_cb()
116 	ovl->vblank_cb = NULL;  in mtk_ovl_unregister_vblank_cb()
117 	ovl->vblank_cb_data = NULL;  in mtk_ovl_unregister_vblank_cb()
124 	writel(0x0, ovl->regs + DISP_REG_OVL_INTSTA);  in mtk_ovl_enable_vblank()
125 	writel_relaxed(OVL_FME_CPL_INT, ovl->regs + DISP_REG_OVL_INTEN);  in mtk_ovl_enable_vblank()
132 	writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_INTEN);  in mtk_ovl_disable_vblank()
139 	return clk_prepare_enable(ovl->clk);  in mtk_ovl_clk_enable()
146 	clk_disable_unprepare(ovl->clk);  in mtk_ovl_clk_disable()
153 	if (ovl->data->smi_id_en) {  in mtk_ovl_start()
156 		reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_start()
158 		writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_start()
160 	writel_relaxed(0x1, ovl->regs + DISP_REG_OVL_EN);  in mtk_ovl_start()
167 	writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_EN);  in mtk_ovl_stop()
168 	if (ovl->data->smi_id_en) {  in mtk_ovl_stop()
171 		reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_stop()
173 		writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_stop()
185 		mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_config()
187 	mtk_ddp_write_relaxed(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_ROI_BGCLR);  in mtk_ovl_config()
189 	mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST);  in mtk_ovl_config()
190 	mtk_ddp_write(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST);  in mtk_ovl_config()
197 	return ovl->data->layer_nr;  in mtk_ovl_layer_nr()
209 	struct drm_plane_state *state = &mtk_state->base;  in mtk_ovl_layer_check()
212 	rotation = drm_rotation_simplify(state->rotation,  in mtk_ovl_layer_check()
220 		return -EINVAL;  in mtk_ovl_layer_check()
226 	if (state->fb->format->is_yuv && rotation != 0)  in mtk_ovl_layer_check()
227 		return -EINVAL;  in mtk_ovl_layer_check()
229 	state->rotation = rotation;  in mtk_ovl_layer_check()
242 	mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_on()
245 		      (GMC_THRESHOLD_BITS - ovl->data->gmc_bits);  in mtk_ovl_layer_on()
247 		      (GMC_THRESHOLD_BITS - ovl->data->gmc_bits);  in mtk_ovl_layer_on()
248 	if (ovl->data->gmc_bits == 10)  in mtk_ovl_layer_on()
254 		      &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RDMA_GMC(idx));  in mtk_ovl_layer_on()
255 	mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_on()
264 	mtk_ddp_write_mask(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_off()
266 	mtk_ddp_write(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_off()
311 	struct mtk_plane_pending_state *pending = &state->pending;  in mtk_ovl_layer_config()
312 	unsigned int addr = pending->addr;  in mtk_ovl_layer_config()
313 	unsigned int pitch = pending->pitch & 0xffff;  in mtk_ovl_layer_config()
314 	unsigned int fmt = pending->format;  in mtk_ovl_layer_config()
315 	unsigned int offset = (pending->y << 16) | pending->x;  in mtk_ovl_layer_config()
316 	unsigned int src_size = (pending->height << 16) | pending->width;  in mtk_ovl_layer_config()
319 	if (!pending->enable) {  in mtk_ovl_layer_config()
325 	if (state->base.fb && state->base.fb->format->has_alpha)  in mtk_ovl_layer_config()
328 	if (pending->rotation & DRM_MODE_REFLECT_Y) {  in mtk_ovl_layer_config()
330 		addr += (pending->height - 1) * pending->pitch;  in mtk_ovl_layer_config()
333 	if (pending->rotation & DRM_MODE_REFLECT_X) {  in mtk_ovl_layer_config()
335 		addr += pending->pitch - 1;  in mtk_ovl_layer_config()
338 	mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_config()
340 	mtk_ddp_write_relaxed(cmdq_pkt, pitch, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_config()
342 	mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_config()
344 	mtk_ddp_write_relaxed(cmdq_pkt, offset, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_config()
346 	mtk_ddp_write_relaxed(cmdq_pkt, addr, &ovl->cmdq_reg, ovl->regs,  in mtk_ovl_layer_config()
357 	reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_bgclr_in_on()
359 	writel(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_bgclr_in_on()
367 	reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_bgclr_in_off()
369 	writel(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);  in mtk_ovl_bgclr_in_off()
390 	struct device *dev = &pdev->dev;  in mtk_disp_ovl_probe()
398 		return -ENOMEM;  in mtk_disp_ovl_probe()
404 	priv->clk = devm_clk_get(dev, NULL);  in mtk_disp_ovl_probe()
405 	if (IS_ERR(priv->clk)) {  in mtk_disp_ovl_probe()
407 		return PTR_ERR(priv->clk);  in mtk_disp_ovl_probe()
411 	priv->regs = devm_ioremap_resource(dev, res);  in mtk_disp_ovl_probe()
412 	if (IS_ERR(priv->regs)) {  in mtk_disp_ovl_probe()
414 		return PTR_ERR(priv->regs);  in mtk_disp_ovl_probe()
417 	ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);  in mtk_disp_ovl_probe()
419 		dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");  in mtk_disp_ovl_probe()
422 	priv->data = of_device_get_match_data(dev);  in mtk_disp_ovl_probe()
445 	component_del(&pdev->dev, &mtk_disp_ovl_component_ops);  in mtk_disp_ovl_remove()
446 	pm_runtime_disable(&pdev->dev);  in mtk_disp_ovl_remove()
496 	{ .compatible = "mediatek,mt2701-disp-ovl",
498 	{ .compatible = "mediatek,mt8173-disp-ovl",
500 	{ .compatible = "mediatek,mt8183-disp-ovl",
502 	{ .compatible = "mediatek,mt8183-disp-ovl-2l",
504 	{ .compatible = "mediatek,mt8192-disp-ovl",
506 	{ .compatible = "mediatek,mt8192-disp-ovl-2l",
516 		.name	= "mediatek-disp-ovl",