1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk-provider.h>
9 /* The MCDE internal clock dividers for FIFO A and B */
20 	struct mcde *mcde = cdiv->mcde;  in mcde_clk_div_enable()
23 	spin_lock(&mcde->fifo_crx1_lock);  in mcde_clk_div_enable()
24 	val = readl(mcde->regs + cdiv->cr);  in mcde_clk_div_enable()
26 	 * Select the PLL72 (LCD) clock as parent  in mcde_clk_div_enable()
31 	/* Internal clock */  in mcde_clk_div_enable()
36 	val |= cdiv->cr_div;  in mcde_clk_div_enable()
38 	writel(val, mcde->regs + cdiv->cr);  in mcde_clk_div_enable()
39 	spin_unlock(&mcde->fifo_crx1_lock);  in mcde_clk_div_enable()
47 	int best_div = 1, div;  in mcde_clk_div_choose_div()  local
51 	int max_div = (1 << MCDE_CRX1_PCD_BITS) - 1;  in mcde_clk_div_choose_div()
53 	for (div = 1; div < max_div; div++) {  in mcde_clk_div_choose_div()
57 			this_prate = clk_hw_round_rate(parent, rate * div);  in mcde_clk_div_choose_div()
60 		div_rate = DIV_ROUND_UP_ULL(this_prate, div);  in mcde_clk_div_choose_div()
61 		diff = abs(rate - div_rate);  in mcde_clk_div_choose_div()
64 			best_div = div;  in mcde_clk_div_choose_div()
77 	int div = mcde_clk_div_choose_div(hw, rate, prate, true);  in mcde_clk_div_round_rate()  local
79 	return DIV_ROUND_UP_ULL(*prate, div);  in mcde_clk_div_round_rate()
86 	struct mcde *mcde = cdiv->mcde;  in mcde_clk_div_recalc_rate()
88 	int div;  in mcde_clk_div_recalc_rate()  local
95 	if (!regulator_is_enabled(mcde->epod))  in mcde_clk_div_recalc_rate()
98 	cr = readl(mcde->regs + cdiv->cr);  in mcde_clk_div_recalc_rate()
103 	div = cr & MCDE_CRX1_PCD_MASK;  in mcde_clk_div_recalc_rate()
104 	div += 2;  in mcde_clk_div_recalc_rate()
106 	return DIV_ROUND_UP_ULL(prate, div);  in mcde_clk_div_recalc_rate()
113 	int div = mcde_clk_div_choose_div(hw, rate, &prate, false);  in mcde_clk_div_set_rate()  local
120 	if (div == 1) {  in mcde_clk_div_set_rate()
121 		/* Bypass clock divider */  in mcde_clk_div_set_rate()
124 		div -= 2;  in mcde_clk_div_set_rate()
125 		cr |= div & MCDE_CRX1_PCD_MASK;  in mcde_clk_div_set_rate()
127 	cdiv->cr_div = cr;  in mcde_clk_div_set_rate()
141 	struct device *dev = mcde->dev;  in mcde_init_clock_divider()
161 	spin_lock_init(&mcde->fifo_crx1_lock);  in mcde_init_clock_divider()
162 	parent_name = __clk_get_name(mcde->lcd_clk);  in mcde_init_clock_divider()
167 		return -ENOMEM;  in mcde_init_clock_divider()
170 		return -ENOMEM;  in mcde_init_clock_divider()
172 	fifoa->mcde = mcde;  in mcde_init_clock_divider()
173 	fifoa->cr = MCDE_CRA1;  in mcde_init_clock_divider()
174 	fifoa->hw.init = &fifoa_init;  in mcde_init_clock_divider()
175 	ret = devm_clk_hw_register(dev, &fifoa->hw);  in mcde_init_clock_divider()
177 		dev_err(dev, "error registering FIFO A clock divider\n");  in mcde_init_clock_divider()
180 	mcde->fifoa_clk = fifoa->hw.clk;  in mcde_init_clock_divider()
182 	fifob->mcde = mcde;  in mcde_init_clock_divider()
183 	fifob->cr = MCDE_CRB1;  in mcde_init_clock_divider()
184 	fifob->hw.init = &fifob_init;  in mcde_init_clock_divider()
185 	ret = devm_clk_hw_register(dev, &fifob->hw);  in mcde_init_clock_divider()
187 		dev_err(dev, "error registering FIFO B clock divider\n");  in mcde_init_clock_divider()
190 	mcde->fifob_clk = fifob->hw.clk;  in mcde_init_clock_divider()