1 // SPDX-License-Identifier: GPL-2.0
13 #include "dcss-dev.h"
100 	if (!dtg->in_use)  in dcss_dtg_write()
101 		dcss_writel(val, dtg->base_reg + ofs);  in dcss_dtg_write()
103 	dcss_ctxld_write(dtg->ctxld, dtg->ctx_id,  in dcss_dtg_write()
104 			 val, dtg->base_ofs + ofs);  in dcss_dtg_write()
112 	status = dcss_readl(dtg->base_reg + DCSS_DTG_INT_STATUS);  in dcss_dtg_irq_handler()
117 	dcss_ctxld_kick(dtg->ctxld);  in dcss_dtg_irq_handler()
119 	dcss_writel(status & LINE0_IRQ, dtg->base_reg + DCSS_DTG_INT_CONTROL);  in dcss_dtg_irq_handler()
129 	dtg->ctxld_kick_irq = platform_get_irq_byname(pdev, "ctxld_kick");  in dcss_dtg_irq_config()
130 	if (dtg->ctxld_kick_irq < 0)  in dcss_dtg_irq_config()
131 		return dtg->ctxld_kick_irq;  in dcss_dtg_irq_config()
134 		    dtg->base_reg + DCSS_DTG_INT_MASK);  in dcss_dtg_irq_config()
136 	ret = request_irq(dtg->ctxld_kick_irq, dcss_dtg_irq_handler,  in dcss_dtg_irq_config()
139 		dev_err(dtg->dev, "dtg: irq request failed.\n");  in dcss_dtg_irq_config()
143 	disable_irq(dtg->ctxld_kick_irq);  in dcss_dtg_irq_config()
145 	dtg->ctxld_kick_irq_en = false;  in dcss_dtg_irq_config()
157 		return -ENOMEM;  in dcss_dtg_init()
159 	dcss->dtg = dtg;  in dcss_dtg_init()
160 	dtg->dev = dcss->dev;  in dcss_dtg_init()
161 	dtg->ctxld = dcss->ctxld;  in dcss_dtg_init()
163 	dtg->base_reg = ioremap(dtg_base, SZ_4K);  in dcss_dtg_init()
164 	if (!dtg->base_reg) {  in dcss_dtg_init()
165 		dev_err(dcss->dev, "dtg: unable to remap dtg base\n");  in dcss_dtg_init()
166 		ret = -ENOMEM;  in dcss_dtg_init()
170 	dtg->base_ofs = dtg_base;  in dcss_dtg_init()
171 	dtg->ctx_id = CTX_DB;  in dcss_dtg_init()
173 	dtg->alpha = 255;  in dcss_dtg_init()
175 	dtg->control_status |= OVL_DATA_MODE | BLENDER_VIDEO_ALPHA_SEL |  in dcss_dtg_init()
176 		((dtg->alpha << DEFAULT_FG_ALPHA_POS) & DEFAULT_FG_ALPHA_MASK);  in dcss_dtg_init()
178 	ret = dcss_dtg_irq_config(dtg, to_platform_device(dcss->dev));  in dcss_dtg_init()
185 	iounmap(dtg->base_reg);  in dcss_dtg_init()
195 	free_irq(dtg->ctxld_kick_irq, dtg);  in dcss_dtg_exit()
197 	if (dtg->base_reg)  in dcss_dtg_exit()
198 		iounmap(dtg->base_reg);  in dcss_dtg_exit()
205 	struct dcss_dev *dcss = dcss_drv_dev_to_dcss(dtg->dev);  in dcss_dtg_sync_set()
210 	u32 pixclock = vm->pixelclock;  in dcss_dtg_sync_set()
213 	dtg_lrc_x = vm->hfront_porch + vm->hback_porch + vm->hsync_len +  in dcss_dtg_sync_set()
214 		    vm->hactive - 1;  in dcss_dtg_sync_set()
215 	dtg_lrc_y = vm->vfront_porch + vm->vback_porch + vm->vsync_len +  in dcss_dtg_sync_set()
216 		    vm->vactive - 1;  in dcss_dtg_sync_set()
217 	dis_ulc_x = vm->hsync_len + vm->hback_porch - 1;  in dcss_dtg_sync_set()
218 	dis_ulc_y = vm->vsync_len + vm->vfront_porch + vm->vback_porch - 1;  in dcss_dtg_sync_set()
219 	dis_lrc_x = vm->hsync_len + vm->hback_porch + vm->hactive - 1;  in dcss_dtg_sync_set()
220 	dis_lrc_y = vm->vsync_len + vm->vfront_porch + vm->vback_porch +  in dcss_dtg_sync_set()
221 		    vm->vactive - 1;  in dcss_dtg_sync_set()
223 	clk_disable_unprepare(dcss->pix_clk);  in dcss_dtg_sync_set()
224 	clk_set_rate(dcss->pix_clk, vm->pixelclock);  in dcss_dtg_sync_set()
225 	clk_prepare_enable(dcss->pix_clk);  in dcss_dtg_sync_set()
227 	actual_clk = clk_get_rate(dcss->pix_clk);  in dcss_dtg_sync_set()
229 		dev_info(dtg->dev,  in dcss_dtg_sync_set()
241 	dtg->dis_ulc_x = dis_ulc_x;  in dcss_dtg_sync_set()
242 	dtg->dis_ulc_y = dis_ulc_y;  in dcss_dtg_sync_set()
264 	p_ulc_x = dtg->dis_ulc_x + px;  in dcss_dtg_plane_pos_set()
265 	p_ulc_y = dtg->dis_ulc_y + py;  in dcss_dtg_plane_pos_set()
285 	return alpha != dtg->alpha;  in dcss_dtg_global_alpha_changed()
296 	 * Use global alpha if pixel format does not have alpha channel or the  in dcss_dtg_plane_alpha_set()
297 	 * user explicitly chose to use global alpha (i.e. alpha is not OPAQUE).  in dcss_dtg_plane_alpha_set()
299 	if (!format->has_alpha || alpha != 255)  in dcss_dtg_plane_alpha_set()
300 		dtg->alpha_cfg = (alpha << DEFAULT_FG_ALPHA_POS) & DEFAULT_FG_ALPHA_MASK;  in dcss_dtg_plane_alpha_set()
301 	else /* use per-pixel alpha otherwise */  in dcss_dtg_plane_alpha_set()
302 		dtg->alpha_cfg = CH1_ALPHA_SEL;  in dcss_dtg_plane_alpha_set()
304 	dtg->alpha = alpha;  in dcss_dtg_plane_alpha_set()
309 	dtg->control_status |=  in dcss_dtg_css_set()
315 	dtg->control_status |= DTG_START;  in dcss_dtg_enable()
317 	dtg->control_status &= ~(CH1_ALPHA_SEL | DEFAULT_FG_ALPHA_MASK);  in dcss_dtg_enable()
318 	dtg->control_status |= dtg->alpha_cfg;  in dcss_dtg_enable()
320 	dcss_dtg_write(dtg, dtg->control_status, DCSS_DTG_TC_CONTROL_STATUS);  in dcss_dtg_enable()
322 	dtg->in_use = true;  in dcss_dtg_enable()
327 	dtg->control_status &= ~DTG_START;  in dcss_dtg_shutoff()
329 	dcss_writel(dtg->control_status,  in dcss_dtg_shutoff()
330 		    dtg->base_reg + DCSS_DTG_TC_CONTROL_STATUS);  in dcss_dtg_shutoff()
332 	dtg->in_use = false;  in dcss_dtg_shutoff()
337 	return dtg->in_use;  in dcss_dtg_is_enabled()
340 void dcss_dtg_ch_enable(struct dcss_dtg *dtg, int ch_num, bool en)  in dcss_dtg_ch_enable()  argument
345 	control_status = dtg->control_status & ~ch_en_map[ch_num];  in dcss_dtg_ch_enable()
346 	control_status |= en ? ch_en_map[ch_num] : 0;  in dcss_dtg_ch_enable()
349 	control_status |= dtg->alpha_cfg;  in dcss_dtg_ch_enable()
351 	if (dtg->control_status != control_status)  in dcss_dtg_ch_enable()
354 	dtg->control_status = control_status;  in dcss_dtg_ch_enable()
357 void dcss_dtg_vblank_irq_enable(struct dcss_dtg *dtg, bool en)  in dcss_dtg_vblank_irq_enable()  argument
360 	u32 mask = en ? LINE1_IRQ : 0;  in dcss_dtg_vblank_irq_enable()
362 	if (en) {  in dcss_dtg_vblank_irq_enable()
363 		status = dcss_readl(dtg->base_reg + DCSS_DTG_INT_STATUS);  in dcss_dtg_vblank_irq_enable()
365 			    dtg->base_reg + DCSS_DTG_INT_CONTROL);  in dcss_dtg_vblank_irq_enable()
368 	dcss_update(mask, LINE1_IRQ, dtg->base_reg + DCSS_DTG_INT_MASK);  in dcss_dtg_vblank_irq_enable()
371 void dcss_dtg_ctxld_kick_irq_enable(struct dcss_dtg *dtg, bool en)  in dcss_dtg_ctxld_kick_irq_enable()  argument
374 	u32 mask = en ? LINE0_IRQ : 0;  in dcss_dtg_ctxld_kick_irq_enable()
376 	if (en) {  in dcss_dtg_ctxld_kick_irq_enable()
377 		status = dcss_readl(dtg->base_reg + DCSS_DTG_INT_STATUS);  in dcss_dtg_ctxld_kick_irq_enable()
379 		if (!dtg->ctxld_kick_irq_en) {  in dcss_dtg_ctxld_kick_irq_enable()
381 				    dtg->base_reg + DCSS_DTG_INT_CONTROL);  in dcss_dtg_ctxld_kick_irq_enable()
382 			enable_irq(dtg->ctxld_kick_irq);  in dcss_dtg_ctxld_kick_irq_enable()
383 			dtg->ctxld_kick_irq_en = true;  in dcss_dtg_ctxld_kick_irq_enable()
385 				    dtg->base_reg + DCSS_DTG_INT_MASK);  in dcss_dtg_ctxld_kick_irq_enable()
391 	if (!dtg->ctxld_kick_irq_en)  in dcss_dtg_ctxld_kick_irq_enable()
394 	disable_irq_nosync(dtg->ctxld_kick_irq);  in dcss_dtg_ctxld_kick_irq_enable()
395 	dtg->ctxld_kick_irq_en = false;  in dcss_dtg_ctxld_kick_irq_enable()
397 	dcss_update(mask, LINE0_IRQ, dtg->base_reg + DCSS_DTG_INT_MASK);  in dcss_dtg_ctxld_kick_irq_enable()
402 	dcss_update(LINE1_IRQ, LINE1_IRQ, dtg->base_reg + DCSS_DTG_INT_CONTROL);  in dcss_dtg_vblank_irq_clear()
407 	return !!(dcss_readl(dtg->base_reg + DCSS_DTG_INT_STATUS) & LINE1_IRQ);  in dcss_dtg_vblank_irq_valid()