104 				 u32 guc_wopcm_base, u32 guc_wopcm_size)  in gen9_check_dword_gap()  argument
113 	offset = guc_wopcm_base + GEN9_GUC_WOPCM_OFFSET;  in gen9_check_dword_gap()
146 				  u32 guc_wopcm_base, u32 guc_wopcm_size,  in check_hw_restrictions()  argument
149 	if (GRAPHICS_VER(i915) == 9 && !gen9_check_dword_gap(i915, guc_wopcm_base,  in check_hw_restrictions()
161 			   u32 guc_wopcm_base, u32 guc_wopcm_size,  in __check_layout()  argument
168 	if (unlikely(range_overflows(guc_wopcm_base, guc_wopcm_size, size))) {  in __check_layout()
171 			guc_wopcm_base / SZ_1K, guc_wopcm_size / SZ_1K,  in __check_layout()
185 	if (unlikely(guc_wopcm_base < size)) {  in __check_layout()
188 			guc_wopcm_base / SZ_1K, size / SZ_1K);  in __check_layout()
192 	return check_hw_restrictions(i915, guc_wopcm_base, guc_wopcm_size,  in __check_layout()
197 				u32 *guc_wopcm_base, u32 *guc_wopcm_size)  in __wopcm_regs_locked()  argument
206 	*guc_wopcm_base = reg_base & GUC_WOPCM_OFFSET_MASK;  in __wopcm_regs_locked()
237 	u32 guc_wopcm_base;  in intel_wopcm_init()  local
253 	if (__wopcm_regs_locked(gt->uncore, &guc_wopcm_base, &guc_wopcm_size)) {  in intel_wopcm_init()
255 			guc_wopcm_base / SZ_1K, guc_wopcm_size / SZ_1K);  in intel_wopcm_init()
281 	guc_wopcm_base = huc_fw_size + WOPCM_RESERVED_SIZE;  in intel_wopcm_init()
282 	guc_wopcm_base = ALIGN(guc_wopcm_base, GUC_WOPCM_OFFSET_ALIGNMENT);  in intel_wopcm_init()
288 	guc_wopcm_base = min(guc_wopcm_base, wopcm_size - ctx_rsvd);  in intel_wopcm_init()
291 	guc_wopcm_size = wopcm_size - ctx_rsvd - guc_wopcm_base;  in intel_wopcm_init()
295 		guc_wopcm_base / SZ_1K, guc_wopcm_size / SZ_1K);  in intel_wopcm_init()
298 	if (__check_layout(i915, wopcm_size, guc_wopcm_base, guc_wopcm_size,  in intel_wopcm_init()
300 		wopcm->guc.base = guc_wopcm_base;  in intel_wopcm_init()