Lines Matching refs:wm
433 mutex_lock(&dev_priv->display.wm.wm_mutex); in intel_set_memory_cxsr()
436 dev_priv->display.wm.vlv.cxsr = enable; in intel_set_memory_cxsr()
438 dev_priv->display.wm.g4x.cxsr = enable; in intel_set_memory_cxsr()
439 mutex_unlock(&dev_priv->display.wm.wm_mutex); in intel_set_memory_cxsr()
467 struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state; in vlv_get_fifo_size()
747 const struct intel_watermark_params *wm, in intel_calculate_wm() argument
761 entries = DIV_ROUND_UP(entries, wm->cacheline_size) + in intel_calculate_wm()
762 wm->guard_size; in intel_calculate_wm()
769 if (wm_size > wm->max_wm) in intel_calculate_wm()
770 wm_size = wm->max_wm; in intel_calculate_wm()
772 wm_size = wm->default_wm; in intel_calculate_wm()
799 return dev_priv->display.wm.max_level + 1; in intel_wm_num_levels()
864 unsigned int wm; in pnv_update_wm() local
885 wm = intel_calculate_wm(pixel_rate, &pnv_display_wm, in pnv_update_wm()
890 reg |= FW_WM(wm, SR); in pnv_update_wm()
895 wm = intel_calculate_wm(pixel_rate, &pnv_cursor_wm, in pnv_update_wm()
900 reg |= FW_WM(wm, CURSOR_SR); in pnv_update_wm()
904 wm = intel_calculate_wm(pixel_rate, &pnv_display_hplloff_wm, in pnv_update_wm()
909 reg |= FW_WM(wm, HPLL_SR); in pnv_update_wm()
913 wm = intel_calculate_wm(pixel_rate, &pnv_cursor_hplloff_wm, in pnv_update_wm()
918 reg |= FW_WM(wm, HPLL_CURSOR); in pnv_update_wm()
946 const struct g4x_wm_values *wm) in g4x_write_wm_values() argument
951 trace_g4x_wm(intel_crtc_for_pipe(dev_priv, pipe), wm); in g4x_write_wm_values()
954 FW_WM(wm->sr.plane, SR) | in g4x_write_wm_values()
955 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) | in g4x_write_wm_values()
956 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) | in g4x_write_wm_values()
957 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA)); in g4x_write_wm_values()
959 (wm->fbc_en ? DSPFW_FBC_SR_EN : 0) | in g4x_write_wm_values()
960 FW_WM(wm->sr.fbc, FBC_SR) | in g4x_write_wm_values()
961 FW_WM(wm->hpll.fbc, FBC_HPLL_SR) | in g4x_write_wm_values()
962 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) | in g4x_write_wm_values()
963 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) | in g4x_write_wm_values()
964 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA)); in g4x_write_wm_values()
966 (wm->hpll_en ? DSPFW_HPLL_SR_EN : 0) | in g4x_write_wm_values()
967 FW_WM(wm->sr.cursor, CURSOR_SR) | in g4x_write_wm_values()
968 FW_WM(wm->hpll.cursor, HPLL_CURSOR) | in g4x_write_wm_values()
969 FW_WM(wm->hpll.plane, HPLL_SR)); in g4x_write_wm_values()
978 const struct vlv_wm_values *wm) in vlv_write_wm_values() argument
983 trace_vlv_wm(intel_crtc_for_pipe(dev_priv, pipe), wm); in vlv_write_wm_values()
986 (wm->ddl[pipe].plane[PLANE_CURSOR] << DDL_CURSOR_SHIFT) | in vlv_write_wm_values()
987 (wm->ddl[pipe].plane[PLANE_SPRITE1] << DDL_SPRITE_SHIFT(1)) | in vlv_write_wm_values()
988 (wm->ddl[pipe].plane[PLANE_SPRITE0] << DDL_SPRITE_SHIFT(0)) | in vlv_write_wm_values()
989 (wm->ddl[pipe].plane[PLANE_PRIMARY] << DDL_PLANE_SHIFT)); in vlv_write_wm_values()
1004 FW_WM(wm->sr.plane, SR) | in vlv_write_wm_values()
1005 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) | in vlv_write_wm_values()
1006 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) | in vlv_write_wm_values()
1007 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA)); in vlv_write_wm_values()
1009 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) | in vlv_write_wm_values()
1010 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) | in vlv_write_wm_values()
1011 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA)); in vlv_write_wm_values()
1013 FW_WM(wm->sr.cursor, CURSOR_SR)); in vlv_write_wm_values()
1017 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) | in vlv_write_wm_values()
1018 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC)); in vlv_write_wm_values()
1020 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) | in vlv_write_wm_values()
1021 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE)); in vlv_write_wm_values()
1023 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) | in vlv_write_wm_values()
1024 FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC)); in vlv_write_wm_values()
1026 FW_WM(wm->sr.plane >> 9, SR_HI) | in vlv_write_wm_values()
1027 FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) | in vlv_write_wm_values()
1028 FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) | in vlv_write_wm_values()
1029 FW_WM(wm->pipe[PIPE_C].plane[PLANE_PRIMARY] >> 8, PLANEC_HI) | in vlv_write_wm_values()
1030 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) | in vlv_write_wm_values()
1031 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) | in vlv_write_wm_values()
1032 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) | in vlv_write_wm_values()
1033 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) | in vlv_write_wm_values()
1034 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) | in vlv_write_wm_values()
1035 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI)); in vlv_write_wm_values()
1038 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) | in vlv_write_wm_values()
1039 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC)); in vlv_write_wm_values()
1041 FW_WM(wm->sr.plane >> 9, SR_HI) | in vlv_write_wm_values()
1042 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) | in vlv_write_wm_values()
1043 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) | in vlv_write_wm_values()
1044 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) | in vlv_write_wm_values()
1045 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) | in vlv_write_wm_values()
1046 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) | in vlv_write_wm_values()
1047 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI)); in vlv_write_wm_values()
1058 dev_priv->display.wm.pri_latency[G4X_WM_LEVEL_NORMAL] = 5; in g4x_setup_wm_latency()
1059 dev_priv->display.wm.pri_latency[G4X_WM_LEVEL_SR] = 12; in g4x_setup_wm_latency()
1060 dev_priv->display.wm.pri_latency[G4X_WM_LEVEL_HPLL] = 35; in g4x_setup_wm_latency()
1062 dev_priv->display.wm.max_level = G4X_WM_LEVEL_HPLL; in g4x_setup_wm_latency()
1115 unsigned int latency = dev_priv->display.wm.pri_latency[level] * 10; in g4x_compute_wm()
1116 unsigned int pixel_rate, htotal, cpp, width, wm; in g4x_compute_wm() local
1142 wm = intel_wm_method2(pixel_rate, htotal, width, cpp, latency); in g4x_compute_wm()
1145 wm = intel_wm_method1(pixel_rate, cpp, latency); in g4x_compute_wm()
1152 wm = min(small, large); in g4x_compute_wm()
1155 wm += g4x_tlb_miss_wa(g4x_plane_fifo_size(plane->id, level), in g4x_compute_wm()
1158 wm = DIV_ROUND_UP(wm, 64) + 2; in g4x_compute_wm()
1160 return min_t(unsigned int, wm, USHRT_MAX); in g4x_compute_wm()
1170 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level]; in g4x_raw_plane_wm_set()
1189 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level]; in g4x_raw_fbc_wm_set()
1220 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level]; in g4x_raw_plane_wm_compute()
1221 int wm, max_wm; in g4x_raw_plane_wm_compute() local
1223 wm = g4x_compute_wm(crtc_state, plane_state, level); in g4x_raw_plane_wm_compute()
1226 if (wm > max_wm) in g4x_raw_plane_wm_compute()
1229 dirty |= raw->plane[plane_id] != wm; in g4x_raw_plane_wm_compute()
1230 raw->plane[plane_id] = wm; in g4x_raw_plane_wm_compute()
1236 wm = ilk_compute_fbc_wm(crtc_state, plane_state, in g4x_raw_plane_wm_compute()
1244 if (wm > max_wm) in g4x_raw_plane_wm_compute()
1245 wm = USHRT_MAX; in g4x_raw_plane_wm_compute()
1247 dirty |= raw->fbc != wm; in g4x_raw_plane_wm_compute()
1248 raw->fbc = wm; in g4x_raw_plane_wm_compute()
1262 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_NORMAL].plane[plane_id], in g4x_raw_plane_wm_compute()
1263 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].plane[plane_id], in g4x_raw_plane_wm_compute()
1264 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]); in g4x_raw_plane_wm_compute()
1269 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].fbc, in g4x_raw_plane_wm_compute()
1270 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].fbc); in g4x_raw_plane_wm_compute()
1279 const struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level]; in g4x_raw_plane_wm_is_valid()
1289 if (level > dev_priv->display.wm.max_level) in g4x_raw_crtc_wm_is_valid()
1305 wm_state->wm.plane[plane_id] = USHRT_MAX; in g4x_invalidate_wms()
1345 struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal; in g4x_compute_pipe_wm()
1373 raw = &crtc_state->wm.g4x.raw[level]; in g4x_compute_pipe_wm()
1375 wm_state->wm.plane[plane_id] = raw->plane[plane_id]; in g4x_compute_pipe_wm()
1381 raw = &crtc_state->wm.g4x.raw[level]; in g4x_compute_pipe_wm()
1392 raw = &crtc_state->wm.g4x.raw[level]; in g4x_compute_pipe_wm()
1428 struct g4x_wm_state *intermediate = &new_crtc_state->wm.g4x.intermediate; in g4x_compute_intermediate_wm()
1429 const struct g4x_wm_state *optimal = &new_crtc_state->wm.g4x.optimal; in g4x_compute_intermediate_wm()
1430 const struct g4x_wm_state *active = &old_crtc_state->wm.g4x.optimal; in g4x_compute_intermediate_wm()
1449 intermediate->wm.plane[plane_id] = in g4x_compute_intermediate_wm()
1450 max(optimal->wm.plane[plane_id], in g4x_compute_intermediate_wm()
1451 active->wm.plane[plane_id]); in g4x_compute_intermediate_wm()
1453 drm_WARN_ON(&dev_priv->drm, intermediate->wm.plane[plane_id] > in g4x_compute_intermediate_wm()
1497 new_crtc_state->wm.need_postvbl_update = true; in g4x_compute_intermediate_wm()
1503 struct g4x_wm_values *wm) in g4x_merge_wm() argument
1508 wm->cxsr = true; in g4x_merge_wm()
1509 wm->hpll_en = true; in g4x_merge_wm()
1510 wm->fbc_en = true; in g4x_merge_wm()
1513 const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x; in g4x_merge_wm()
1519 wm->cxsr = false; in g4x_merge_wm()
1521 wm->hpll_en = false; in g4x_merge_wm()
1523 wm->fbc_en = false; in g4x_merge_wm()
1529 wm->cxsr = false; in g4x_merge_wm()
1530 wm->hpll_en = false; in g4x_merge_wm()
1531 wm->fbc_en = false; in g4x_merge_wm()
1535 const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x; in g4x_merge_wm()
1538 wm->pipe[pipe] = wm_state->wm; in g4x_merge_wm()
1539 if (crtc->active && wm->cxsr) in g4x_merge_wm()
1540 wm->sr = wm_state->sr; in g4x_merge_wm()
1541 if (crtc->active && wm->hpll_en) in g4x_merge_wm()
1542 wm->hpll = wm_state->hpll; in g4x_merge_wm()
1548 struct g4x_wm_values *old_wm = &dev_priv->display.wm.g4x; in g4x_program_watermarks()
1574 mutex_lock(&dev_priv->display.wm.wm_mutex); in g4x_initial_watermarks()
1575 crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate; in g4x_initial_watermarks()
1577 mutex_unlock(&dev_priv->display.wm.wm_mutex); in g4x_initial_watermarks()
1587 if (!crtc_state->wm.need_postvbl_update) in g4x_optimize_watermarks()
1590 mutex_lock(&dev_priv->display.wm.wm_mutex); in g4x_optimize_watermarks()
1591 crtc->wm.active.g4x = crtc_state->wm.g4x.optimal; in g4x_optimize_watermarks()
1593 mutex_unlock(&dev_priv->display.wm.wm_mutex); in g4x_optimize_watermarks()
1615 dev_priv->display.wm.pri_latency[VLV_WM_LEVEL_PM2] = 3; in vlv_setup_wm_latency()
1617 dev_priv->display.wm.max_level = VLV_WM_LEVEL_PM2; in vlv_setup_wm_latency()
1620 dev_priv->display.wm.pri_latency[VLV_WM_LEVEL_PM5] = 12; in vlv_setup_wm_latency()
1621 dev_priv->display.wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33; in vlv_setup_wm_latency()
1623 dev_priv->display.wm.max_level = VLV_WM_LEVEL_DDR_DVFS; in vlv_setup_wm_latency()
1635 unsigned int pixel_rate, htotal, cpp, width, wm; in vlv_compute_wm_level() local
1637 if (dev_priv->display.wm.pri_latency[level] == 0) in vlv_compute_wm_level()
1655 wm = 63; in vlv_compute_wm_level()
1657 wm = vlv_wm_method2(pixel_rate, htotal, width, cpp, in vlv_compute_wm_level()
1658 dev_priv->display.wm.pri_latency[level] * 10); in vlv_compute_wm_level()
1661 return min_t(unsigned int, wm, USHRT_MAX); in vlv_compute_wm_level()
1675 &crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2]; in vlv_compute_fifo()
1676 struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state; in vlv_compute_fifo()
1763 wm_state->wm[level].plane[plane_id] = USHRT_MAX; in vlv_invalidate_wms()
1770 static u16 vlv_invert_wm_value(u16 wm, u16 fifo_size) in vlv_invert_wm_value() argument
1772 if (wm > fifo_size) in vlv_invert_wm_value()
1775 return fifo_size - wm; in vlv_invert_wm_value()
1790 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level]; in vlv_raw_plane_wm_set()
1815 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level]; in vlv_raw_plane_wm_compute()
1816 int wm = vlv_compute_wm_level(crtc_state, plane_state, level); in vlv_raw_plane_wm_compute() local
1819 if (wm > max_wm) in vlv_raw_plane_wm_compute()
1822 dirty |= raw->plane[plane_id] != wm; in vlv_raw_plane_wm_compute()
1823 raw->plane[plane_id] = wm; in vlv_raw_plane_wm_compute()
1834 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id], in vlv_raw_plane_wm_compute()
1835 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id], in vlv_raw_plane_wm_compute()
1836 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id]); in vlv_raw_plane_wm_compute()
1845 &crtc_state->wm.vlv.raw[level]; in vlv_raw_plane_wm_is_valid()
1847 &crtc_state->wm.vlv.fifo_state; in vlv_raw_plane_wm_is_valid()
1866 struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal; in vlv_compute_pipe_wm()
1868 &crtc_state->wm.vlv.fifo_state; in vlv_compute_pipe_wm()
1907 &old_crtc_state->wm.vlv.fifo_state; in vlv_compute_pipe_wm()
1929 const struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level]; in vlv_compute_pipe_wm()
1936 wm_state->wm[level].plane[plane_id] = in vlv_compute_pipe_wm()
1975 &crtc_state->wm.vlv.fifo_state; in vlv_atomic_update_fifo()
2072 struct vlv_wm_state *intermediate = &new_crtc_state->wm.vlv.intermediate; in vlv_compute_intermediate_wm()
2073 const struct vlv_wm_state *optimal = &new_crtc_state->wm.vlv.optimal; in vlv_compute_intermediate_wm()
2074 const struct vlv_wm_state *active = &old_crtc_state->wm.vlv.optimal; in vlv_compute_intermediate_wm()
2093 intermediate->wm[level].plane[plane_id] = in vlv_compute_intermediate_wm()
2094 min(optimal->wm[level].plane[plane_id], in vlv_compute_intermediate_wm()
2095 active->wm[level].plane[plane_id]); in vlv_compute_intermediate_wm()
2112 new_crtc_state->wm.need_postvbl_update = true; in vlv_compute_intermediate_wm()
2118 struct vlv_wm_values *wm) in vlv_merge_wm() argument
2123 wm->level = dev_priv->display.wm.max_level; in vlv_merge_wm()
2124 wm->cxsr = true; in vlv_merge_wm()
2127 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv; in vlv_merge_wm()
2133 wm->cxsr = false; in vlv_merge_wm()
2136 wm->level = min_t(int, wm->level, wm_state->num_levels - 1); in vlv_merge_wm()
2140 wm->cxsr = false; in vlv_merge_wm()
2143 wm->level = VLV_WM_LEVEL_PM2; in vlv_merge_wm()
2146 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv; in vlv_merge_wm()
2149 wm->pipe[pipe] = wm_state->wm[wm->level]; in vlv_merge_wm()
2150 if (crtc->active && wm->cxsr) in vlv_merge_wm()
2151 wm->sr = wm_state->sr[wm->level]; in vlv_merge_wm()
2153 wm->ddl[pipe].plane[PLANE_PRIMARY] = DDL_PRECISION_HIGH | 2; in vlv_merge_wm()
2154 wm->ddl[pipe].plane[PLANE_SPRITE0] = DDL_PRECISION_HIGH | 2; in vlv_merge_wm()
2155 wm->ddl[pipe].plane[PLANE_SPRITE1] = DDL_PRECISION_HIGH | 2; in vlv_merge_wm()
2156 wm->ddl[pipe].plane[PLANE_CURSOR] = DDL_PRECISION_HIGH | 2; in vlv_merge_wm()
2162 struct vlv_wm_values *old_wm = &dev_priv->display.wm.vlv; in vlv_program_watermarks()
2200 mutex_lock(&dev_priv->display.wm.wm_mutex); in vlv_initial_watermarks()
2201 crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate; in vlv_initial_watermarks()
2203 mutex_unlock(&dev_priv->display.wm.wm_mutex); in vlv_initial_watermarks()
2213 if (!crtc_state->wm.need_postvbl_update) in vlv_optimize_watermarks()
2216 mutex_lock(&dev_priv->display.wm.wm_mutex); in vlv_optimize_watermarks()
2217 crtc->wm.active.vlv = crtc_state->wm.vlv.optimal; in vlv_optimize_watermarks()
2219 mutex_unlock(&dev_priv->display.wm.wm_mutex); in vlv_optimize_watermarks()
2800 u16 pri_latency = dev_priv->display.wm.pri_latency[level]; in ilk_compute_wm_level()
2801 u16 spr_latency = dev_priv->display.wm.spr_latency[level]; in ilk_compute_wm_level()
2802 u16 cur_latency = dev_priv->display.wm.cur_latency[level]; in ilk_compute_wm_level()
2826 static void hsw_read_wm_latency(struct drm_i915_private *i915, u16 wm[]) in hsw_read_wm_latency() argument
2832 wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd); in hsw_read_wm_latency()
2833 if (wm[0] == 0) in hsw_read_wm_latency()
2834 wm[0] = REG_FIELD_GET64(SSKPD_OLD_WM0_MASK_HSW, sskpd); in hsw_read_wm_latency()
2835 wm[1] = REG_FIELD_GET64(SSKPD_WM1_MASK_HSW, sskpd); in hsw_read_wm_latency()
2836 wm[2] = REG_FIELD_GET64(SSKPD_WM2_MASK_HSW, sskpd); in hsw_read_wm_latency()
2837 wm[3] = REG_FIELD_GET64(SSKPD_WM3_MASK_HSW, sskpd); in hsw_read_wm_latency()
2838 wm[4] = REG_FIELD_GET64(SSKPD_WM4_MASK_HSW, sskpd); in hsw_read_wm_latency()
2841 static void snb_read_wm_latency(struct drm_i915_private *i915, u16 wm[]) in snb_read_wm_latency() argument
2847 wm[0] = REG_FIELD_GET(SSKPD_WM0_MASK_SNB, sskpd); in snb_read_wm_latency()
2848 wm[1] = REG_FIELD_GET(SSKPD_WM1_MASK_SNB, sskpd); in snb_read_wm_latency()
2849 wm[2] = REG_FIELD_GET(SSKPD_WM2_MASK_SNB, sskpd); in snb_read_wm_latency()
2850 wm[3] = REG_FIELD_GET(SSKPD_WM3_MASK_SNB, sskpd); in snb_read_wm_latency()
2853 static void ilk_read_wm_latency(struct drm_i915_private *i915, u16 wm[]) in ilk_read_wm_latency() argument
2860 wm[0] = 7; in ilk_read_wm_latency()
2861 wm[1] = REG_FIELD_GET(MLTR_WM1_MASK, mltr); in ilk_read_wm_latency()
2862 wm[2] = REG_FIELD_GET(MLTR_WM2_MASK, mltr); in ilk_read_wm_latency()
2866 u16 wm[5]) in intel_fixup_spr_wm_latency()
2870 wm[0] = 13; in intel_fixup_spr_wm_latency()
2874 u16 wm[5]) in intel_fixup_cur_wm_latency()
2878 wm[0] = 13; in intel_fixup_cur_wm_latency()
2897 const char *name, const u16 wm[]) in intel_print_wm_latency() argument
2902 unsigned int latency = wm[level]; in intel_print_wm_latency()
2922 wm[level], latency / 10, latency % 10); in intel_print_wm_latency()
2927 u16 wm[5], u16 min) in ilk_increase_wm_latency()
2931 if (wm[0] >= min) in ilk_increase_wm_latency()
2934 wm[0] = max(wm[0], min); in ilk_increase_wm_latency()
2936 wm[level] = max_t(u16, wm[level], DIV_ROUND_UP(min, 5)); in ilk_increase_wm_latency()
2949 changed = ilk_increase_wm_latency(dev_priv, dev_priv->display.wm.pri_latency, 12); in snb_wm_latency_quirk()
2950 changed |= ilk_increase_wm_latency(dev_priv, dev_priv->display.wm.spr_latency, 12); in snb_wm_latency_quirk()
2951 changed |= ilk_increase_wm_latency(dev_priv, dev_priv->display.wm.cur_latency, 12); in snb_wm_latency_quirk()
2958 intel_print_wm_latency(dev_priv, "Primary", dev_priv->display.wm.pri_latency); in snb_wm_latency_quirk()
2959 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->display.wm.spr_latency); in snb_wm_latency_quirk()
2960 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->display.wm.cur_latency); in snb_wm_latency_quirk()
2976 if (dev_priv->display.wm.pri_latency[3] == 0 && in snb_wm_lp3_irq_quirk()
2977 dev_priv->display.wm.spr_latency[3] == 0 && in snb_wm_lp3_irq_quirk()
2978 dev_priv->display.wm.cur_latency[3] == 0) in snb_wm_lp3_irq_quirk()
2981 dev_priv->display.wm.pri_latency[3] = 0; in snb_wm_lp3_irq_quirk()
2982 dev_priv->display.wm.spr_latency[3] = 0; in snb_wm_lp3_irq_quirk()
2983 dev_priv->display.wm.cur_latency[3] = 0; in snb_wm_lp3_irq_quirk()
2987 intel_print_wm_latency(dev_priv, "Primary", dev_priv->display.wm.pri_latency); in snb_wm_lp3_irq_quirk()
2988 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->display.wm.spr_latency); in snb_wm_lp3_irq_quirk()
2989 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->display.wm.cur_latency); in snb_wm_lp3_irq_quirk()
2995 hsw_read_wm_latency(dev_priv, dev_priv->display.wm.pri_latency); in ilk_setup_wm_latency()
2997 snb_read_wm_latency(dev_priv, dev_priv->display.wm.pri_latency); in ilk_setup_wm_latency()
2999 ilk_read_wm_latency(dev_priv, dev_priv->display.wm.pri_latency); in ilk_setup_wm_latency()
3001 memcpy(dev_priv->display.wm.spr_latency, dev_priv->display.wm.pri_latency, in ilk_setup_wm_latency()
3002 sizeof(dev_priv->display.wm.pri_latency)); in ilk_setup_wm_latency()
3003 memcpy(dev_priv->display.wm.cur_latency, dev_priv->display.wm.pri_latency, in ilk_setup_wm_latency()
3004 sizeof(dev_priv->display.wm.pri_latency)); in ilk_setup_wm_latency()
3006 intel_fixup_spr_wm_latency(dev_priv, dev_priv->display.wm.spr_latency); in ilk_setup_wm_latency()
3007 intel_fixup_cur_wm_latency(dev_priv, dev_priv->display.wm.cur_latency); in ilk_setup_wm_latency()
3009 intel_print_wm_latency(dev_priv, "Primary", dev_priv->display.wm.pri_latency); in ilk_setup_wm_latency()
3010 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->display.wm.spr_latency); in ilk_setup_wm_latency()
3011 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->display.wm.cur_latency); in ilk_setup_wm_latency()
3034 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) { in ilk_validate_pipe_wm()
3058 pipe_wm = &crtc_state->wm.ilk.optimal; in ilk_compute_pipe_wm()
3083 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm)); in ilk_compute_pipe_wm()
3085 pristate, sprstate, curstate, &pipe_wm->wm[0]); in ilk_compute_pipe_wm()
3093 struct intel_wm_level *wm = &pipe_wm->wm[level]; in ilk_compute_pipe_wm() local
3096 pristate, sprstate, curstate, wm); in ilk_compute_pipe_wm()
3103 if (!ilk_validate_wm_level(level, &max, wm)) { in ilk_compute_pipe_wm()
3104 memset(wm, 0, sizeof(*wm)); in ilk_compute_pipe_wm()
3125 struct intel_pipe_wm *a = &new_crtc_state->wm.ilk.intermediate; in ilk_compute_intermediate_wm()
3126 const struct intel_pipe_wm *b = &old_crtc_state->wm.ilk.optimal; in ilk_compute_intermediate_wm()
3134 *a = new_crtc_state->wm.ilk.optimal; in ilk_compute_intermediate_wm()
3145 struct intel_wm_level *a_wm = &a->wm[level]; in ilk_compute_intermediate_wm()
3146 const struct intel_wm_level *b_wm = &b->wm[level]; in ilk_compute_intermediate_wm()
3168 if (memcmp(a, &new_crtc_state->wm.ilk.optimal, sizeof(*a)) != 0) in ilk_compute_intermediate_wm()
3169 new_crtc_state->wm.need_postvbl_update = true; in ilk_compute_intermediate_wm()
3186 const struct intel_pipe_wm *active = &crtc->wm.active.ilk; in ilk_merge_wm_level()
3187 const struct intel_wm_level *wm = &active->wm[level]; in ilk_merge_wm_level() local
3197 if (!wm->enable) in ilk_merge_wm_level()
3200 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val); in ilk_merge_wm_level()
3201 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val); in ilk_merge_wm_level()
3202 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val); in ilk_merge_wm_level()
3203 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val); in ilk_merge_wm_level()
3228 struct intel_wm_level *wm = &merged->wm[level]; in ilk_wm_merge() local
3230 ilk_merge_wm_level(dev_priv, level, wm); in ilk_wm_merge()
3233 wm->enable = false; in ilk_wm_merge()
3234 else if (!ilk_validate_wm_level(level, max, wm)) in ilk_wm_merge()
3242 if (wm->fbc_val > max->fbc) { in ilk_wm_merge()
3243 if (wm->enable) in ilk_wm_merge()
3245 wm->fbc_val = 0; in ilk_wm_merge()
3253 struct intel_wm_level *wm = &merged->wm[level]; in ilk_wm_merge() local
3255 wm->enable = false; in ilk_wm_merge()
3263 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable); in ilk_wm_lp_to_level()
3273 return dev_priv->display.wm.pri_latency[level]; in ilk_wm_lp_latency()
3293 r = &merged->wm[level]; in ilk_compute_wm_results()
3327 const struct intel_pipe_wm *pipe_wm = &crtc->wm.active.ilk; in ilk_compute_wm_results()
3328 const struct intel_wm_level *r = &pipe_wm->wm[0]; in ilk_compute_wm_results()
3351 if (r1->wm[level].enable) in ilk_find_best_result()
3353 if (r2->wm[level].enable) in ilk_find_best_result()
3425 struct ilk_wm_values *previous = &dev_priv->display.wm.hw; in _ilk_disable_lp_wm()
3459 struct ilk_wm_values *previous = &dev_priv->display.wm.hw; in ilk_write_wm_values()
3521 dev_priv->display.wm.hw = *results; in ilk_write_wm_values()
3536 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk; in ilk_compute_wm_config() local
3538 if (!wm->pipe_enabled) in ilk_compute_wm_config()
3541 config->sprites_enabled |= wm->sprites_enabled; in ilk_compute_wm_config()
3542 config->sprites_scaled |= wm->sprites_scaled; in ilk_compute_wm_config()
3586 mutex_lock(&dev_priv->display.wm.wm_mutex); in ilk_initial_watermarks()
3587 crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate; in ilk_initial_watermarks()
3589 mutex_unlock(&dev_priv->display.wm.wm_mutex); in ilk_initial_watermarks()
3599 if (!crtc_state->wm.need_postvbl_update) in ilk_optimize_watermarks()
3602 mutex_lock(&dev_priv->display.wm.wm_mutex); in ilk_optimize_watermarks()
3603 crtc->wm.active.ilk = crtc_state->wm.ilk.optimal; in ilk_optimize_watermarks()
3605 mutex_unlock(&dev_priv->display.wm.wm_mutex); in ilk_optimize_watermarks()
3612 struct ilk_wm_values *hw = &dev_priv->display.wm.hw; in ilk_pipe_wm_get_hw_state()
3614 struct intel_pipe_wm *active = &crtc_state->wm.ilk.optimal; in ilk_pipe_wm_get_hw_state()
3632 active->wm[0].enable = true; in ilk_pipe_wm_get_hw_state()
3633 active->wm[0].pri_val = REG_FIELD_GET(WM0_PIPE_PRIMARY_MASK, tmp); in ilk_pipe_wm_get_hw_state()
3634 active->wm[0].spr_val = REG_FIELD_GET(WM0_PIPE_SPRITE_MASK, tmp); in ilk_pipe_wm_get_hw_state()
3635 active->wm[0].cur_val = REG_FIELD_GET(WM0_PIPE_CURSOR_MASK, tmp); in ilk_pipe_wm_get_hw_state()
3645 active->wm[level].enable = true; in ilk_pipe_wm_get_hw_state()
3648 crtc->wm.active.ilk = *active; in ilk_pipe_wm_get_hw_state()
3657 struct g4x_wm_values *wm) in g4x_read_wm_values() argument
3662 wm->sr.plane = _FW_WM(tmp, SR); in g4x_read_wm_values()
3663 wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB); in g4x_read_wm_values()
3664 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB); in g4x_read_wm_values()
3665 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEA); in g4x_read_wm_values()
3668 wm->fbc_en = tmp & DSPFW_FBC_SR_EN; in g4x_read_wm_values()
3669 wm->sr.fbc = _FW_WM(tmp, FBC_SR); in g4x_read_wm_values()
3670 wm->hpll.fbc = _FW_WM(tmp, FBC_HPLL_SR); in g4x_read_wm_values()
3671 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEB); in g4x_read_wm_values()
3672 wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA); in g4x_read_wm_values()
3673 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEA); in g4x_read_wm_values()
3676 wm->hpll_en = tmp & DSPFW_HPLL_SR_EN; in g4x_read_wm_values()
3677 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR); in g4x_read_wm_values()
3678 wm->hpll.cursor = _FW_WM(tmp, HPLL_CURSOR); in g4x_read_wm_values()
3679 wm->hpll.plane = _FW_WM(tmp, HPLL_SR); in g4x_read_wm_values()
3683 struct vlv_wm_values *wm) in vlv_read_wm_values() argument
3691 wm->ddl[pipe].plane[PLANE_PRIMARY] = in vlv_read_wm_values()
3693 wm->ddl[pipe].plane[PLANE_CURSOR] = in vlv_read_wm_values()
3695 wm->ddl[pipe].plane[PLANE_SPRITE0] = in vlv_read_wm_values()
3697 wm->ddl[pipe].plane[PLANE_SPRITE1] = in vlv_read_wm_values()
3702 wm->sr.plane = _FW_WM(tmp, SR); in vlv_read_wm_values()
3703 wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB); in vlv_read_wm_values()
3704 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB); in vlv_read_wm_values()
3705 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA); in vlv_read_wm_values()
3708 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB); in vlv_read_wm_values()
3709 wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA); in vlv_read_wm_values()
3710 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA); in vlv_read_wm_values()
3713 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR); in vlv_read_wm_values()
3717 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED); in vlv_read_wm_values()
3718 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC); in vlv_read_wm_values()
3721 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEF); in vlv_read_wm_values()
3722 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEE); in vlv_read_wm_values()
3725 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEC); in vlv_read_wm_values()
3726 wm->pipe[PIPE_C].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORC); in vlv_read_wm_values()
3729 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9; in vlv_read_wm_values()
3730 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEF_HI) << 8; in vlv_read_wm_values()
3731 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEE_HI) << 8; in vlv_read_wm_values()
3732 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEC_HI) << 8; in vlv_read_wm_values()
3733 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8; in vlv_read_wm_values()
3734 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8; in vlv_read_wm_values()
3735 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8; in vlv_read_wm_values()
3736 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8; in vlv_read_wm_values()
3737 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8; in vlv_read_wm_values()
3738 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8; in vlv_read_wm_values()
3741 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED); in vlv_read_wm_values()
3742 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC); in vlv_read_wm_values()
3745 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9; in vlv_read_wm_values()
3746 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8; in vlv_read_wm_values()
3747 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8; in vlv_read_wm_values()
3748 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8; in vlv_read_wm_values()
3749 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8; in vlv_read_wm_values()
3750 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8; in vlv_read_wm_values()
3751 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8; in vlv_read_wm_values()
3760 struct g4x_wm_values *wm = &dev_priv->display.wm.g4x; in g4x_wm_get_hw_state() local
3763 g4x_read_wm_values(dev_priv, wm); in g4x_wm_get_hw_state()
3765 wm->cxsr = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN; in g4x_wm_get_hw_state()
3770 struct g4x_wm_state *active = &crtc->wm.active.g4x; in g4x_wm_get_hw_state()
3776 active->cxsr = wm->cxsr; in g4x_wm_get_hw_state()
3777 active->hpll_en = wm->hpll_en; in g4x_wm_get_hw_state()
3778 active->fbc_en = wm->fbc_en; in g4x_wm_get_hw_state()
3780 active->sr = wm->sr; in g4x_wm_get_hw_state()
3781 active->hpll = wm->hpll; in g4x_wm_get_hw_state()
3784 active->wm.plane[plane_id] = in g4x_wm_get_hw_state()
3785 wm->pipe[pipe].plane[plane_id]; in g4x_wm_get_hw_state()
3788 if (wm->cxsr && wm->hpll_en) in g4x_wm_get_hw_state()
3790 else if (wm->cxsr) in g4x_wm_get_hw_state()
3796 raw = &crtc_state->wm.g4x.raw[level]; in g4x_wm_get_hw_state()
3798 raw->plane[plane_id] = active->wm.plane[plane_id]; in g4x_wm_get_hw_state()
3804 raw = &crtc_state->wm.g4x.raw[level]; in g4x_wm_get_hw_state()
3814 raw = &crtc_state->wm.g4x.raw[level]; in g4x_wm_get_hw_state()
3827 crtc_state->wm.g4x.optimal = *active; in g4x_wm_get_hw_state()
3828 crtc_state->wm.g4x.intermediate = *active; in g4x_wm_get_hw_state()
3833 wm->pipe[pipe].plane[PLANE_PRIMARY], in g4x_wm_get_hw_state()
3834 wm->pipe[pipe].plane[PLANE_CURSOR], in g4x_wm_get_hw_state()
3835 wm->pipe[pipe].plane[PLANE_SPRITE0]); in g4x_wm_get_hw_state()
3840 wm->sr.plane, wm->sr.cursor, wm->sr.fbc); in g4x_wm_get_hw_state()
3843 wm->hpll.plane, wm->hpll.cursor, wm->hpll.fbc); in g4x_wm_get_hw_state()
3845 str_yes_no(wm->cxsr), str_yes_no(wm->hpll_en), in g4x_wm_get_hw_state()
3846 str_yes_no(wm->fbc_en)); in g4x_wm_get_hw_state()
3854 mutex_lock(&dev_priv->display.wm.wm_mutex); in g4x_wm_sanitize()
3863 struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal; in g4x_wm_sanitize()
3872 &crtc_state->wm.g4x.raw[level]; in g4x_wm_sanitize()
3875 wm_state->wm.plane[plane_id] = 0; in g4x_wm_sanitize()
3881 &crtc_state->wm.g4x.raw[level]; in g4x_wm_sanitize()
3895 crtc_state->wm.g4x.intermediate = in g4x_wm_sanitize()
3896 crtc_state->wm.g4x.optimal; in g4x_wm_sanitize()
3897 crtc->wm.active.g4x = crtc_state->wm.g4x.optimal; in g4x_wm_sanitize()
3902 mutex_unlock(&dev_priv->display.wm.wm_mutex); in g4x_wm_sanitize()
3907 struct vlv_wm_values *wm = &dev_priv->display.wm.vlv; in vlv_wm_get_hw_state() local
3911 vlv_read_wm_values(dev_priv, wm); in vlv_wm_get_hw_state()
3913 wm->cxsr = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; in vlv_wm_get_hw_state()
3914 wm->level = VLV_WM_LEVEL_PM2; in vlv_wm_get_hw_state()
3921 wm->level = VLV_WM_LEVEL_PM5; in vlv_wm_get_hw_state()
3941 dev_priv->display.wm.max_level = VLV_WM_LEVEL_PM5; in vlv_wm_get_hw_state()
3945 wm->level = VLV_WM_LEVEL_DDR_DVFS; in vlv_wm_get_hw_state()
3954 struct vlv_wm_state *active = &crtc->wm.active.vlv; in vlv_wm_get_hw_state()
3956 &crtc_state->wm.vlv.fifo_state; in vlv_wm_get_hw_state()
3963 active->num_levels = wm->level + 1; in vlv_wm_get_hw_state()
3964 active->cxsr = wm->cxsr; in vlv_wm_get_hw_state()
3968 &crtc_state->wm.vlv.raw[level]; in vlv_wm_get_hw_state()
3970 active->sr[level].plane = wm->sr.plane; in vlv_wm_get_hw_state()
3971 active->sr[level].cursor = wm->sr.cursor; in vlv_wm_get_hw_state()
3974 active->wm[level].plane[plane_id] = in vlv_wm_get_hw_state()
3975 wm->pipe[pipe].plane[plane_id]; in vlv_wm_get_hw_state()
3978 vlv_invert_wm_value(active->wm[level].plane[plane_id], in vlv_wm_get_hw_state()
3988 crtc_state->wm.vlv.optimal = *active; in vlv_wm_get_hw_state()
3989 crtc_state->wm.vlv.intermediate = *active; in vlv_wm_get_hw_state()
3994 wm->pipe[pipe].plane[PLANE_PRIMARY], in vlv_wm_get_hw_state()
3995 wm->pipe[pipe].plane[PLANE_CURSOR], in vlv_wm_get_hw_state()
3996 wm->pipe[pipe].plane[PLANE_SPRITE0], in vlv_wm_get_hw_state()
3997 wm->pipe[pipe].plane[PLANE_SPRITE1]); in vlv_wm_get_hw_state()
4002 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr); in vlv_wm_get_hw_state()
4010 mutex_lock(&dev_priv->display.wm.wm_mutex); in vlv_wm_sanitize()
4019 struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal; in vlv_wm_sanitize()
4021 &crtc_state->wm.vlv.fifo_state; in vlv_wm_sanitize()
4030 &crtc_state->wm.vlv.raw[level]; in vlv_wm_sanitize()
4034 wm_state->wm[level].plane[plane_id] = in vlv_wm_sanitize()
4044 crtc_state->wm.vlv.intermediate = in vlv_wm_sanitize()
4045 crtc_state->wm.vlv.optimal; in vlv_wm_sanitize()
4046 crtc->wm.active.vlv = crtc_state->wm.vlv.optimal; in vlv_wm_sanitize()
4051 mutex_unlock(&dev_priv->display.wm.wm_mutex); in vlv_wm_sanitize()
4072 struct ilk_wm_values *hw = &dev_priv->display.wm.hw; in ilk_wm_get_hw_state()
4999 if ((DISPLAY_VER(dev_priv) == 5 && dev_priv->display.wm.pri_latency[1] && in intel_init_pm()
5000 dev_priv->display.wm.spr_latency[1] && dev_priv->display.wm.cur_latency[1]) || in intel_init_pm()
5001 (DISPLAY_VER(dev_priv) != 5 && dev_priv->display.wm.pri_latency[0] && in intel_init_pm()
5002 dev_priv->display.wm.spr_latency[0] && dev_priv->display.wm.cur_latency[0])) { in intel_init_pm()
5003 dev_priv->display.funcs.wm = &ilk_wm_funcs; in intel_init_pm()
5008 dev_priv->display.funcs.wm = &nop_funcs; in intel_init_pm()
5012 dev_priv->display.funcs.wm = &vlv_wm_funcs; in intel_init_pm()
5015 dev_priv->display.funcs.wm = &g4x_wm_funcs; in intel_init_pm()
5029 dev_priv->display.funcs.wm = &nop_funcs; in intel_init_pm()
5031 dev_priv->display.funcs.wm = &pnv_wm_funcs; in intel_init_pm()
5033 dev_priv->display.funcs.wm = &i965_wm_funcs; in intel_init_pm()
5035 dev_priv->display.funcs.wm = &i9xx_wm_funcs; in intel_init_pm()
5038 dev_priv->display.funcs.wm = &i845_wm_funcs; in intel_init_pm()
5040 dev_priv->display.funcs.wm = &i9xx_wm_funcs; in intel_init_pm()
5044 dev_priv->display.funcs.wm = &nop_funcs; in intel_init_pm()