Lines Matching refs:VLV_DISPLAY_BASE
226 #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100)
248 #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
249 #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
254 #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110)
1023 #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028)
1047 #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)
1048 #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)
1056 #define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060)
1059 #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064)
1060 #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084)
1061 #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0)
1062 #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4)
1063 #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8)
1064 #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac)
1065 #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)
1293 #define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000)
1297 #define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38)
1300 #define _VLV_AUD_PORT_EN_B_DBG (VLV_DISPLAY_BASE + 0x62F20)
1301 #define _VLV_AUD_PORT_EN_C_DBG (VLV_DISPLAY_BASE + 0x62F30)
1302 #define _VLV_AUD_PORT_EN_D_DBG (VLV_DISPLAY_BASE + 0x62F34)
1514 #define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240)
1516 #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
1527 #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
1612 #define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024)
1759 #define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500)
1762 #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)
1764 #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508)
1769 #define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C)
1776 #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510)
2419 #define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100)
2568 #define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140)
2569 #define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160)
2570 #define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C)
2778 #define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE)
3365 #define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100)
3366 #define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200)
3367 #define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300)
3761 #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028)
3782 #define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
3827 #define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
3840 #define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */
3885 #define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070)
3892 #define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074)
3901 #define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078)
3904 #define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c)
3905 #define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
3914 #define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8)
3923 #define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
3934 #define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064)
3955 #define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068)
3978 #define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
3986 #define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400)
3990 #define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450)
4559 #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
4585 #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
4586 #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
4587 #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
4592 #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
4597 #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
4598 #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
4599 #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
4601 #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
4602 #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
4607 #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
4611 #define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0)
4616 #define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4)
4621 #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721e0)
4623 #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
4624 #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
4625 #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
4626 #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
4627 #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
4628 #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
4629 #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
4630 #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
4631 #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
4632 #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
4633 #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
4634 #define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0)
4635 #define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4)
4636 #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722e0)
4666 _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
5109 #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400)
6159 #define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)
6160 #define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)
6161 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)
6163 #define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)
6164 #define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)
6165 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)
6167 #define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0)
6168 #define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4)
6169 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8)
6576 #define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C)
7876 #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
7877 #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
7878 #define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908)
7879 #define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C)
7880 #define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910)
7881 #define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000)
7885 #define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000)
7889 #define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00)
7894 #define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900)
7895 #define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904)
7896 #define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908)
7897 #define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C)
7898 #define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910)
7899 #define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000)
7900 #define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000)
7901 #define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00)