Lines Matching +full:slew +full:- +full:time +full:- +full:us
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
43 * registers that are defined solely for the use by function-like macros.
51 * should be defined using function-like macros.
57 * with underscore, followed by a function-like macro choosing the right
67 * function-like macros may be used to define bit fields, but do note that the
86 * Try to re-use existing register macro definitions. Only add new macros for
118 #define DISPLAY_MMIO_BASE(dev_priv) (INTEL_INFO(dev_priv)->display.mmio_offset)
122 * numbers, pick the 0-based __index'th value.
126 #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
129 * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
164 #define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->display.pipe_offsets[(pipe)] - \
165 INTEL_INFO(dev_priv)->display.pipe_offsets[PIPE_A] + \
167 #define _MMIO_TRANS2(tran, reg) _MMIO(INTEL_INFO(dev_priv)->display.trans_offsets[(tran)] - \
168 INTEL_INFO(dev_priv)->display.trans_offsets[TRANSCODER_A] + \
170 #define _MMIO_CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->display.cursor_offsets[(pipe)] - \
171 INTEL_INFO(dev_priv)->display.cursor_offsets[PIPE_A] + \
268 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
614 _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))
617 (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \
618 (reg_ch1) - _BXT_PHY0_BASE))
901 * [0-7] @ 0x2000 gen2,gen3
902 * [8-15] @ 0x3000 945,g33,pnv
904 * [0-15] @ 0x3000 gen4,gen5
906 * [0-15] @ 0x100000 gen6,vlv,chv
907 * [0-31] @ 0x100000 gen7+
912 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
920 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
949 #define PRB0_BASE (0x2030 - 0x30)
950 #define PRB1_BASE (0x2040 - 0x30) /* 830,gen3 */
951 #define PRB2_BASE (0x2050 - 0x30) /* gen3 */
952 #define SRB0_BASE (0x2100 - 0x30) /* gen2 */
953 #define SRB1_BASE (0x2110 - 0x30) /* gen2 */
954 #define SRB2_BASE (0x2120 - 0x30) /* 830 */
955 #define SRB3_BASE (0x2130 - 0x30) /* 830 */
1068 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */
1186 /* Enables non-sequential data reads through arbiter
1195 /* Arbiter time slice for non-isoch streams */
1229 * These defines should cover us well from SNB->HSW with minor exceptions
1268 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */
1303 #define VLV_AUD_PORT_EN_DBG(port) _MMIO_PORT3((port) - PORT_B, \
1383 #define DPFC_CTL_PLANE_MASK_G4X REG_BIT(30) /* g4x-snb */
1385 #define DPFC_CTL_FENCE_EN_G4X REG_BIT(29) /* g4x-snb */
1389 #define DPFC_CTL_PERSISTENT_MODE REG_BIT(25) /* g4x-snb */
1415 #define DPFC_HT_MODIFY REG_BIT(31) /* pre-ivb */
1529 #define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch))))
1530 #define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline)…
1539 /* i830, required in DVO non-gang */
1551 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9)
1653 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
1654 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
1655 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
1656 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
1657 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
1658 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
1659 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
1660 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
1661 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
1662 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
1663 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
1664 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
1670 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
1671 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
1772 #define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */
2159 0 : ((trans) - TRANSCODER_A + 1) * 8)
2224 #define EDP_SU_TRACK_ENABLE (1 << 30) /* up to adl-p */
2232 #define EDP_PSR2_IO_BUFFER_WAKE(lines) ((EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - (lines)) << 13)
2236 #define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines) (((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << …
2239 #define EDP_PSR2_FAST_WAKE(lines) ((EDP_PSR2_FAST_WAKE_MAX_LINES - (lines)) << 11)
2243 #define TGL_EDP_PSR2_FAST_WAKE(lines) (((lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << TGL_EDP_P…
2325 #define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2328 #define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2331 #define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2334 #define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2353 #define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2356 #define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2359 #define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2362 #define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2378 #define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2381 #define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2384 #define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2387 #define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2403 #define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2406 #define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2409 #define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2412 #define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2429 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
2594 * Programmed value is multiplier - 1, up to 5x.
2685 /* Selects pipe B for LVDS data. Must be set on pre-965. */
2698 /* Enable border for unscaled (or aspect-scaled) display */
2701 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
2723 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
2724 * setting for whether we are in dual-channel mode. The B3 pair will
2735 * of the infoframe structure specified by CEA-861. */
2781 #define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->display.pps.mmio_base - \
2791 * - PLL enabled
2792 * - pipe enabled
2793 * - LVDS/DVOB/DVOC on
2864 /* Pre-965 */
2910 /* Sets the colorburst to PAL mode. Required for non-M PAL modes. */
2925 /* Read-only state that reports all features enabled */
2927 /* Read-only state that reports that Macrovision is disabled in hardware*/
2929 /* Read-only state that reports that TV-out is disabled in hardware. */
2933 /* Encoder test pattern 1 - combo pattern */
2935 /* Encoder test pattern 2 - full screen vertical 75% color bars */
2937 /* Encoder test pattern 3 - full screen horizontal 75% color bars */
2939 /* Encoder test pattern 4 - random noise */
2941 /* Encoder test pattern 5 - linear color ramps */
2967 * Enables DAC state detection logic, for load-based TV detection.
2981 /* Sets the slew rate. Must be preserved in software */
2998 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
2999 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
3000 * -1 (0x3) being the only legal negative value.
3054 /* 2s-complement brightness adjustment */
3084 /* Enables the colorburst (needed for non-component color) */
3288 * (src width - 1) / ((oversample * dest width) - 1)
3295 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
3297 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
3302 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
3311 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
3313 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
3320 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
3380 /* Link training mode - select a suitable mode for each stage */
3404 /* Signal pre-emphasis levels, like voltages, the other end tells us what
3415 #define DP_PORT_WIDTH(width) (((width) - 1) << 19)
3474 0, /* port/aux_ch C is non-existent */ \
3488 0, /* port/aux_ch C is non-existent */ \
3522 #define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
3523 #define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
3541 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
3543 #define TU_SIZE(x) REG_FIELD_PREP(TU_SIZE_MASK, (x) - 1) /* default size 64 */
3559 * Attributes and VB-ID.
3580 #define PIPECONF_DOUBLE_WIDE REG_BIT(30) /* pre-i965 */
3583 #define PIPECONF_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* pre-hsw */
3584 …ECONF_FRAME_START_DELAY(x) REG_FIELD_PREP(PIPECONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */
3588 #define PIPECONF_GAMMA_MODE_MASK_ILK REG_GENMASK(25, 24) /* ilk-ivb */
3591 #define PIPECONF_GAMMA_MODE_12BIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */
3602 * DBL=power saving pixel doubling, PF-ID* requires panel fitter
3617 #define PIPECONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12, 11) /* ilk-ivb */
3618 #define PIPECONF_OUTPUT_COLORSPACE_RGB REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-…
3619 … PIPECONF_OUTPUT_COLORSPACE_YUV601 REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */
3620 … PIPECONF_OUTPUT_COLORSPACE_YUV709 REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */
3622 #define PIPECONF_BPC_MASK REG_GENMASK(7, 5) /* ctg-ivb */
3651 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL << 18) /* pre-965 */
3674 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL << 2) /* pre-965 */
3723 * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with
3725 * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of:
3870 #define DSPFW_PLANEC_OLD_MASK (0x7f << 0) /* pre-gen4 sprite C */
4154 #define CURSOR_STRIDE(stride) REG_FIELD_PREP(CURSOR_STRIDE_MASK, ffs(stride) - 9) /* 256,512,1k,2…
4284 #define DSPGAMC(plane, i) _MMIO_PIPE2(plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
4455 #define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 …
4639 _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
4656 #define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)…
4666 _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
4710 #define PLANE_CTL_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-GLK */
4714 * expanded to include bit 23 as well. However, the shift-24 based values
4717 #define PLANE_CTL_FORMAT_MASK_SKL REG_GENMASK(27, 24) /* pre-icl */
4736 #define PLANE_CTL_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-GLK */
4751 #define PLANE_CTL_PLANE_GAMMA_DISABLE REG_BIT(13) /* Pre-GLK */
4761 #define PLANE_CTL_ALPHA_MASK REG_GENMASK(5, 4) /* Pre-GLK */
4839 #define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */
4841 #define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */
5073 #define _SEL_FETCH_PLANE_BASE(pipe, plane) (_SEL_FETCH_PLANE_BASE_1(pipe) - \
5079 _SEL_FETCH_PLANE_CTL_1_A - \
5085 _SEL_FETCH_PLANE_POS_1_A - \
5090 _SEL_FETCH_PLANE_SIZE_1_A - \
5095 _SEL_FETCH_PLANE_OFFSET_1_A - \
5117 #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */
5118 #define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */
5119 #define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */
5120 #define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */
5121 #define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */
5396 #define GAMMA_MODE_MODE_SPLIT (3 << 0) /* ivb-bdw */
5401 #define MMIO_TIMEOUT_US(us) ((us) << 0) argument
5549 #define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A)
5550 #define _HPD_PIN_TC(hpd_pin) ((hpd_pin) - HPD_PORT_TC1)
5653 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
5768 * with display 13, the bspec switches to a 0-based numbering scheme
5770 * We'll just use the 0-based numbering here for all platforms since it's the
5787 #define DBUF_MIN_TRACKER_STATE_SERVICE_MASK REG_GENMASK(18, 16) /* ADL-P+ */
5788 …F_MIN_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x) /* ADL-P+ */
5907 /* south display engine interrupt: CPT - CNP */
5989 #define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */
5990 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */
5991 #define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */
5992 #define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */
5993 #define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */
6000 #define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */
6001 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */
6002 #define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */
6003 #define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */
6004 #define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */
6011 #define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */
6012 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */
6013 #define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */
6014 #define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */
6015 #define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */
6142 /* Per-transcoder DIP controls (PCH) */
6158 /* Per-transcoder DIP controls (VLV) */
6280 #define TRANS_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */
6301 #define TRANS_CHICKEN2_FRAME_START_DELAY(x) ((x) << 27) /* 0-3 */
6312 #define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
6313 #define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
6358 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
6360 /* SNB A-stepping */
6365 /* SNB B-stepping */
6373 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
6390 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
6491 #define PCH_DP_AUX_CH_CTL(aux_ch) _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AU…
6492 #define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_…
6502 #define TRANS_DP_PORT_SEL(port) REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, (port) - PORT_B)
6537 /* SNB A-stepping */
6542 /* SNB B-stepping */
6599 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
6652 /* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
6655 /* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */
6678 /* These are the 4 32-bit write offset registers for each stream
6685 * HSW - ICL power wells
6689 * - main (HSW_PWR_WELL_CTL[1-4])
6690 * - AUX (ICL_PWR_WELL_CTL_AUX[1-4])
6691 * - DDI (ICL_PWR_WELL_CTL_DDI[1-4])
6694 * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1)
6695 * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2)
6696 * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set)
6697 * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4)
6722 /* ICL/TGL - power wells */
6729 /* XE_LPD - power wells */
6781 /* HSW - power well misc debug registers */
6801 * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2
6804 ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1)
6807 * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4
6810 ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1)
6811 #define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
6813 #define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
6822 /* Per-pipe DDI Function Control */
6940 #define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
7038 #define WRPLL_REF_SPECIAL_HSW (2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */
7219 #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
7220 #define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
7228 (tc_port) - TC_PORT_4 + 21))
7308 /* ADL-P Type C PLL */
7401 /* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */
7424 (TC_PORT_1 + ((__reg).reg - _DKL_PHY1_BASE) / (_DKL_PHY2_BASE - _DKL_PHY1_BASE))
7624 /* Pipe WM_LINETIME - watermark line time */
7664 #define CSC_POSITION_BEFORE_GAMMA (1 << 1) /* pre-glk */
7912 /* Gen4+ Timestamp and Pipe Frame time stamp registers */
7947 #define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7961 #define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7990 #define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7993 #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8012 #define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8015 #define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8026 #define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8029 #define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8041 #define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8044 #define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8056 #define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8059 #define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8071 #define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8074 #define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8086 #define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8089 #define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8103 #define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8106 #define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8118 #define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8121 #define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8133 #define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8136 #define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8148 #define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8151 #define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8165 #define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8168 #define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8178 #define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8181 #define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8191 #define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8194 #define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8204 #define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8207 #define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8217 #define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8220 #define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8230 #define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8233 #define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8253 #define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8256 #define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8259 #define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8262 #define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8278 #define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8281 #define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8284 #define ICL_DSC1_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8287 #define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \