Lines Matching +full:36 +full:- +full:bit
176 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
177 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
186 .__runtime.platform_engine_mask = BIT(RCS0), \
198 .__runtime.pipe_mask = BIT(PIPE_A), \
199 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A), \
207 .__runtime.platform_engine_mask = BIT(RCS0), \
230 .__runtime.fbc_mask = BIT(INTEL_FBC_A),
236 .__runtime.fbc_mask = BIT(INTEL_FBC_A),
241 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
242 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
245 .__runtime.platform_engine_mask = BIT(RCS0), \
275 .__runtime.fbc_mask = BIT(INTEL_FBC_A),
300 .__runtime.fbc_mask = BIT(INTEL_FBC_A),
310 .dma_mask_size = 36,
318 .dma_mask_size = 36,
327 .dma_mask_size = 36,
332 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
333 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
337 .__runtime.platform_engine_mask = BIT(RCS0), \
341 .dma_mask_size = 36, \
360 .__runtime.fbc_mask = BIT(INTEL_FBC_A),
370 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
378 .__runtime.fbc_mask = BIT(INTEL_FBC_A),
380 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
386 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
387 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
389 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
395 .dma_mask_size = 36, \
412 .__runtime.fbc_mask = BIT(INTEL_FBC_A),
417 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
418 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
420 .__runtime.fbc_mask = BIT(INTEL_FBC_A), \
421 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
469 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
470 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
472 .__runtime.fbc_mask = BIT(INTEL_FBC_A), \
473 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
533 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
534 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
546 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
557 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
558 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
559 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
563 .has_rc6p = 0 /* RC6p removed-by HSW */, \
622 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
628 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
629 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
632 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
667 .display.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
668 .display.dbuf.slice_mask = BIT(DBUF_S1)
687 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
703 .display.dbuf.slice_mask = BIT(DBUF_S1), \
705 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
706 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
707 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
708 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
709 BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
714 .__runtime.fbc_mask = BIT(INTEL_FBC_A), \
741 .display.dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
748 .display.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
770 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
791 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
816 .display.abox_mask = BIT(0), \
817 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
818 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
819 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
839 .display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
848 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
854 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
855 .__runtime.ppgtt_size = 36,
861 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
862 .__runtime.ppgtt_size = 36,
869 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
870 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
871 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
872 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
899 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
905 .display.abox_mask = BIT(0),
906 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
907 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
908 BIT(TRANSCODER_C),
912 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
928 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
931 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
932 BIT(VCS0) | BIT(VCS2),
940 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
944 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
956 .display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
957 BIT(DBUF_S4), \
963 .__runtime.fbc_mask = BIT(INTEL_FBC_A), \
970 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
993 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
994 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
995 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
1000 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
1048 BIT(RCS0) | BIT(BCS0) |
1049 BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |
1050 BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) |
1051 BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7) |
1052 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
1070 BIT(RCS0) | BIT(BCS0) | \
1071 BIT(VECS0) | BIT(VECS1) | \
1072 BIT(VCS0) | BIT(VCS2) | \
1073 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3)
1078 .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
1079 BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
1110 BIT(BCS0) |
1111 BIT(VCS0) |
1112 BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
1120 .__runtime.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B)
1127 .engine_mask = BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
1149 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),
1299 int gttmmaddr_bar = intel_info->__runtime.graphics.ip.ver == 2 ? GEN2_GTTMMADR_BAR : GTTMMADR_BAR; in intel_mmio_bar_valid()
1307 (struct intel_device_info *) ent->driver_data; in i915_pci_probe()
1310 if (intel_info->require_force_probe && in i915_pci_probe()
1311 !force_probe(pdev->device, i915_modparams.force_probe)) { in i915_pci_probe()
1312 dev_info(&pdev->dev, in i915_pci_probe()
1317 pdev->device, pdev->device, pdev->device); in i915_pci_probe()
1318 return -ENODEV; in i915_pci_probe()
1322 * used function 1 as a placeholder for multi-head. This causes in i915_pci_probe()
1324 * functions have the same PCI-ID! in i915_pci_probe()
1326 if (PCI_FUNC(pdev->devfn)) in i915_pci_probe()
1327 return -ENODEV; in i915_pci_probe()
1330 return -ENXIO; in i915_pci_probe()
1334 return -EPROBE_DEFER; in i915_pci_probe()
1342 return -ENODEV; in i915_pci_probe()
1348 return err > 0 ? -ENOTTY : err; in i915_pci_probe()
1354 return err > 0 ? -ENOTTY : err; in i915_pci_probe()