Lines Matching +full:sub +full:- +full:sampled
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
11 * distribute, sub license, and/or sell copies of the Software, and to
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
81 WRITE_ONCE(i915->pmu.irq_count, i915->pmu.irq_count + 1); in pmu_irq_stats()
188 struct intel_hotplug *hpd = &dev_priv->display.hotplug; in intel_hpd_init_pins()
193 hpd->hpd = hpd_status_g4x; in intel_hpd_init_pins()
195 hpd->hpd = hpd_status_i915; in intel_hpd_init_pins()
200 hpd->hpd = hpd_gen11; in intel_hpd_init_pins()
202 hpd->hpd = hpd_bxt; in intel_hpd_init_pins()
204 hpd->hpd = hpd_bdw; in intel_hpd_init_pins()
206 hpd->hpd = hpd_ivb; in intel_hpd_init_pins()
208 hpd->hpd = hpd_ilk; in intel_hpd_init_pins()
215 hpd->pch_hpd = hpd_sde_dg1; in intel_hpd_init_pins()
217 hpd->pch_hpd = hpd_icp; in intel_hpd_init_pins()
219 hpd->pch_hpd = hpd_spt; in intel_hpd_init_pins()
221 hpd->pch_hpd = hpd_cpt; in intel_hpd_init_pins()
223 hpd->pch_hpd = hpd_ibx; in intel_hpd_init_pins()
233 drm_crtc_handle_vblank(&crtc->base); in intel_handle_vblank()
275 drm_WARN(&uncore->i915->drm, 1, in gen3_assert_iir_is_zero()
291 drm_WARN(&uncore->i915->drm, 1, in gen2_assert_iir_is_zero()
330 lockdep_assert_held(&dev_priv->irq_lock); in i915_hotplug_interrupt_update_locked()
331 drm_WARN_ON(&dev_priv->drm, bits & ~mask); in i915_hotplug_interrupt_update_locked()
333 val = intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_EN); in i915_hotplug_interrupt_update_locked()
336 intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_EN, val); in i915_hotplug_interrupt_update_locked()
340 * i915_hotplug_interrupt_update - update hotplug interrupt enable
345 * of an interrupt context. To avoid that read-modify-write cycles
348 * held already, this function acquires the lock itself. A non-locking
355 spin_lock_irq(&dev_priv->irq_lock); in i915_hotplug_interrupt_update()
357 spin_unlock_irq(&dev_priv->irq_lock); in i915_hotplug_interrupt_update()
361 * ilk_update_display_irq - update DEIMR
371 lockdep_assert_held(&dev_priv->irq_lock); in ilk_update_display_irq()
372 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask); in ilk_update_display_irq()
374 new_val = dev_priv->irq_mask; in ilk_update_display_irq()
378 if (new_val != dev_priv->irq_mask && in ilk_update_display_irq()
379 !drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) { in ilk_update_display_irq()
380 dev_priv->irq_mask = new_val; in ilk_update_display_irq()
381 intel_uncore_write(&dev_priv->uncore, DEIMR, dev_priv->irq_mask); in ilk_update_display_irq()
382 intel_uncore_posting_read(&dev_priv->uncore, DEIMR); in ilk_update_display_irq()
397 * bdw_update_port_irq - update DE port interrupt
409 lockdep_assert_held(&dev_priv->irq_lock); in bdw_update_port_irq()
411 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask); in bdw_update_port_irq()
413 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) in bdw_update_port_irq()
416 old_val = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IMR); in bdw_update_port_irq()
423 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PORT_IMR, new_val); in bdw_update_port_irq()
424 intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PORT_IMR); in bdw_update_port_irq()
429 * bdw_update_pipe_irq - update DE pipe interrupt
441 lockdep_assert_held(&dev_priv->irq_lock); in bdw_update_pipe_irq()
443 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask); in bdw_update_pipe_irq()
445 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) in bdw_update_pipe_irq()
448 new_val = dev_priv->de_irq_mask[pipe]; in bdw_update_pipe_irq()
452 if (new_val != dev_priv->de_irq_mask[pipe]) { in bdw_update_pipe_irq()
453 dev_priv->de_irq_mask[pipe] = new_val; in bdw_update_pipe_irq()
454 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); in bdw_update_pipe_irq()
455 intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe)); in bdw_update_pipe_irq()
472 * ibx_display_interrupt_update - update SDEIMR
481 u32 sdeimr = intel_uncore_read(&dev_priv->uncore, SDEIMR); in ibx_display_interrupt_update()
485 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask); in ibx_display_interrupt_update()
487 lockdep_assert_held(&dev_priv->irq_lock); in ibx_display_interrupt_update()
489 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv))) in ibx_display_interrupt_update()
492 intel_uncore_write(&dev_priv->uncore, SDEIMR, sdeimr); in ibx_display_interrupt_update()
493 intel_uncore_posting_read(&dev_priv->uncore, SDEIMR); in ibx_display_interrupt_update()
509 u32 status_mask = dev_priv->pipestat_irq_mask[pipe]; in i915_pipestat_enable_mask()
512 lockdep_assert_held(&dev_priv->irq_lock); in i915_pipestat_enable_mask()
521 if (drm_WARN_ON_ONCE(&dev_priv->drm, in i915_pipestat_enable_mask()
528 if (drm_WARN_ON_ONCE(&dev_priv->drm, in i915_pipestat_enable_mask()
541 drm_WARN_ONCE(&dev_priv->drm, in i915_pipestat_enable_mask()
556 drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK, in i915_enable_pipestat()
560 lockdep_assert_held(&dev_priv->irq_lock); in i915_enable_pipestat()
561 drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)); in i915_enable_pipestat()
563 if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == status_mask) in i915_enable_pipestat()
566 dev_priv->pipestat_irq_mask[pipe] |= status_mask; in i915_enable_pipestat()
569 intel_uncore_write(&dev_priv->uncore, reg, enable_mask | status_mask); in i915_enable_pipestat()
570 intel_uncore_posting_read(&dev_priv->uncore, reg); in i915_enable_pipestat()
579 drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK, in i915_disable_pipestat()
583 lockdep_assert_held(&dev_priv->irq_lock); in i915_disable_pipestat()
584 drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)); in i915_disable_pipestat()
586 if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == 0) in i915_disable_pipestat()
589 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask; in i915_disable_pipestat()
592 intel_uncore_write(&dev_priv->uncore, reg, enable_mask | status_mask); in i915_disable_pipestat()
593 intel_uncore_posting_read(&dev_priv->uncore, reg); in i915_disable_pipestat()
598 if (!dev_priv->display.opregion.asle) in i915_has_asle()
605 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
613 spin_lock_irq(&dev_priv->irq_lock); in i915_enable_asle_pipestat()
620 spin_unlock_irq(&dev_priv->irq_lock); in i915_enable_asle_pipestat()
640 * | may be shifted forward 1-3 extra lines via PIPECONF
647 * ----va---> <-----------------vb--------------------> <--------va-------------
648 * | | <----vs-----> |
649 …* -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter …
650 …* -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter …
651 …* -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter …
666 * - most events happen at the start of horizontal sync
667 * - frame start happens at the start of horizontal blank, 1-4 lines
669 * - gen3/4 pixel and frame counter are synchronized with the start
678 struct drm_i915_private *dev_priv = to_i915(crtc->dev); in i915_get_vblank_counter()
679 struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)]; in i915_get_vblank_counter()
680 const struct drm_display_mode *mode = &vblank->hwmode; in i915_get_vblank_counter()
681 enum pipe pipe = to_intel_crtc(crtc)->pipe; in i915_get_vblank_counter()
693 * does not like us returning non-zero frame counter values in i915_get_vblank_counter()
695 * counter. Thus we must stop non-zero values leaking out. in i915_get_vblank_counter()
697 if (!vblank->max_vblank_count) in i915_get_vblank_counter()
700 htotal = mode->crtc_htotal; in i915_get_vblank_counter()
701 hsync_start = mode->crtc_hsync_start; in i915_get_vblank_counter()
702 vbl_start = mode->crtc_vblank_start; in i915_get_vblank_counter()
703 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in i915_get_vblank_counter()
710 vbl_start -= htotal - hsync_start; in i915_get_vblank_counter()
715 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); in i915_get_vblank_counter()
728 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); in i915_get_vblank_counter()
744 struct drm_i915_private *dev_priv = to_i915(crtc->dev); in g4x_get_vblank_counter()
745 struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)]; in g4x_get_vblank_counter()
746 enum pipe pipe = to_intel_crtc(crtc)->pipe; in g4x_get_vblank_counter()
748 if (!vblank->max_vblank_count) in g4x_get_vblank_counter()
751 return intel_uncore_read(&dev_priv->uncore, PIPE_FRMCOUNT_G4X(pipe)); in g4x_get_vblank_counter()
756 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_crtc_scanlines_since_frame_timestamp()
758 &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)]; in intel_crtc_scanlines_since_frame_timestamp()
759 const struct drm_display_mode *mode = &vblank->hwmode; in intel_crtc_scanlines_since_frame_timestamp()
760 u32 htotal = mode->crtc_htotal; in intel_crtc_scanlines_since_frame_timestamp()
761 u32 clock = mode->crtc_clock; in intel_crtc_scanlines_since_frame_timestamp()
774 * is sampled at every start of vertical blank. in intel_crtc_scanlines_since_frame_timestamp()
777 PIPE_FRMTMSTMP(crtc->pipe)); in intel_crtc_scanlines_since_frame_timestamp()
786 PIPE_FRMTMSTMP(crtc->pipe)); in intel_crtc_scanlines_since_frame_timestamp()
789 return div_u64(mul_u32_u32(scan_curr_time - scan_prev_time, in intel_crtc_scanlines_since_frame_timestamp()
804 &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)]; in __intel_get_crtc_scanline_from_timestamp()
805 const struct drm_display_mode *mode = &vblank->hwmode; in __intel_get_crtc_scanline_from_timestamp()
806 u32 vblank_start = mode->crtc_vblank_start; in __intel_get_crtc_scanline_from_timestamp()
807 u32 vtotal = mode->crtc_vtotal; in __intel_get_crtc_scanline_from_timestamp()
811 scanline = min(scanline, vtotal - 1); in __intel_get_crtc_scanline_from_timestamp()
823 struct drm_device *dev = crtc->base.dev; in __intel_get_crtc_scanline()
827 enum pipe pipe = crtc->pipe; in __intel_get_crtc_scanline()
830 if (!crtc->active) in __intel_get_crtc_scanline()
833 vblank = &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)]; in __intel_get_crtc_scanline()
834 mode = &vblank->hwmode; in __intel_get_crtc_scanline()
836 if (crtc->mode_flags & I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP) in __intel_get_crtc_scanline()
839 vtotal = mode->crtc_vtotal; in __intel_get_crtc_scanline()
840 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in __intel_get_crtc_scanline()
874 return (position + crtc->scanline_offset) % vtotal; in __intel_get_crtc_scanline()
883 struct drm_device *dev = _crtc->dev; in i915_get_crtc_scanoutpos()
886 enum pipe pipe = crtc->pipe; in i915_get_crtc_scanoutpos()
892 crtc->mode_flags & I915_MODE_FLAG_USE_SCANLINE_COUNTER; in i915_get_crtc_scanoutpos()
894 if (drm_WARN_ON(&dev_priv->drm, !mode->crtc_clock)) { in i915_get_crtc_scanoutpos()
895 drm_dbg(&dev_priv->drm, in i915_get_crtc_scanoutpos()
901 htotal = mode->crtc_htotal; in i915_get_crtc_scanoutpos()
902 hsync_start = mode->crtc_hsync_start; in i915_get_crtc_scanoutpos()
903 vtotal = mode->crtc_vtotal; in i915_get_crtc_scanoutpos()
904 vbl_start = mode->crtc_vblank_start; in i915_get_crtc_scanoutpos()
905 vbl_end = mode->crtc_vblank_end; in i915_get_crtc_scanoutpos()
907 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { in i915_get_crtc_scanoutpos()
918 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); in i915_get_crtc_scanoutpos()
926 if (crtc->mode_flags & I915_MODE_FLAG_VRR) { in i915_get_crtc_scanoutpos()
938 position = min(crtc->vmax_vblank_start + scanlines, vtotal - 1); in i915_get_crtc_scanoutpos()
966 position = vtotal - 1; in i915_get_crtc_scanoutpos()
975 * always add htotal-hsync_start to the current pixel position. in i915_get_crtc_scanoutpos()
977 position = (position + htotal - hsync_start) % vtotal; in i915_get_crtc_scanoutpos()
986 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); in i915_get_crtc_scanoutpos()
995 position -= vbl_end; in i915_get_crtc_scanoutpos()
997 position += vtotal - vbl_end; in i915_get_crtc_scanoutpos()
1004 *hpos = position - (*vpos * htotal); in i915_get_crtc_scanoutpos()
1020 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_get_crtc_scanline()
1024 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); in intel_get_crtc_scanline()
1026 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); in intel_get_crtc_scanline()
1032 * ivb_parity_work - Workqueue called when a parity error interrupt
1054 mutex_lock(&dev_priv->drm.struct_mutex); in ivb_parity_work()
1057 if (drm_WARN_ON(&dev_priv->drm, !dev_priv->l3_parity.which_slice)) in ivb_parity_work()
1060 misccpctl = intel_uncore_read(&dev_priv->uncore, GEN7_MISCCPCTL); in ivb_parity_work()
1061 intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); in ivb_parity_work()
1062 intel_uncore_posting_read(&dev_priv->uncore, GEN7_MISCCPCTL); in ivb_parity_work()
1064 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { in ivb_parity_work()
1067 slice--; in ivb_parity_work()
1068 if (drm_WARN_ON_ONCE(&dev_priv->drm, in ivb_parity_work()
1072 dev_priv->l3_parity.which_slice &= ~(1<<slice); in ivb_parity_work()
1076 error_status = intel_uncore_read(&dev_priv->uncore, reg); in ivb_parity_work()
1081 intel_uncore_write(&dev_priv->uncore, reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); in ivb_parity_work()
1082 intel_uncore_posting_read(&dev_priv->uncore, reg); in ivb_parity_work()
1091 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj, in ivb_parity_work()
1094 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", in ivb_parity_work()
1103 intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl); in ivb_parity_work()
1106 drm_WARN_ON(&dev_priv->drm, dev_priv->l3_parity.which_slice); in ivb_parity_work()
1107 spin_lock_irq(gt->irq_lock); in ivb_parity_work()
1109 spin_unlock_irq(gt->irq_lock); in ivb_parity_work()
1111 mutex_unlock(&dev_priv->drm.struct_mutex); in ivb_parity_work()
1262 drm_dbg(&dev_priv->drm, in intel_get_hpd_pins()
1274 for_each_intel_encoder(&dev_priv->drm, encoder) in intel_hpd_enabled_irqs()
1275 if (dev_priv->display.hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED) in intel_hpd_enabled_irqs()
1276 enabled_irqs |= hpd[encoder->hpd_pin]; in intel_hpd_enabled_irqs()
1287 for_each_intel_encoder(&dev_priv->drm, encoder) in intel_hpd_hotplug_irqs()
1288 hotplug_irqs |= hpd[encoder->hpd_pin]; in intel_hpd_hotplug_irqs()
1299 for_each_intel_encoder(&i915->drm, encoder) in intel_hpd_hotplug_enables()
1300 hotplug |= hotplug_enables(i915, encoder->hpd_pin); in intel_hpd_hotplug_enables()
1307 wake_up_all(&dev_priv->display.gmbus.wait_queue); in gmbus_irq_handler()
1312 wake_up_all(&dev_priv->display.gmbus.wait_queue); in dp_aux_irq_handler()
1323 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc; in display_pipe_crc_irq_handler()
1328 spin_lock(&pipe_crc->lock); in display_pipe_crc_irq_handler()
1337 if (pipe_crc->skipped <= 0 || in display_pipe_crc_irq_handler()
1338 (DISPLAY_VER(dev_priv) >= 8 && pipe_crc->skipped == 1)) { in display_pipe_crc_irq_handler()
1339 pipe_crc->skipped++; in display_pipe_crc_irq_handler()
1340 spin_unlock(&pipe_crc->lock); in display_pipe_crc_irq_handler()
1343 spin_unlock(&pipe_crc->lock); in display_pipe_crc_irq_handler()
1345 drm_crtc_add_crc_entry(&crtc->base, true, in display_pipe_crc_irq_handler()
1346 drm_crtc_accurate_vblank_count(&crtc->base), in display_pipe_crc_irq_handler()
1362 struct drm_crtc_state *crtc_state = crtc->base.state; in flip_done_handler()
1363 struct drm_pending_vblank_event *e = crtc_state->event; in flip_done_handler()
1364 struct drm_device *dev = &i915->drm; in flip_done_handler()
1367 spin_lock_irqsave(&dev->event_lock, irqflags); in flip_done_handler()
1369 crtc_state->event = NULL; in flip_done_handler()
1371 drm_crtc_send_vblank_event(&crtc->base, e); in flip_done_handler()
1373 spin_unlock_irqrestore(&dev->event_lock, irqflags); in flip_done_handler()
1380 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)), in hsw_pipe_crc_irq_handler()
1388 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)), in ivb_pipe_crc_irq_handler()
1389 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_2_IVB(pipe)), in ivb_pipe_crc_irq_handler()
1390 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_3_IVB(pipe)), in ivb_pipe_crc_irq_handler()
1391 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_4_IVB(pipe)), in ivb_pipe_crc_irq_handler()
1392 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_5_IVB(pipe))); in ivb_pipe_crc_irq_handler()
1401 res1 = intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RES1_I915(pipe)); in i9xx_pipe_crc_irq_handler()
1406 res2 = intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RES2_G4X(pipe)); in i9xx_pipe_crc_irq_handler()
1411 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RED(pipe)), in i9xx_pipe_crc_irq_handler()
1412 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_GREEN(pipe)), in i9xx_pipe_crc_irq_handler()
1413 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_BLUE(pipe)), in i9xx_pipe_crc_irq_handler()
1422 intel_uncore_write(&dev_priv->uncore, PIPESTAT(pipe), in i9xx_pipestat_irq_reset()
1426 dev_priv->pipestat_irq_mask[pipe] = 0; in i9xx_pipestat_irq_reset()
1435 spin_lock(&dev_priv->irq_lock); in i9xx_pipestat_irq_ack()
1437 if (!dev_priv->display_irqs_enabled) { in i9xx_pipestat_irq_ack()
1438 spin_unlock(&dev_priv->irq_lock); in i9xx_pipestat_irq_ack()
1470 status_mask |= dev_priv->pipestat_irq_mask[pipe]; in i9xx_pipestat_irq_ack()
1476 pipe_stats[pipe] = intel_uncore_read(&dev_priv->uncore, reg) & status_mask; in i9xx_pipestat_irq_ack()
1489 intel_uncore_write(&dev_priv->uncore, reg, pipe_stats[pipe]); in i9xx_pipestat_irq_ack()
1490 intel_uncore_write(&dev_priv->uncore, reg, enable_mask); in i9xx_pipestat_irq_ack()
1493 spin_unlock(&dev_priv->irq_lock); in i9xx_pipestat_irq_ack()
1609 u32 tmp = intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT) & hotplug_status_mask; in i9xx_hpd_irq_ack()
1615 intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_STAT, hotplug_status); in i9xx_hpd_irq_ack()
1618 drm_WARN_ONCE(&dev_priv->drm, 1, in i9xx_hpd_irq_ack()
1620 intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT)); in i9xx_hpd_irq_ack()
1640 dev_priv->display.hotplug.hpd, in i9xx_hpd_irq_handler()
1661 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in valleyview_irq_handler()
1669 gt_iir = intel_uncore_read(&dev_priv->uncore, GTIIR); in valleyview_irq_handler()
1670 pm_iir = intel_uncore_read(&dev_priv->uncore, GEN6_PMIIR); in valleyview_irq_handler()
1671 iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR); in valleyview_irq_handler()
1685 * A CPU interrupt will only be raised when 'x' has a 0->1 edge. in valleyview_irq_handler()
1691 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0); in valleyview_irq_handler()
1692 ier = intel_uncore_read(&dev_priv->uncore, VLV_IER); in valleyview_irq_handler()
1693 intel_uncore_write(&dev_priv->uncore, VLV_IER, 0); in valleyview_irq_handler()
1696 intel_uncore_write(&dev_priv->uncore, GTIIR, gt_iir); in valleyview_irq_handler()
1698 intel_uncore_write(&dev_priv->uncore, GEN6_PMIIR, pm_iir); in valleyview_irq_handler()
1716 intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir); in valleyview_irq_handler()
1718 intel_uncore_write(&dev_priv->uncore, VLV_IER, ier); in valleyview_irq_handler()
1719 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); in valleyview_irq_handler()
1724 gen6_rps_irq_handler(&to_gt(dev_priv)->rps, pm_iir); in valleyview_irq_handler()
1734 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in valleyview_irq_handler()
1748 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in cherryview_irq_handler()
1756 master_ctl = intel_uncore_read(&dev_priv->uncore, GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; in cherryview_irq_handler()
1757 iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR); in cherryview_irq_handler()
1771 * A CPU interrupt will only be raised when 'x' has a 0->1 edge. in cherryview_irq_handler()
1777 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, 0); in cherryview_irq_handler()
1778 ier = intel_uncore_read(&dev_priv->uncore, VLV_IER); in cherryview_irq_handler()
1779 intel_uncore_write(&dev_priv->uncore, VLV_IER, 0); in cherryview_irq_handler()
1800 intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir); in cherryview_irq_handler()
1802 intel_uncore_write(&dev_priv->uncore, VLV_IER, ier); in cherryview_irq_handler()
1803 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); in cherryview_irq_handler()
1813 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in cherryview_irq_handler()
1829 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG); in ibx_hpd_irq_handler()
1838 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, dig_hotplug_reg); in ibx_hpd_irq_handler()
1844 dev_priv->display.hotplug.pch_hpd, in ibx_hpd_irq_handler()
1860 drm_dbg(&dev_priv->drm, "PCH audio power change on port %d\n", in ibx_irq_handler()
1871 drm_dbg(&dev_priv->drm, "PCH HDCP audio interrupt\n"); in ibx_irq_handler()
1874 drm_dbg(&dev_priv->drm, "PCH transcoder audio interrupt\n"); in ibx_irq_handler()
1877 drm_err(&dev_priv->drm, "PCH poison interrupt\n"); in ibx_irq_handler()
1881 drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n", in ibx_irq_handler()
1883 intel_uncore_read(&dev_priv->uncore, FDI_RX_IIR(pipe))); in ibx_irq_handler()
1887 drm_dbg(&dev_priv->drm, "PCH transcoder CRC done interrupt\n"); in ibx_irq_handler()
1890 drm_dbg(&dev_priv->drm, in ibx_irq_handler()
1902 u32 err_int = intel_uncore_read(&dev_priv->uncore, GEN7_ERR_INT); in ivb_err_int_handler()
1906 drm_err(&dev_priv->drm, "Poison interrupt\n"); in ivb_err_int_handler()
1920 intel_uncore_write(&dev_priv->uncore, GEN7_ERR_INT, err_int); in ivb_err_int_handler()
1925 u32 serr_int = intel_uncore_read(&dev_priv->uncore, SERR_INT); in cpt_serr_int_handler()
1929 drm_err(&dev_priv->drm, "PCH poison interrupt\n"); in cpt_serr_int_handler()
1935 intel_uncore_write(&dev_priv->uncore, SERR_INT, serr_int); in cpt_serr_int_handler()
1948 drm_dbg(&dev_priv->drm, "PCH audio power change on port %c\n", in cpt_irq_handler()
1959 drm_dbg(&dev_priv->drm, "Audio CP request interrupt\n"); in cpt_irq_handler()
1962 drm_dbg(&dev_priv->drm, "Audio CP change interrupt\n"); in cpt_irq_handler()
1966 drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n", in cpt_irq_handler()
1968 intel_uncore_read(&dev_priv->uncore, FDI_RX_IIR(pipe))); in cpt_irq_handler()
1984 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_DDI); in icp_irq_handler()
1985 intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_DDI, dig_hotplug_reg); in icp_irq_handler()
1989 dev_priv->display.hotplug.pch_hpd, in icp_irq_handler()
1996 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_TC); in icp_irq_handler()
1997 intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_TC, dig_hotplug_reg); in icp_irq_handler()
2001 dev_priv->display.hotplug.pch_hpd, in icp_irq_handler()
2022 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG); in spt_irq_handler()
2023 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, dig_hotplug_reg); in spt_irq_handler()
2027 dev_priv->display.hotplug.pch_hpd, in spt_irq_handler()
2034 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG2); in spt_irq_handler()
2035 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG2, dig_hotplug_reg); in spt_irq_handler()
2039 dev_priv->display.hotplug.pch_hpd, in spt_irq_handler()
2055 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL); in ilk_hpd_irq_handler()
2056 intel_uncore_write(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg); in ilk_hpd_irq_handler()
2060 dev_priv->display.hotplug.hpd, in ilk_hpd_irq_handler()
2082 drm_err(&dev_priv->drm, "Poison interrupt\n"); in ilk_display_irq_handler()
2100 u32 pch_iir = intel_uncore_read(&dev_priv->uncore, SDEIIR); in ilk_display_irq_handler()
2108 intel_uncore_write(&dev_priv->uncore, SDEIIR, pch_iir); in ilk_display_irq_handler()
2112 gen5_rps_irq_handler(&to_gt(dev_priv)->rps); in ilk_display_irq_handler()
2143 u32 pch_iir = intel_uncore_read(&dev_priv->uncore, SDEIIR); in ivb_display_irq_handler()
2148 intel_uncore_write(&dev_priv->uncore, SDEIIR, pch_iir); in ivb_display_irq_handler()
2154 * 1 - Disable Master Interrupt Control.
2155 * 2 - Find the source(s) of the interrupt.
2156 * 3 - Clear the Interrupt Identity bits (IIR).
2157 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2158 * 5 - Re-enable Master Interrupt Control.
2163 void __iomem * const regs = i915->uncore.regs; in ilk_irq_handler()
2171 disable_rpm_wakeref_asserts(&i915->runtime_pm); in ilk_irq_handler()
2213 gen6_rps_irq_handler(&to_gt(i915)->rps, pm_iir); in ilk_irq_handler()
2225 enable_rpm_wakeref_asserts(&i915->runtime_pm); in ilk_irq_handler()
2235 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG); in bxt_hpd_irq_handler()
2236 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, dig_hotplug_reg); in bxt_hpd_irq_handler()
2240 dev_priv->display.hotplug.hpd, in bxt_hpd_irq_handler()
2255 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL); in gen11_hpd_irq_handler()
2256 intel_uncore_write(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL, dig_hotplug_reg); in gen11_hpd_irq_handler()
2260 dev_priv->display.hotplug.hpd, in gen11_hpd_irq_handler()
2267 dig_hotplug_reg = intel_uncore_read(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL); in gen11_hpd_irq_handler()
2268 intel_uncore_write(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL, dig_hotplug_reg); in gen11_hpd_irq_handler()
2272 dev_priv->display.hotplug.hpd, in gen11_hpd_irq_handler()
2279 drm_err(&dev_priv->drm, in gen11_hpd_irq_handler()
2350 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { in gen8_de_misc_irq_handler()
2354 iir_reg = TRANS_PSR_IIR(intel_dp->psr.transcoder); in gen8_de_misc_irq_handler()
2358 psr_iir = intel_uncore_read(&dev_priv->uncore, iir_reg); in gen8_de_misc_irq_handler()
2359 intel_uncore_write(&dev_priv->uncore, iir_reg, psr_iir); in gen8_de_misc_irq_handler()
2373 drm_err(&dev_priv->drm, "Unexpected DE Misc interrupt\n"); in gen8_de_misc_irq_handler()
2388 val = intel_uncore_read(&dev_priv->uncore, TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0)); in gen11_dsi_te_interrupt_handler()
2400 val = intel_uncore_read(&dev_priv->uncore, DSI_TRANS_FUNC_CONF(dsi_trans)); in gen11_dsi_te_interrupt_handler()
2404 drm_err(&dev_priv->drm, "DSI trancoder not configured in command mode\n"); in gen11_dsi_te_interrupt_handler()
2409 val = intel_uncore_read(&dev_priv->uncore, TRANS_DDI_FUNC_CTL(dsi_trans)); in gen11_dsi_te_interrupt_handler()
2421 drm_err(&dev_priv->drm, "Invalid PIPE\n"); in gen11_dsi_te_interrupt_handler()
2429 tmp = intel_uncore_read(&dev_priv->uncore, DSI_INTR_IDENT_REG(port)); in gen11_dsi_te_interrupt_handler()
2430 intel_uncore_write(&dev_priv->uncore, DSI_INTR_IDENT_REG(port), tmp); in gen11_dsi_te_interrupt_handler()
2459 drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DISPLAY(dev_priv)); in gen8_de_irq_handler()
2462 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_MISC_IIR); in gen8_de_irq_handler()
2464 intel_uncore_write(&dev_priv->uncore, GEN8_DE_MISC_IIR, iir); in gen8_de_irq_handler()
2468 drm_err(&dev_priv->drm, in gen8_de_irq_handler()
2474 iir = intel_uncore_read(&dev_priv->uncore, GEN11_DE_HPD_IIR); in gen8_de_irq_handler()
2476 intel_uncore_write(&dev_priv->uncore, GEN11_DE_HPD_IIR, iir); in gen8_de_irq_handler()
2480 drm_err(&dev_priv->drm, in gen8_de_irq_handler()
2486 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IIR); in gen8_de_irq_handler()
2490 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PORT_IIR, iir); in gen8_de_irq_handler()
2530 drm_err(&dev_priv->drm, in gen8_de_irq_handler()
2534 drm_err(&dev_priv->drm, in gen8_de_irq_handler()
2544 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe)); in gen8_de_irq_handler()
2546 drm_err(&dev_priv->drm, in gen8_de_irq_handler()
2552 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe), iir); in gen8_de_irq_handler()
2568 drm_err(&dev_priv->drm, in gen8_de_irq_handler()
2579 * on older pch-split platforms. But this needs testing. in gen8_de_irq_handler()
2581 iir = intel_uncore_read(&dev_priv->uncore, SDEIIR); in gen8_de_irq_handler()
2583 intel_uncore_write(&dev_priv->uncore, SDEIIR, iir); in gen8_de_irq_handler()
2597 drm_dbg(&dev_priv->drm, in gen8_de_irq_handler()
2626 void __iomem * const regs = dev_priv->uncore.regs; in gen8_irq_handler()
2638 /* Find, queue (onto bottom-halves), then clear each source */ in gen8_irq_handler()
2643 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in gen8_irq_handler()
2645 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in gen8_irq_handler()
2658 void __iomem * const regs = i915->uncore.regs; in gen11_gu_misc_irq_ack()
2699 void __iomem * const regs = i915->uncore.regs; in gen11_display_irq_handler()
2702 disable_rpm_wakeref_asserts(&i915->runtime_pm); in gen11_display_irq_handler()
2712 enable_rpm_wakeref_asserts(&i915->runtime_pm); in gen11_display_irq_handler()
2718 void __iomem * const regs = i915->uncore.regs; in gen11_irq_handler()
2732 /* Find, queue (onto bottom-halves), then clear each source */ in gen11_irq_handler()
2776 void __iomem * const regs = gt->uncore->regs; in dg1_irq_handler()
2820 struct drm_i915_private *dev_priv = to_i915(crtc->dev); in i8xx_enable_vblank()
2821 enum pipe pipe = to_intel_crtc(crtc)->pipe; in i8xx_enable_vblank()
2824 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in i8xx_enable_vblank()
2826 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in i8xx_enable_vblank()
2833 struct drm_i915_private *dev_priv = to_i915(crtc->dev); in i915gm_enable_vblank()
2837 * Disabling render clock gating during C-states avoids in i915gm_enable_vblank()
2841 if (dev_priv->vblank_enabled++ == 0) in i915gm_enable_vblank()
2842 …intel_uncore_write(&dev_priv->uncore, SCPD0, _MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE)); in i915gm_enable_vblank()
2849 struct drm_i915_private *dev_priv = to_i915(crtc->dev); in i965_enable_vblank()
2850 enum pipe pipe = to_intel_crtc(crtc)->pipe; in i965_enable_vblank()
2853 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in i965_enable_vblank()
2856 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in i965_enable_vblank()
2863 struct drm_i915_private *dev_priv = to_i915(crtc->dev); in ilk_enable_vblank()
2864 enum pipe pipe = to_intel_crtc(crtc)->pipe; in ilk_enable_vblank()
2869 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in ilk_enable_vblank()
2871 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in ilk_enable_vblank()
2885 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); in gen11_dsi_configure_te()
2889 if (!(intel_crtc->mode_flags & in gen11_dsi_configure_te()
2894 if (intel_crtc->mode_flags & I915_MODE_FLAG_DSI_USE_TE1) in gen11_dsi_configure_te()
2899 tmp = intel_uncore_read(&dev_priv->uncore, DSI_INTR_MASK_REG(port)); in gen11_dsi_configure_te()
2905 intel_uncore_write(&dev_priv->uncore, DSI_INTR_MASK_REG(port), tmp); in gen11_dsi_configure_te()
2907 tmp = intel_uncore_read(&dev_priv->uncore, DSI_INTR_IDENT_REG(port)); in gen11_dsi_configure_te()
2908 intel_uncore_write(&dev_priv->uncore, DSI_INTR_IDENT_REG(port), tmp); in gen11_dsi_configure_te()
2916 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in bdw_enable_vblank()
2917 enum pipe pipe = crtc->pipe; in bdw_enable_vblank()
2923 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in bdw_enable_vblank()
2925 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in bdw_enable_vblank()
2931 drm_crtc_vblank_restore(&crtc->base); in bdw_enable_vblank()
2941 struct drm_i915_private *dev_priv = to_i915(crtc->dev); in i8xx_disable_vblank()
2942 enum pipe pipe = to_intel_crtc(crtc)->pipe; in i8xx_disable_vblank()
2945 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in i8xx_disable_vblank()
2947 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in i8xx_disable_vblank()
2952 struct drm_i915_private *dev_priv = to_i915(crtc->dev); in i915gm_disable_vblank()
2956 if (--dev_priv->vblank_enabled == 0) in i915gm_disable_vblank()
2957 …intel_uncore_write(&dev_priv->uncore, SCPD0, _MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE)… in i915gm_disable_vblank()
2962 struct drm_i915_private *dev_priv = to_i915(crtc->dev); in i965_disable_vblank()
2963 enum pipe pipe = to_intel_crtc(crtc)->pipe; in i965_disable_vblank()
2966 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in i965_disable_vblank()
2969 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in i965_disable_vblank()
2974 struct drm_i915_private *dev_priv = to_i915(crtc->dev); in ilk_disable_vblank()
2975 enum pipe pipe = to_intel_crtc(crtc)->pipe; in ilk_disable_vblank()
2980 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in ilk_disable_vblank()
2982 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in ilk_disable_vblank()
2988 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in bdw_disable_vblank()
2989 enum pipe pipe = crtc->pipe; in bdw_disable_vblank()
2995 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in bdw_disable_vblank()
2997 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in bdw_disable_vblank()
3002 struct intel_uncore *uncore = &dev_priv->uncore; in ibx_irq_reset()
3010 intel_uncore_write(&dev_priv->uncore, SERR_INT, 0xffffffff); in ibx_irq_reset()
3015 struct intel_uncore *uncore = &dev_priv->uncore; in vlv_display_irq_reset()
3023 …intel_uncore_write(uncore, PORT_HOTPLUG_STAT, intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_ST… in vlv_display_irq_reset()
3028 dev_priv->irq_mask = ~0u; in vlv_display_irq_reset()
3033 struct intel_uncore *uncore = &dev_priv->uncore; in vlv_display_irq_postinstall()
3055 drm_WARN_ON(&dev_priv->drm, dev_priv->irq_mask != ~0u); in vlv_display_irq_postinstall()
3057 dev_priv->irq_mask = ~enable_mask; in vlv_display_irq_postinstall()
3059 GEN3_IRQ_INIT(uncore, VLV_, dev_priv->irq_mask, enable_mask); in vlv_display_irq_postinstall()
3066 struct intel_uncore *uncore = &dev_priv->uncore; in ilk_irq_reset()
3069 dev_priv->irq_mask = ~0u; in ilk_irq_reset()
3086 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, 0); in valleyview_irq_reset()
3087 intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER); in valleyview_irq_reset()
3091 spin_lock_irq(&dev_priv->irq_lock); in valleyview_irq_reset()
3092 if (dev_priv->display_irqs_enabled) in valleyview_irq_reset()
3094 spin_unlock_irq(&dev_priv->irq_lock); in valleyview_irq_reset()
3099 struct intel_uncore *uncore = &dev_priv->uncore; in gen8_display_irq_reset()
3119 struct intel_uncore *uncore = &dev_priv->uncore; in gen8_irq_reset()
3121 gen8_master_intr_disable(dev_priv->uncore.regs); in gen8_irq_reset()
3134 struct intel_uncore *uncore = &dev_priv->uncore; in gen11_display_irq_reset()
3178 struct intel_uncore *uncore = gt->uncore; in gen11_irq_reset()
3180 gen11_master_intr_disable(dev_priv->uncore.regs); in gen11_irq_reset()
3192 struct intel_uncore *uncore = gt->uncore; in dg1_irq_reset()
3194 dg1_master_intr_disable(dev_priv->uncore.regs); in dg1_irq_reset()
3206 struct intel_uncore *uncore = &dev_priv->uncore; in gen8_irq_power_well_post_enable()
3212 spin_lock_irq(&dev_priv->irq_lock); in gen8_irq_power_well_post_enable()
3215 spin_unlock_irq(&dev_priv->irq_lock); in gen8_irq_power_well_post_enable()
3221 dev_priv->de_irq_mask[pipe], in gen8_irq_power_well_post_enable()
3222 ~dev_priv->de_irq_mask[pipe] | extra_ier); in gen8_irq_power_well_post_enable()
3224 spin_unlock_irq(&dev_priv->irq_lock); in gen8_irq_power_well_post_enable()
3230 struct intel_uncore *uncore = &dev_priv->uncore; in gen8_irq_power_well_pre_disable()
3233 spin_lock_irq(&dev_priv->irq_lock); in gen8_irq_power_well_pre_disable()
3236 spin_unlock_irq(&dev_priv->irq_lock); in gen8_irq_power_well_pre_disable()
3243 spin_unlock_irq(&dev_priv->irq_lock); in gen8_irq_power_well_pre_disable()
3251 struct intel_uncore *uncore = &dev_priv->uncore; in cherryview_irq_reset()
3253 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, 0); in cherryview_irq_reset()
3254 intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ); in cherryview_irq_reset()
3260 spin_lock_irq(&dev_priv->irq_lock); in cherryview_irq_reset()
3261 if (dev_priv->display_irqs_enabled) in cherryview_irq_reset()
3263 spin_unlock_irq(&dev_priv->irq_lock); in cherryview_irq_reset()
3300 hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG); in ibx_hpd_detection_setup()
3309 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, hotplug); in ibx_hpd_detection_setup()
3316 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd); in ibx_hpd_irq_setup()
3317 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd); in ibx_hpd_irq_setup()
3358 hotplug = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_DDI); in icp_ddi_hpd_detection_setup()
3364 intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_DDI, hotplug); in icp_ddi_hpd_detection_setup()
3371 hotplug = intel_uncore_read(&dev_priv->uncore, SHOTPLUG_CTL_TC); in icp_tc_hpd_detection_setup()
3379 intel_uncore_write(&dev_priv->uncore, SHOTPLUG_CTL_TC, hotplug); in icp_tc_hpd_detection_setup()
3386 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd); in icp_hpd_irq_setup()
3387 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd); in icp_hpd_irq_setup()
3390 intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ); in icp_hpd_irq_setup()
3418 val = intel_uncore_read(&dev_priv->uncore, SOUTH_CHICKEN1); in dg1_hpd_irq_setup()
3423 intel_uncore_write(&dev_priv->uncore, SOUTH_CHICKEN1, val); in dg1_hpd_irq_setup()
3432 hotplug = intel_uncore_read(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL); in gen11_tc_hpd_detection_setup()
3440 intel_uncore_write(&dev_priv->uncore, GEN11_TC_HOTPLUG_CTL, hotplug); in gen11_tc_hpd_detection_setup()
3447 hotplug = intel_uncore_read(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL); in gen11_tbt_hpd_detection_setup()
3455 intel_uncore_write(&dev_priv->uncore, GEN11_TBT_HOTPLUG_CTL, hotplug); in gen11_tbt_hpd_detection_setup()
3463 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.hpd); in gen11_hpd_irq_setup()
3464 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.hpd); in gen11_hpd_irq_setup()
3466 val = intel_uncore_read(&dev_priv->uncore, GEN11_DE_HPD_IMR); in gen11_hpd_irq_setup()
3469 intel_uncore_write(&dev_priv->uncore, GEN11_DE_HPD_IMR, val); in gen11_hpd_irq_setup()
3470 intel_uncore_posting_read(&dev_priv->uncore, GEN11_DE_HPD_IMR); in gen11_hpd_irq_setup()
3513 val = intel_uncore_read(&dev_priv->uncore, SOUTH_CHICKEN1); in spt_hpd_detection_setup()
3516 intel_uncore_write(&dev_priv->uncore, SOUTH_CHICKEN1, val); in spt_hpd_detection_setup()
3520 hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG); in spt_hpd_detection_setup()
3526 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, hotplug); in spt_hpd_detection_setup()
3528 hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG2); in spt_hpd_detection_setup()
3531 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG2, hotplug); in spt_hpd_detection_setup()
3539 intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ); in spt_hpd_irq_setup()
3541 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd); in spt_hpd_irq_setup()
3542 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd); in spt_hpd_irq_setup()
3570 hotplug = intel_uncore_read(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL); in ilk_hpd_detection_setup()
3574 intel_uncore_write(&dev_priv->uncore, DIGITAL_PORT_HOTPLUG_CNTRL, hotplug); in ilk_hpd_detection_setup()
3581 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.hpd); in ilk_hpd_irq_setup()
3582 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.hpd); in ilk_hpd_irq_setup()
3624 hotplug = intel_uncore_read(&dev_priv->uncore, PCH_PORT_HOTPLUG); in bxt_hpd_detection_setup()
3632 intel_uncore_write(&dev_priv->uncore, PCH_PORT_HOTPLUG, hotplug); in bxt_hpd_detection_setup()
3639 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.hpd); in bxt_hpd_irq_setup()
3640 hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.hpd); in bxt_hpd_irq_setup()
3649 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3660 struct intel_uncore *uncore = &dev_priv->uncore; in ibx_irq_postinstall()
3678 struct intel_uncore *uncore = &dev_priv->uncore; in ilk_irq_postinstall()
3709 dev_priv->irq_mask = ~display_mask; in ilk_irq_postinstall()
3715 GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask, in ilk_irq_postinstall()
3721 lockdep_assert_held(&dev_priv->irq_lock); in valleyview_enable_display_irqs()
3723 if (dev_priv->display_irqs_enabled) in valleyview_enable_display_irqs()
3726 dev_priv->display_irqs_enabled = true; in valleyview_enable_display_irqs()
3736 lockdep_assert_held(&dev_priv->irq_lock); in valleyview_disable_display_irqs()
3738 if (!dev_priv->display_irqs_enabled) in valleyview_disable_display_irqs()
3741 dev_priv->display_irqs_enabled = false; in valleyview_disable_display_irqs()
3752 spin_lock_irq(&dev_priv->irq_lock); in valleyview_irq_postinstall()
3753 if (dev_priv->display_irqs_enabled) in valleyview_irq_postinstall()
3755 spin_unlock_irq(&dev_priv->irq_lock); in valleyview_irq_postinstall()
3757 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); in valleyview_irq_postinstall()
3758 intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER); in valleyview_irq_postinstall()
3763 struct intel_uncore *uncore = &dev_priv->uncore; in gen8_de_irq_postinstall()
3819 dev_priv->de_irq_mask[pipe] = ~de_pipe_masked; in gen8_de_irq_postinstall()
3824 dev_priv->de_irq_mask[pipe], in gen8_de_irq_postinstall()
3843 struct intel_uncore *uncore = &dev_priv->uncore; in icp_irq_postinstall()
3859 gen8_master_intr_enable(dev_priv->uncore.regs); in gen8_irq_postinstall()
3869 intel_uncore_write(&dev_priv->uncore, GEN11_DISPLAY_INT_CTL, in gen11_de_irq_postinstall()
3876 struct intel_uncore *uncore = gt->uncore; in gen11_irq_postinstall()
3887 gen11_master_intr_enable(uncore->regs); in gen11_irq_postinstall()
3888 intel_uncore_posting_read(&dev_priv->uncore, GEN11_GFX_MSTR_IRQ); in gen11_irq_postinstall()
3894 struct intel_uncore *uncore = gt->uncore; in dg1_irq_postinstall()
3904 intel_uncore_write(&dev_priv->uncore, GEN11_DISPLAY_INT_CTL, in dg1_irq_postinstall()
3908 dg1_master_intr_enable(uncore->regs); in dg1_irq_postinstall()
3916 spin_lock_irq(&dev_priv->irq_lock); in cherryview_irq_postinstall()
3917 if (dev_priv->display_irqs_enabled) in cherryview_irq_postinstall()
3919 spin_unlock_irq(&dev_priv->irq_lock); in cherryview_irq_postinstall()
3921 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); in cherryview_irq_postinstall()
3922 intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ); in cherryview_irq_postinstall()
3927 struct intel_uncore *uncore = &dev_priv->uncore; in i8xx_irq_reset()
3932 dev_priv->irq_mask = ~0u; in i8xx_irq_reset()
3937 struct intel_uncore *uncore = &dev_priv->uncore; in i8xx_irq_postinstall()
3946 dev_priv->irq_mask = in i8xx_irq_postinstall()
3957 GEN2_IRQ_INIT(uncore, dev_priv->irq_mask, enable_mask); in i8xx_irq_postinstall()
3959 /* Interrupt setup is already guaranteed to be single-threaded, this is in i8xx_irq_postinstall()
3961 spin_lock_irq(&dev_priv->irq_lock); in i8xx_irq_postinstall()
3964 spin_unlock_irq(&dev_priv->irq_lock); in i8xx_irq_postinstall()
3970 struct intel_uncore *uncore = &i915->uncore; in i8xx_error_irq_ack()
4003 drm_dbg(&dev_priv->drm, "EIR stuck: 0x%04x, masked\n", in i8xx_error_irq_handler()
4012 *eir = intel_uncore_read(&dev_priv->uncore, EIR); in i9xx_error_irq_ack()
4014 intel_uncore_write(&dev_priv->uncore, EIR, *eir); in i9xx_error_irq_ack()
4016 *eir_stuck = intel_uncore_read(&dev_priv->uncore, EIR); in i9xx_error_irq_ack()
4030 emr = intel_uncore_read(&dev_priv->uncore, EMR); in i9xx_error_irq_ack()
4031 intel_uncore_write(&dev_priv->uncore, EMR, 0xffffffff); in i9xx_error_irq_ack()
4032 intel_uncore_write(&dev_priv->uncore, EMR, emr | *eir_stuck); in i9xx_error_irq_ack()
4041 drm_dbg(&dev_priv->drm, "EIR stuck: 0x%08x, masked\n", in i9xx_error_irq_handler()
4054 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in i8xx_irq_handler()
4061 iir = intel_uncore_read16(&dev_priv->uncore, GEN2_IIR); in i8xx_irq_handler()
4074 intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir); in i8xx_irq_handler()
4077 intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], iir); in i8xx_irq_handler()
4087 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in i8xx_irq_handler()
4094 struct intel_uncore *uncore = &dev_priv->uncore; in i915_irq_reset()
4098 …intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_STAT, intel_uncore_read(&dev_priv->uncore, PORT… in i915_irq_reset()
4104 dev_priv->irq_mask = ~0u; in i915_irq_reset()
4109 struct intel_uncore *uncore = &dev_priv->uncore; in i915_irq_postinstall()
4112 intel_uncore_write(&dev_priv->uncore, EMR, ~(I915_ERROR_PAGE_TABLE | in i915_irq_postinstall()
4116 dev_priv->irq_mask = in i915_irq_postinstall()
4133 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; in i915_irq_postinstall()
4136 GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask); in i915_irq_postinstall()
4138 /* Interrupt setup is already guaranteed to be single-threaded, this is in i915_irq_postinstall()
4140 spin_lock_irq(&dev_priv->irq_lock); in i915_irq_postinstall()
4143 spin_unlock_irq(&dev_priv->irq_lock); in i915_irq_postinstall()
4157 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in i915_irq_handler()
4165 iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR); in i915_irq_handler()
4182 intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir); in i915_irq_handler()
4185 intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], iir); in i915_irq_handler()
4198 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in i915_irq_handler()
4205 struct intel_uncore *uncore = &dev_priv->uncore; in i965_irq_reset()
4208 …intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_STAT, intel_uncore_read(&dev_priv->uncore, PORT… in i965_irq_reset()
4213 dev_priv->irq_mask = ~0u; in i965_irq_reset()
4218 struct intel_uncore *uncore = &dev_priv->uncore; in i965_irq_postinstall()
4235 intel_uncore_write(&dev_priv->uncore, EMR, error_mask); in i965_irq_postinstall()
4238 dev_priv->irq_mask = in i965_irq_postinstall()
4256 GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask); in i965_irq_postinstall()
4258 /* Interrupt setup is already guaranteed to be single-threaded, this is in i965_irq_postinstall()
4260 spin_lock_irq(&dev_priv->irq_lock); in i965_irq_postinstall()
4264 spin_unlock_irq(&dev_priv->irq_lock); in i965_irq_postinstall()
4273 lockdep_assert_held(&dev_priv->irq_lock); in i915_hpd_irq_setup()
4303 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in i965_irq_handler()
4311 iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR); in i965_irq_handler()
4327 intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir); in i965_irq_handler()
4330 intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], in i965_irq_handler()
4334 intel_engine_cs_irq(to_gt(dev_priv)->engine[VCS0], in i965_irq_handler()
4348 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); in i965_irq_handler()
4373 if (i915->display_irqs_enabled && i915->display.funcs.hotplug) in intel_hpd_irq_setup()
4374 i915->display.funcs.hotplug->hpd_irq_setup(i915); in intel_hpd_irq_setup()
4378 * intel_irq_init - initializes irq support
4386 struct drm_device *dev = &dev_priv->drm; in intel_irq_init()
4389 INIT_WORK(&dev_priv->l3_parity.error_work, ivb_parity_work); in intel_irq_init()
4391 dev_priv->l3_parity.remap_info[i] = NULL; in intel_irq_init()
4393 /* pre-gen11 the guc irqs bits are in the upper 16 bits of the pm reg */ in intel_irq_init()
4395 to_gt(dev_priv)->pm_guc_events = GUC_INTR_GUC2HOST << 16; in intel_irq_init()
4404 dev->vblank_disable_immediate = true; in intel_irq_init()
4406 /* Most platforms treat the display irq block as an always-on in intel_irq_init()
4412 dev_priv->display_irqs_enabled = true; in intel_irq_init()
4414 dev_priv->display_irqs_enabled = false; in intel_irq_init()
4416 dev_priv->display.hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD; in intel_irq_init()
4423 dev_priv->display.hotplug.hpd_short_storm_enabled = !HAS_DP_MST(dev_priv); in intel_irq_init()
4427 dev_priv->display.funcs.hotplug = &i915_hpd_funcs; in intel_irq_init()
4430 dev_priv->display.funcs.hotplug = &icp_hpd_funcs; in intel_irq_init()
4432 dev_priv->display.funcs.hotplug = &dg1_hpd_funcs; in intel_irq_init()
4434 dev_priv->display.funcs.hotplug = &gen11_hpd_funcs; in intel_irq_init()
4436 dev_priv->display.funcs.hotplug = &bxt_hpd_funcs; in intel_irq_init()
4438 dev_priv->display.funcs.hotplug = &icp_hpd_funcs; in intel_irq_init()
4440 dev_priv->display.funcs.hotplug = &spt_hpd_funcs; in intel_irq_init()
4442 dev_priv->display.funcs.hotplug = &ilk_hpd_funcs; in intel_irq_init()
4447 * intel_irq_fini - deinitializes IRQ support
4457 kfree(i915->l3_parity.remap_info[i]); in intel_irq_fini()
4536 * intel_irq_install - enables the hardware interrupt
4544 * workers. Hence the split into this two-stage approach.
4548 int irq = to_pci_dev(dev_priv->drm.dev)->irq; in intel_irq_install()
4556 dev_priv->runtime_pm.irqs_enabled = true; in intel_irq_install()
4558 dev_priv->irq_enabled = true; in intel_irq_install()
4565 dev_priv->irq_enabled = false; in intel_irq_install()
4575 * intel_irq_uninstall - finilizes all irq handling
4583 int irq = to_pci_dev(dev_priv->drm.dev)->irq; in intel_irq_uninstall()
4591 if (!dev_priv->irq_enabled) in intel_irq_uninstall()
4594 dev_priv->irq_enabled = false; in intel_irq_uninstall()
4601 dev_priv->runtime_pm.irqs_enabled = false; in intel_irq_uninstall()
4605 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4614 dev_priv->runtime_pm.irqs_enabled = false; in intel_runtime_pm_disable_interrupts()
4619 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4627 dev_priv->runtime_pm.irqs_enabled = true; in intel_runtime_pm_enable_interrupts()
4634 return dev_priv->runtime_pm.irqs_enabled; in intel_irqs_enabled()
4639 synchronize_irq(to_pci_dev(i915->drm.dev)->irq); in intel_synchronize_irq()
4644 synchronize_hardirq(to_pci_dev(i915->drm.dev)->irq); in intel_synchronize_hardirq()